19-07-24

Introduction to Digital Systems Design

with FPGAs

Lecture 3 - Processes, state machines and synthesis

Instructors:
Daniel Holanda Noronha, [email protected]
Cristian Grecu, [email protected]

Vancouver Summer Program

2019

What we will talk about today

● Understanding signals better

○ STD_LOGIC values
● More sequential logic
○ Definition of process
○ Moore and Mealy state machines
○ More process examples
○ Variables and Signals
○ Asynchronous vs. Synchronous Sets and Resets
○ Wait until/for
● Making VHDL synthesizable

1
 19-07-24

Understanding signals better - STD_LOGIC values

Understanding signals better - STD_LOGIC values

● STD_LOGIC will always have 1 of the following 9 values:

○ 'U': uninitialized.
■ This signal hasn't been set yet.
○ 'X': unknown or illegal value
■ This commonly happens if it is being driven to both 0 and 1 at
the same time.
■ Digital designers also use the symbol X to indicate “don’t care”
values in truth tables. Be sure not to mix up the two meanings.
● When X appears in a truth table, it indicates that the
value of the variable in the truth table is unimportant (can be
either 0 or 1).
● When X appears in a circuit, it means that the circuit node has
an unknown or illegal value.

2
 19-07-24

Understanding signals better - STD_LOGIC values

○ '0': logic 0
○ '1': logic 1
○ 'Z': High Impedance
■ The symbol Z indicates that a node is being driven neither HIGH nor
LOW.
■ The node is said to be floating, high impedance, or high Z.
■ Common ways to produce a floating node
● forget to connect a voltage to a circuit input
● Assume that an unconnected input is the same as an input with
the value of 0.
■ This mistake may cause the circuit to behave erratically as the
floating input randomly changes from 0 to 1.
■ Logic gates with possible outputs 0,1, and Z do exist and CAD tools
can synthesize such circuits
5

Understanding signals better - STD_LOGIC values

○ 'W': Weak signal

■ can't tell if it should be 0 or 1
○ 'L':
■ Weak signal that should probably go to 0
○ 'H':
■ Weak signal that should probably go to 1
○ '-': Don't care
■ If you assign a signal to be a "don't care" the tool will have more
chances to optimize the circuit that contains that signal

3
 19-07-24

What we will talk about today

● Understanding signals better

○ STD_LOGIC values
● More sequential logic
○ Definition of process
○ Moore and Mealy state machines
○ More process examples
○ Variables and Signals
○ Asynchronous vs. Synchronous Sets and Resets
○ Wait until/for
● Making VHDL synthesizable

More sequential logic - Definition of Process

4
 19-07-24

More sequential logic - Definition of Process

● The process construct will help us to describe the function or behaviour of a

circuit or subcircuit without describing the actual hardware
● We have already seen some sorts of behavioural descriptions:
○ Ex: X <= (B nand A) or C;
This describes the behaviour of the circuit driving X without necessarily
specifying the actual hardware implementation using gates

But we are going to take this MUCH further and describe circuits
at a much higher level.

More sequential logic - Definition of Process

● Process syntax
...
process (sensitivity_list)
begin
statements
end process;
...

● Each process describes the function of one piece of hardware

○ Statements within a process are executed sequentially
○ Different processes in a VHDL description are executed concurrently

10

5
 19-07-24

More sequential logic - Definition of Process

...
● The sensitivity list process (sensitivity_list)
begin
○ Is a list of signals statements
○ A change in value on one or more of these end process;
...
signals, causes the process to be activated
○ Example:
process(clk)
defines the start of a process that is
"executed" whenever CLK changes

11

More sequential logic - Definition of Process

● Example: Flip-flop using a process

library ieee;
use ieee.std_logic_1164.all;

entity MY_ENTITY is
port(clk: in STD_LOGIC;
d: in STD_LOGIC_VECTOR(3 downto 0);
rising_edge(clk)
q: out STD_LOGIC_VECTOR(3 downto 0)); is the same as
end MY_ENTITY; clk'event and clk = '1'
architecture MY_ARCH of MY_ENTITY is
begin
process(clk) begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end MY_ARCH; 17

6
 19-07-24

More sequential logic - Moore and Mealy

● Moore machine
○ Output depends only on the current state of the machine only
● Mealy machine
○ Output depends on both the current state and input(s).

18
Both of these images show a Moore state machine, since the output only depends on current state

More sequential logic - Moore & Mealy State Machines

Moore Mealy

● Moore SM are preferable due to simplicity and

predictability (outputs change value on the active edge
of the clock)

7
 19-07-24

More sequential logic - Moore and Mealy

● Moore machine:
...
architecture MY_ARCH of MY_ENTITY is
begin
process (clk)
variable PRESENT_STATE : bit_vector(1 downto 0) := "00";
begin
if (clk’event and clk = '1') then
case PRESENT_STATE is
when "00" => PRESENT_STATE := "01";
when "01" => PRESENT_STATE := "10";
when "10" => PRESENT_STATE := "11";
when "11" => PRESENT_STATE := "00";
end case;
Z <= PRESENT_STATE; -- update output Z
end if;
end process;
end MY_ARCH; 25

More sequential logic - Moore and Mealy

● Moore machine:
architecture MY_ARCH of MY_ENTITY is
begin
process (clk)
type state_set is (StateInit, StateWait, StateSample, StateDisplay);
variable PRESENT_STATE : state_set;
begin
if (clk’event and clk = '1') then
● To make code more readable, you can
define enumerated types
case PRESENT_STATE is
when StateInit => PRESENT_STATE := StateWait;
● Here, we have defined a variable
when StateWait => PRESENT_STATE := StateSample; called CURRENT_STATE that
when StateSample => PRESENT_STATE := StateDisplay; can take on one of four values:
when StateDisplay => PRESENT_STATE := StateInit; StateLive, StateWait, StateSimple,
end case; StateDisplay.
Z <= PRESENT_STATE; -- update output Z
end if;
end process; After synthesis, there will be two bits for each signal
end MY_ARCH; 26

8
 19-07-24

More sequential logic - Moore and Mealy

● Another Moore machine:
entity MY_ENTITY is when Sb => if (INPUT = '0') then
port ( INPUT, CLK : in std_logic; NEXT_STATE := Sb;
Z : out std_logic); else
end MY_ENTITY; NEXT_STATE := Sc;
architecture MY_ARCH of MY_ENTITY is end if;
begin -- same for Sc and Sd
process(CLK) end case;
type state_types is (Sa, Sb, Sc, Sd); PRESENT_STATE := NEXT_STATE;
variable PRESENT_STATE : state_types := Sa; case NEXT_STATE is
variable NEXT_STATE : state_types; when Sa => Z<='0';
begin when Sb => Z<='1';
if (clk’event and clk = '1') then when Sc => Z<='1';
case PRESENT_STATE is when Sd => Z<='0';
when Sa => if (INPUT = '0') then end case;
NEXT_STATE := Sa; end if;
else end process;
NEXT_STATE := Sb; end MY_ARCH;
end if;

27

More sequential logic - More process examples

● Using process to define combinational logic
entity MY_ENTITY is
port ( S : in std_logic_vector(1 downto 0);
D0, D1, D2, D3 : in std_logic;
Y : out std_logic);
end MY_ENTITY;
architecture MY_ARCH of MY_ENTITY is
begin
process(Sel, D0, D1, D2, D3)
begin
if (S="00") then
Y <= D0;
elsif (S="01") then
Y <= D1;
elsif (S="10") then
Y <= D2;
else
Y <= D3;
end if;
end process;
end MY_ARCH;

28

9
 19-07-24

More sequential logic - More process examples

● Using process to define something more complex

● Operation is as follows:
○ If Reset is 1, the value in the register is set to 0, regardless of clock
(asynchronously)
○ Otherwise, on each rising edge of the clock
■ if load is 1, load in value from D into register
■ otherwise, rotate value in register one bit to the right
29

More sequential logic - More process examples

● Using process to define something more complex
library ieee; elsif (clk='1' and clk'event) then
use ieee.std_logic_1164.all; if (load='1') then
myVar := d;
entity MY_ENTITY is else
port( clk, reset, load : in std_logic; myVar := myVar(0) & myVar(7 downto 1);
d : in std_logic_vector(7 downto 0); end if;
q : out std_logic_vector(7 downto end if;
0)); q <= myVar;
end MY_ENTITY; end process;
architecture MY_ARCH of MY_ENTITY is end MY_ARCH;
begin
process(reset, clk)
variable myVar : std_logic_vector (7 downto 0);
begin
if (reset = '1') then
myVar := "00000000";

30

10
 19-07-24

More sequential logic - More process examples

● By the way...

library ieee;
use ieee.std_logic_1164.all; Any concurrent statements not inside a
process are also considered processes
entity MY_ENTITY is
port (A, B,C,D : in STD_LOGIC;
X,Y,Z : out STD_LOGIC);
end MY_ENTITY;
architecture MY_ARCH of MY_ENTITY is
begin
X <= A and B and C;
Y <= C and not D; These statements are treated as three processes
Z <= A xor B xor D;
end MY_ARCH;
The "sensitivity list" is made of all signals of
the assignment
In this case: A, B and D
31

More sequential logic - More process examples

● Is your whole design a single process?

○ Normal design process:
■ divide your design into small blocks, and write a process for each
one.
■ Splitting it makes it simpler to understand and test
○ Each process is a single combinational or sequential block
○ Each process is “compiled” independently (in most tools)

32

11
 19-07-24

More sequential logic - Variables and Signals

● Signals:
○ Used to transmit data between processes
● Variables:
○ Used within a process to help describe behaviour

Note: There are things called “shared variables” but don’t use them.
33

More sequential logic - Variables and Signals

● Note:
○ All inputs and outputs of a Process are signals.

34

12
 19-07-24

More sequential logic - Variables and Signals

● Example form earlier

...
architecture MY_ARCH of MY_ENTITY is The variable PRESENT_STATE could
begin not be accessed outside this process.
process (clk)
variable PRESENT_STATE : bit_vector(1 downto 0) := "00";
begin But Z (signal) could be accessed from
if (clk’event and clk = '1') then outside the process.
case PRESENT_STATE is
when "00" => PRESENT_STATE := "01";
when "01" => PRESENT_STATE := "10";
when "10" => PRESENT_STATE := "11";
when "11" => PRESENT_STATE := "00";
end case;
Z <= PRESENT_STATE; -- update output Z
end if;
end process;
end MY_ARCH;

35

More sequential logic - Variables and Signals

● Example form earlier

...
architecture MY_ARCH of MY_ENTITY is ● Updating Variables
begin ○ Variables are updated
process (clk) immediately when using :=
variable PRESENT_STATE : bit_vector(1 downto 0) := "00"; ○ As soon as one of these is
begin “executed”,
if (clk’event and clk = '1') then PRESENT_STATE is
case PRESENT_STATE is updated
when "00" => PRESENT_STATE := "01";
when "01" => PRESENT_STATE := "10";
when "10" => PRESENT_STATE := "11"; ● Updating signals
when "11" => PRESENT_STATE := "00"; ○ Z is updated once we finish
end case; the process (in this case, it
Z <= PRESENT_STATE; -- update output Z is the last statement in the
end if; process)
end process;
end MY_ARCH; 36

13
 19-07-24

More sequential logic - Variables and Signals

● Example ● Updating Signals

○ Signals z and w get updated at
... the same time, at the end of
architecture MY_ARCH of MY_ENTITY is the process
signal x, y, z, w: std_logic;
process(x,y)
begin ● Strange thing:
z <= x and y; ○ The assignment to w uses the
w <= z or y;
end process; old value of z, not the new
end MY_ARCH; value!
○ That is because z is not
updated until the end of the
process.

● What we learned:
○ Don’t use a signal to
communicate within a process

37

More sequential logic - Asynchronous vs. Synchronous

● A flip-flop (or a sequential circuit in general) can have either a synchronous or

asynchronous reset
○ Asynchronous Reset:
■ When the reset signal is high, the flip-flop is reset (forced to ‘0’)
immediately, regardless of the clock.
○ Synchronous Reset:
■ On a rising clock edge, if the reset signal is high,
the flip-flop is reset (forced to ‘0’).
■ Reset can happen on either positive or negative edge of the clock
■ Active reset signal can be either high or low (depending on how the
designers defines it)

38

14
 19-07-24

More sequential logic - Asynchronous vs. Synchronous

Asynchronous flip-flop Synchronous flip-flop

... ...
architecture MY_ARCH of MY_ENTITY is architecture MY_ARCH of MY_ENTITY is
begin begin
process (clk, reset) process (clk)
begin begin
if (reset = '1') then if (clk='1' and clk'event) then
Q <= '0'; if (reset = '1') then
elsif (clk='1' and clk'event) then Q <= '0';
Q <= D; else
end if; Q <= D;
end process; end if;
end MY_ARCH; end if;
end process;
end MY_ARCH;

39

More sequential logic - Asynchronous vs. Synchronous

Time for assignment 1

40

15
 19-07-24

More sequential logic - Wait until/for

● Wait until
○ The wait until form suspends a process until a change occurs on one or
more of the signals in the statement and the condition is evaluated to be
true.
process
process(A) begin
begin wait until A'event;
-- sequential -- sequential
statements statements
end process; end process;

○ Those processes have the same effect

41

More sequential logic - Wait until/for

● Wait for
○ Wait for and wait are useful in behavioural models and test benches.
○ Wait on it's own suspends a process indefinitely
○ Example inside of a testbench (we will learn more about testbenches
later)

…
EN_1 <= '0';
EN_2 <= '1';
wait for 10 ns;
EN_1 <= '1';
EN_2 <= '0';
wait for 10 ns;
EN_1 <= '0';
wait for 10 ns;
wait; -- end of test
...
42

16
 19-07-24

More sequential logic - Wait until/for

● Most logic synthesis tools only support a single wait until

● Wait for and wait statements are only simulation
● A process may have either a WAIT statement or a sensitivity list, but not
both!

43

What we will talk about today

● Understanding signals better

○ STD_LOGIC values
● More sequential logic
○ Definition of process
○ Moore and Mealy state machines
○ More process examples
○ Variables and Signals
○ Asynchronous vs. Synchronous Sets and Resets
○ Wait until/for
● Making VHDL synthesizable

44

17
 19-07-24

Making VHDL synthesizable

45

Making VHDL synthesizable

● We talked about “Process”: the most important concept in VHDL.

○ Right way to describe hardware:
■ Each “piece of hardware” corresponds to a process
■ Within a process, you can use variables to store temporary results
■ Variables can be used in a process to describe sequential behaviour
(describe hardware using algorithmic, software-like statements)
■ Variables only have lifetime within a process.
■ Signals are only used to communicate between processes.

46

18
 19-07-24

Making VHDL synthesizable

● Most important thing:

○ When you are describing hardware in VHDL, you are only describing the
behaviour.
○ The actual circuit will be synthesized (by the tools, eg. Quartus II) to gates
(and gates are transformed to a bitstream).
○ The FPGA then implements the gates.
○ The FPGA does NOT execute the VHDL code directly!!!!

47

Making VHDL synthesizable

This is likely the most important slide set of all.

● If you learn VHDL from a book, write your code using the constructs they
describe, and try to compile it to a hardware (FPGA, ASIC), it probably won’t
work!
○ I’ll tell you in this slide set, and also talk about how to make sure it
does work

Why is this the most important slide set of all?

Because, it will save you tons of debugging time in the lab if you
understand it.

48

19
 19-07-24

Making VHDL synthesizable

● Synthesis
○ Converting VHDL to gates in a netlist
● Netlist
○ List of nets or wires that connect gate outputs to other
gate inputs
● Map
○ In which component to put this gate?
Memory? LUT? DSP?
● Place
○ There are many of those components in the FPGA
○ In which of those should I put each specific gate?
● Route
○ How to connect the placed components
● Bitstream
○ What actually goes in the FPGA to configure it
49

Making VHDL synthesizable

● What do you think it happens if the synthesis tool cannot make
hardware for your VHDL? Two things can happen
○ Option 1 - Your circuit won’t implement the behaviour you
specified
○ Option 2 - If you are lucky, you get an error message

50

20
 19-07-24

Making VHDL synthesizable

● Not all VHDL code can be synthesized by current tools.

○ This isn’t limited to our tools (Quartus )

● If you write VHDL that is not synthesizable:

○ Tools will not be able to create hardware
○ Sometimes it will try, but end up with something that is “not quite right”
○ Sometimes you get an error message, sometimes you don’t!

● In the next few slides, I am going to show you the types of VHDL code that
synthesizable by all tools.
○ If you restrict your VHDL to those types of code, your code will be
synthesizable by all tools

51

Making VHDL synthesizable

● To make sure your VHDL is synthesizable, every process must be one of three
types:

Type 1: Purely Combinational:

○ All outputs are a function only of the current inputs (not on the previous
inputs)

process (SEL, A, B)
begin
if (SEL = ‘0’) then
Y <= A;
else
Y <= B;
end if;
end process;

52

21
 19-07-24

Making VHDL synthesizable

● To make sure your VHDL is synthesizable, every process must be one of three
types:

Type 1: Purely Combinational:

○ All outputs are a function only of the current inputs (not on the previous
inputs)

process (SEL, A, B) Rule 1: Every input (that can affect the

begin outputs) must be in the sensitivity list.
if (SEL = ‘0’) then
Y <= A;
else Rule 2: Every output must be assigned
a value for every possible combination
Y <= B;
end if; of the inputs.
end process;

53

Making VHDL synthesizable

This could not be synthesizable.

Why?

process (A, B)
begin
if (SEL = ‘0’) then
Y <= A; Rule 1: Every input (that can affect the
else outputs) must be in the sensitivity list.
Y <= B;
end if;
end process; Rule 2: Every output must be assigned
a value for every possible combination
of the inputs.

54

22
 19-07-24

Making VHDL synthesizable

This could not be synthesizable.

Why?

process (SEL,A, B)
begin
if (SEL = ‘0’) then Rule 1: Every input (that can affect the
Y <= A; outputs) must be in the sensitivity list.
end if;
end process;
Rule 2: Every output must be assigned
a value for every possible combination
of the inputs.

56

Making VHDL synthesizable

● To make sure your VHDL is synthesizable, every process must be one of three
types:

Type 2: Purely synchronous:

○ Every output of the process changes only on the rising or falling edge of a
single clock

process (CLK) Rule 1: Only the clock signal should be

begin in the sensitivity list
if (CLK’event and CLK=‘1’) then
Z <= A and B;
end if; Rule 2: Only signals that change on the
end process; same edge of the same clock should be
part of the same process

58

23
 19-07-24

Making VHDL synthesizable

● To make sure your VHDL is synthesizable, every process must be one of three
types:

Type 3: Same thing as before, but with asynchronous reset:

○ Every output of the process changes only on the rising or falling edge of a
single clock

process (CLK, RESET) Rule 1: Sensitivity list includes clock and

begin set/reset signal
if (RESET = ‘1’) then
Z <= ‘0’;
elsif (CLK’event and CLK=‘1’) then Rule 2: Need the clk’event clause
Z <= A and B; (to be edge triggered)
end if;
end process;

59

Making VHDL synthesizable

● If you want to synthesize your circuit, every process must fall exactly into one of
these categories.
● What if I have a big process that will not fit in any of the three types?
○ You need to break it up into blocks, where each block does fit into one of
these types.

(note: I am being a little bit conservative here… some synthesizers will

handle a few patterns not described here. But don’t count on it).

60

24
 19-07-24

Making VHDL synthesizable

● Summary
○ Make sure every process is one of these three types:
■ Type 1: Purely Combinational
■ Type 2: Purely Synchronous
■ Type 3: Purely Synchronous with async set/reset

If you do so, your code will be synthesizable.

If you don’t, there is a good chance your circuit won’t work.

Remember this when debugging:

● for each process:
- Identify which of the three types it is
- For that type, follow the pattern in this slide set,
exactly.
○ Bonus: if you ever learn Verilog, the rules above apply identically to Verilog
(but different syntax, of course) 61

Making VHDL synthesizable

● Time for assignment sheet 2

62

25
 19-07-24

What we talked about today

● Understanding signals better

○ STD_LOGIC values
● More sequential logic
○ Definition of process
○ Moore and Mealy state machines
○ More process examples
○ Variables and Signals
○ Asynchronous vs. Synchronous Sets and Resets
○ Wait until/for
● Making VHDL synthesizable

63

26