19-07-25

Introduction to Digital Systems Design

with FPGAs

Lecture 4 - Counters and Timing

Instructors: Daniel Holanda Noronha, [email protected]

Cristian Grecu, [email protected]

Vancouver Summer Program

2019

What we will talk about today

● Logic minimization, basic concepts

● Signed vs. Unsigned in VHDL
○ How to deal with signed and unsigned numbers
● Common sequential circuits
○ Shift Registers
○ Counters
○ Linear-Feedback Shift Registers (LFSRs)
● Timing
○ FMax and critical path
○ Setup and hold time
○ Metastability

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Logic minimization - basic concepts

Logic minimization - basic concepts

● During the last lectures many of you came up with different combinational
circuits, but often they were all right (had the same behaviour)
○ If different circuits can have the same behaviour, which circuit is the best
one to implement?
■ Answer: The smallest one!

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Logic minimization - basic concepts

● There are different ways to manipulate logic expressions

+ -> or . -> and ' -> not

Don't worry this for now, just be aware that this exists
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Important basic concepts - Logic minimization

● Simple example
○ (P AND NOT A) OR (P AND A) = P AND (A AND NOT A) = P

A P P AND NOT A P AND A (P AND NOT A) OR (P AND A)

0 0 0 0 0

0 1 1 0 1

1 0 0 0 0

1 1 0 1 1

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Logic minimization - basic concepts

● Karnaugh maps
○ A graphical method to do logic minimization
○ Works well for problems with up to four variables

Logic minimization - basic concepts

● Karnaugh map rules:

○ Use the fewest circles necessary to cover all the 1’s
○ All the squares in each circle must contain only 1’s
○ Each circle must span a rectangular block that is a power of 2 (i.e.,
1, 2, or 4) squares in each direction
○ Each circle should be as large as possible
○ A circle may wrap around the edges of the K-map
○ A 1 in a K-map may be circled multiple times

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Logic minimization - basic concepts

● Karnaugh map example with 3 variables:

Logic minimization - basic concepts

● Another Karnaugh map example with 3 variables:

Y = (A'.B)+ (A.C')+ (A.B')

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Logic minimization - basic concepts

● Another Karnaugh map example with 3 variables:

Y = (A.C')+ B'

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Important basic concepts - Logic minimization

● Is this a part of the daily job of an engineer that works with digital design?
○ No! The tools do that for you now!
This means that if The tool will
you write the VHDL probably implement
for this something like this

● Does that mean that it doesn't really matter how I write VHDL?
○ No! The tool can do simple logic minimization, but we are responsible for
creating larger designs that are efficient (especially in RTL level)
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What we will talk about today

● Logic minimization - basic concepts

● Signed vs. Unsigned in VHDL
○ How to deal with signed and unsigned numbers
● Common sequential circuits
○ Shift Registers
○ Counters
○ Linear-Feedback Shift Registers (LFSRs)
● Timing
○ FMax and critical path
○ Setup and hold time
○ Metastability

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Signed vs. Unsigned in VHDL

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Signed vs. Unsigned in VHDL

● All Digital Designers must understand how math works inside of an FPGA
● The first step to that is understanding how signed and unsigned signal types
work
○ Signed and unsigned types exist in the numeric_std package
○ A signal that is defined as type signed means that the tools interpret this
signal to be either positive or negative
○ A signal that is defined as type unsigned means that the signal will be
only positive.
○ Internally, the FPGA will use Two's Complement representation.

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Signed vs. Unsigned in VHDL

● Example
○ A 3-bit signal can be interpreted according to the table below:

Note: To convert from negative to positive (and vice versa) invert all bits and add 1 16

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Signed vs. Unsigned in VHDL

● Unintuitive thing:
○ Whether or not the signals are defined as signed or unsigned does not
affect how some of the actual binary math is performed

● Unsigned example:
○ Lets calculate 4 (which is 100) + 2 (which is 010)
■ 100 + 010 = 110
● Converting back to decimal: 110 -> 6
○ Result is right!
● Signed value
○ Lets calculate -4 (which is 100) + 2 (which is 010)
■ 100 + 010 = 110
● Converting back to decimal: 110-> -2
○ Result is right!
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Signed vs. Unsigned in VHDL

● If the math is the same, what does the library do?

○ Correctly converts from bits to signed/unsigned
○ Takes care of other operations that are different between those types
■ Ex: evaluate if (111 > 001)
● True using unsigned logic (7 > 1 -> true)
● False using Signed logic (-1 > 1 -> false)

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Signed vs. Unsigned in VHDL

● How to use this package?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

● How to declare a variable?

signal my_unsigned_signal : unsigned(3 downto 0);

signal my_signed_signal : signed(3 downto 0);

● How to perform operations?

○ You will learn with some examples in this lecture

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What we will talk about today

● Logic minimization - basic concepts

● Signed vs. Unsigned in VHDL
○ How to deal with signed and unsigned numbers
● Common sequential circuits
○ Shift Registers
○ Counters
○ Linear-Feedback Shift Registers (LFSRs)
● Timing

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Common Sequential Circuits

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Common Sequential Circuits

● So now we know how to design with flip-flops and registers, and we know
how to specify such circuits in VHDL.
● Using the state machine design techniques, you can design any state machine
○ You already know how to describe any of them in behavioural VHDL.
● However, there are some very common sequential circuits that are used so
often, they are worth talking about separately.
○ Shift Registers
○ Counters
○ Linear-Feedback Shift Registers (LFSR’s)

Textbook: Sections 7.8 - 7.12

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Common Sequential Circuits - Shift Registers

● A shift register is a cascade of flip flops that:

○ Shares the same clock AND
The output of each flip-flop is connected to the 'data' input of the next flip-
flop
■ This results in a circuit that shifts by one position the 'bit array' stored
in it

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Common Sequential Circuits - Shift Registers

● Writing the VHDL code for shift register
entity MY_ENTITY is
port( clk, insig : in std_logic;
outsig : out std_logic; INSIG
end MY_ENTITY;
architecture MY_ARCH of MY_ENTITY is
begin
process(CLK)
variable int_value : std_logic_vector (3 downto 0);
begin
if (clk='1' and clk'event) then
int_value := insig & int_value(3 downto 1);
outsig <= int_value(0);
end if;
end process;
end MY_ARCH;

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Common Sequential Circuits - Shift Registers

● Shift Register with Parallel Input

○ It is a shift register that we can load all variables in parallel!

INSIG

If LOAD = 1: Loads a 4-bit value into the register

If LOAD = 0: Operates as a normal shift register
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Common Sequential Circuits - Shift Registers

● Writing the VHDL code for shift register
entity MY_ENTITY is
port( clk, insig, load : in std_logic;
parallel_in : in std_logic_vector (3 downto 0);
outsig : out std_logic);
end MY_ENTITY;
INSIG
architecture MY_ARCH of MY_ENTITY is
begin
process(CLK)
variable int_value : std_logic_vector (3 downto 0);
begin
if (clk='1' and clk'event) then
if (load = '1' ) then
int_value := parallel_in;
else
int_value := insig & int_value(3 downto 1);
end if;
outsig <= int_value(0);
end if;
end process;
end MY_ARCH;

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Common Sequential Circuits - Counters

● Why use counters?

○ Keeping track of time
■ Ex: Build a machine that sprays a fragrance in the air every 30min
■ Oscillator (what produces the clock) needs to be good enough
○ Create clock dividers
■ Ex: Our lab1
○ Object or event counting
■ Ex: Counting the number of cars that crossed an intersection

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Common Sequential Circuits - Counters

● There are many ways to do a counter and many different kinds of counters
● We can actually make a counter using a Moore state machine

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Common Sequential Circuits - Counters

● Moore state machine with synchronous reset

...
architecture MY_ARCH of MY_ENTITY is
begin
process (clk)
variable PRESENT_STATE : bit_vector(2 downto 0) := "000"; when "101" => PRESENT_STATE := "110";
begin when "110" => PRESENT_STATE := "111";
if (clk’event and clk = '1') then when "111" => PRESENT_STATE := "000";
if (reset = '1') then end case;
PRESENT_STATE := "000"; else
elsif (enable='1') then -- Not needed since it is type 2, but nice
case PRESENT_STATE is PRESENT_STATE := PRESENT_STATE;
when "000" => PRESENT_STATE := "001"; end if;
when "001" => PRESENT_STATE := "010"; Z <= PRESENT_STATE; -- update output Z
when "010" => PRESENT_STATE := "011"; end if;
when "011" => PRESENT_STATE := "100"; end process;
when "100" => PRESENT_STATE := "101"; end MY_ARCH;
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Common Sequential Circuits - Counters

● Simulating behavioral description
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MY_ENTITY is
port( clk, enable, reset : inout std_logic;
count : out unsigned(2 downto 0));
end MY_ENTITY;
architecture MY_ARCH of MY_ENTITY is Process -- Used for simulation only
begin begin
process (clk) enable <= '0';
variable unsigned_value : unsigned (2 downto 0) := "000"; reset <= '0';
begin wait for 40 ps;
if (reset='1') then enable <= '1';
unsigned_value := "000"; wait for 300 ps;
elsif (clk='1' and clk'event) then enable <= '0';
if (enable = '1') then wait for 35 ps;
unsigned_value := unsigned_value + 1; reset <= '1';
end if; wait for 35 ps;
end if; reset <= '0';
count <= unsigned_value; wait;
end process; end process;
end MY_ARCH; 51

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Common Sequential Circuits - Counters

● Simulating behavioral description

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Common Sequential Circuits - Counters

● Problem with binary counters
○ They are normally implemented like this at gate level

● They are slow!

○ The length of one clock period is

the length of the longest path

○ If we have many bits, the

longest path is way too long!

○ Solution: Use a one-hot counter

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Common Sequential Circuits - Counters

● One-hot counter
○ Count:
It is a circular shift register!
100000000 > 01000000 > 00100000 > etc. (with some minor differences)
○ Advantage:
■ fast counting
○ Disadvantage:
■ more flip-flops

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Common Sequential Circuits - Counters

● One-hot counter
○ Initialization
■ Initialize one flip-flop to 1, and the others to 0

1 0 0 0 0

0 0 0

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Common Sequential Circuits - LFSR

● Linear Feedback Shift Register (LFSR)

○ In computing, a linear-feedback shift register (LFSR) is a shift register
whose input bit is a linear function of its previous state
○ Main applications:
■ pseudo-random number generator
■ Fast digital counter

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Common Sequential Circuits - LFSR

● Linear Feedback Shift Register (LFSR) as a fast digital counter

○ Advantages
■ Fast and small
○ Disadvantages
■ Counts in a weird sequence and always has a dead state (never reached in
normal operation)

Count Sequence:
0000 -> 1000 -> 1100 -> 1110 -> 0111 -> 1011 ->1101 -> 0110 -> 0011 ->
1001 -> 0100 ->1010 -> 0101 -> 0010 -> 0001 -> repeat 65
Counts through 15 numbers, but in a strange order

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Common Sequential Circuits - LFSR

● Linear Feedback Shift Register (LFSR) as a pseudo-random number generator

○ An LFSR with a well-chosen feedback function can produce a sequence of bits
that appears random and has a very long cycle.
○ The initial value of the LFSR is called the seed
○ The operation of the register is deterministic (this is why it is a PSEUDO-random
generator)

How to choose the initial seed?

In a computer often the current time is used as a seed
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Common Sequential Circuits - LFSR

● Time for assignment 1

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What we will talk about today

● Important basic concepts

○ Logic minimization
● Signed vs. Unsigned in VHDL
○ How to deal with signed and unsigned numbers
● Common sequential circuits
○ Shift Registers
○ Counters
○ Linear-Feedback Shift Registers (LFSRs)
● Timing
○ FMax and critical path
○ Setup and hold time
○ Metastability
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Timing

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Timing

● Is very important to understand timing to handle two things

○ Know how to make your circuit run faster
○ Diagnose time related problems (as we will see in the next slides)

● Some important concepts related to timing

○ fMax and critical path
○ Set-up and hold time
○ Metastability

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Timing - fMax and critical path

● Maximum Frequency (fMax)

○ It is the maximum frequency that the clock is able toggle without "breaking" the
logic of the circuit
○ It is calculated automatically by the tool during synthesis
○ Cannot be higher than maximum FPGA frequency (normally 400-700 MHz)
○ Depends on:
■ FPGA technology (7nm, 10nm, etc.)
■ Number of gates in a single path (more gates → longer delay)
■ How gates are routed (takes time to go through long wires)

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Timing - fMax and critical path

● Critical path
○ The longest path between any inputs, outputs and flip-flops
○ Ex: What is the longest delay in this combinational circuit assuming that all gates
take 1ns and wires transmit data instantaneously (wire delay is zero)?

○ The maximum frequency is then given by 1/critical_path = 1/5ns = 200 MHz

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Timing - fMax and critical path

● Critical path
In other words, in the previous circuit, if we apply all inputs at time 0,
then by time 5ns, all the outputs have settled to their final values.

Note: 1. Some outputs might settle earlier

2. Some outputs may switch back and forth a few times before
settling to a final value
3. Although there is a maximum frequency there is no minimum frequency
(You can run the circuit at 1Hz if you want to)

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Timing - Setup and hold time

● All registers in digital devices (such as FPGAs) have defined signal timing requirements
○ Those requirements need to be met to allow registers to correctly capture data
● Setup time (tsu)
○ Time that the input should remain stable before the clock edge arrival
● Hold time (thold)
○ Time that the input should remain stable after the clock edge arrival
● Clock-to-output-delay (Clk-to-Q delay)
○ Time required for output to be available after setup time
If the data doesn't arrive tsu
before the clock edge or it
is not held for more than
thold the flip-flop might not
be able to record the right
value.

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Timing - Metastability

● Definition
○ Metastability is a phenomenon that can cause system failure in digital devices,
including FPGAs
○ If a data signal transition violates a register’s tsu or thold requirements, the output
of the register may go into a metastable state.
○ In a metastable state, the register output hovers at a value between the high and
low states for some period of time
■ This means the output transition to a defined high or low state is delayed
beyond the specified tCO.

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Timing - Metastability

● Understanding metastability

Case II Case I Case III

What can happen

when we have
metastability 76

What we talked about today

● Time for assignment 2

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What we talked about today

● Important basic concepts

○ Logic minimization
● Signed vs. Unsigned in VHDL
○ How to deal with signed and unsigned numbers
● Common sequential circuits
○ Shift Registers
○ Counters
○ Linear-Feedback Shift Registers (LFSRs)
● Timing
○ FMax and critical path
○ Setup and hold time
○ Metastability

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