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Lab07 Coverage

The document discusses coverage testing for a finite state machine design. It describes testing the output signals and states of the FSM using a covergroup. It creates coverpoints for the output values and current state to achieve high coverage.

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Mohamed Alahmady
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16 views3 pages

Lab07 Coverage

The document discusses coverage testing for a finite state machine design. It describes testing the output signals and states of the FSM using a covergroup. It creates coverpoints for the output values and current state to achieve high coverage.

Uploaded by

Mohamed Alahmady
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab 07: Coverage

Mohamed Khaled Alahamdy v23010489


Mohamed Niazy Hassanein v23010512

• Testbench
module tb();
bit clk, reset;
logic in;
logic [2:0] out;
typedef enum { S0=0, S1, S2, S3} states;
FSM u_FSM (.*);
initial begin
forever #5 clk = ~clk;
end

covergroup cg @(posedge clk);


cover_point_out: coverpoint out{
bins zero = {0};
bins one = {1};
bins three = {3};
bins seven = {7};
bins d = default;
}
cover_point_state: coverpoint u_FSM.current_state{
}

endgroup

initial begin
cg cg_inst = new();
reset = 1'b1;
#10;
reset = 1'b0;
in = 1'b0;
#40;
in = 1'b1;
#60;
$finish();
end
endmodule
© CND
Lab 07: Coverage
• Output Signal Coverage

© CND
Lab 07: Coverage
• State and State Transition Coverage

© CND

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