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Xlinkslib

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8 views8 pages

Xlinkslib

Uploaded by

rudrarudrahara
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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module srflipflop(s, r, clk, q, qb);

input s;
input r;
input clk;
output q;
output qb;
reg q,qb;
always@(posedge clk)
begin
if(s==0&r==0)
q=0;
else if(s==0&r==1)
q=0;
else if(s==1&r==0)
q=1;
else if(s==1&r==1)
q=1'bx;
qb=~q;
end
endmodule

module jk(j,k,clk, q,qb);


input j,k,clk;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
q=(j&(~q)|(~k)&q);
qb=~q;
end
endmodule

module dff(d,clk, q,qb);


input d,clk;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
q=d;
qb=~q;
end
endmodule

module count(clk,res, q);


input clk,res;
output [3:0] q;
reg [3:0] q=4'b0000;
always@(posedge clk)
begin
if(res==0)
q=q+1'b1;
else
q=q-1'b1;
end
endmodule
module bit(a,b, cin, s, cout);
input [3:0] a,b;
input cin;
output [3:0] s;
output cout;
wire c0,c1,c2;
fa stage0(cin,a[0],b[0],s[0],c0);
fa stage1(c0,a[1],b[1],s[1],c1);
fa stage2(c1,a[2],b[2],s[2],c2);
fa stage3(c2,a[3],b[3],s[3],cout);
endmodule
module fa(x,y,z,sum,carry);
input x,y,z;
output sum,carry;
assign sum=x^y^z;
assign carry=(x&y)|(y&z)|(z&x);
endmodule

module alu(a,b, opcode, en, y, y_mul);


input [31:0] a,b;
input [2:0] opcode;
input en;
output [31:0] y;
output [63:0] y_mul;
reg [31:0] y;
reg [63:0] y_mul;
always @(a,b,opcode)
begin
if (en==1)
case (opcode)
3'd0: y = a+b;
3'd1: y= a-b;
3'd2: y = a%b;
3'd3: y = a|b;
3'd4: y = a&b;
3'd5: y_mul = a*b;
3'd6: y = a^b;
3'd7: y = ~(a|b);
endcase
end
endmodule
Test bench code
module srfipflop_v;
reg s;
reg r;
reg clk;
wire q;
wire qb;
srflipflop uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
s = 0;
r = 0;
clk = 0;
end
initial begin
forever begin
#10 clk=~clk;
end
end
initial begin
s=0;r=0;
#20 $display("q=%b,qb=%b",q,qb);
s=0;r=1;
#20 $display("q=%b,qb=%b",q,qb);
s=1;r=0;
#20 $display("q=%b,qb=%b",q,qb);
s=1;r=1;
#20 $display("q=%b,qb=%b",q,qb);
end
endmodule

module jkflipflop_v;
reg j;
reg k;
reg clk;
wire q;
wire qb;
jk uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
j = 0;
k = 0;
clk = 0;
end
initial begin
forever begin
#10 clk=~clk;
end
end
initial begin
j=0;k=0;
#20 $display("q=%b,qb=%b",q,qb);
j=0;k=1;
#20 $display("q=%b,qb=%b",q,qb);
j=1;k=0;
#20 $display("q=%b,qb=%b",q,qb);
j=1;k=1;
#20 $display("q=%b,qb=%b",q,qb);
end
endmodule

module dflipflop_v;
reg d;
reg clk;
wire q;
wire qb;
dff uut (
.d(d),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
d = 0;
clk = 0;
end
initial begin
forever begin
#10 clk=~clk;
end
end
initial begin
d=0;
#20 $display ("q=%b,qb=%b",q,qb);
d=1;
#20 $display ("q=%b,qb=%b",q,qb);
end
endmodule

module Asynchronouscounter_v;
reg clk;
reg res;
wire [3:0] q;
count uut (
.clk(clk),
.res(res),
.q(q)
);

initial begin
clk = 0;
res = 0;
end
initial begin
forever begin
#5 clk=~clk;
end
end
initial begin
res=0;
$monitor("q=%d",q);
#160 res=1;
$monitor("q=%d",q);
#160 $finish;
end
endmodule

module 4bitadder_v;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] s;
wire cout;
bit uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout)
);
initial begin
a = 0;
b = 0;
cin = 0;
end
initial begin
a=4'b0101 ; b=4'b0100;
#40 $display("S=%b,cout=%b",s,cout);
a=4'b0001 ; b=4'b1110;
#40 $display("S=%b,cout=%b",s,cout);
a=4'b1010 ; b=4'b0101; cin=1'b1;
#40 $display("S=%b,cout=%b",s,cout);
#20 $finish;
end
endmodule

module 32bitalu_v;
reg [31:0] a;
reg [31:0] b;
reg [2:0] opcode;
reg en;
wire [31:0] y;
wire [63:0] y_mul;
alu uut (
.a(a),
.b(b),
.opcode(opcode),
.en(en),
.y(y),
.y_mul(y_mul)
);
initial begin
a = 32'd100;
b = 32'd140;
opcode = 0;
en = 1;
end
initial begin
#20 opcode = 3'd0;
#20 opcode = 3'd1;
#20 opcode = 3'd2;
#20 opcode = 3'd3;
#20 opcode = 3'd4;
#20 opcode = 3'd5;
#20 opcode = 3'd6;
#20 opcode = 3'd7;
end
endmodule

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