Terms used in microprocessor literature

Bit : A digit of the binary number or code is called bit.

Nibble : The 4-bit (4-digit) binary number or code is called nibble.
Byte : The 8-bit (8-digit) binary number or code is called byte.
Word : The 16-bit (16-digit) binary number or code is called word.
Double Word : The 32-bit binary number or code is called double word.

Multiple Word : The 64, 128, ... bit /digit binary numbers or codes are called
multiple words.

Data : The quantity (binary number/code) operated by an instruction

of a program is called data. The size of data is specified as bit,
byte, word, etc.

Address : Address is an identification number in binary for memory

locations.

The 8086 processor uses a 20-bit address for memory.

Memory Word Size : The memory word size or addressability is the size of
binary information (or Addressability) that can be stored
in a memory location. The memory word size for an 8086
processor-based system is 8-bit.

Microprocessor: The microprocessor is a program controlled

semiconductor device(IC), which fetches (from memory),
decodes and executes instructions. It is used as CPU (Central
Processing Unit) in computers. The basic functional blocks of a
microprocessor are ALU (Arithmetic
Logic Unit), an array of registers and a control unit. The
microprocessor is identified with the size of data, the ALU of
the processor can work with at a time. The 8086 processor has a
16-bit ALU, hence it is called a 16-bit processor. The 80486
processor has a 32-bit ALU, hence it is called a 32-bit
processor.

Bus : A bus is a group of conducting lines that carries data, address

and control signals. Buses can be classified into Data bus,
 Address bus and Control bus. The group of conducting lines
that carries data is called data bus. The group of conducting
lines that carries address is called address bus. The group of
conducting lines that carries control signals is called control
bus.

CPU Bus : The group of conducting lines that are directly connected to the
microprocessor is called CPU bus. In a CPU bus, the signals are
multiplexed, i.e., more than one signal is passed through the
same line but at different timings.
System Bus : The group of conducting lines that carries data, address and
control signals in a microcomputer system is called System bus.
Multiplexing is not allowed in a system bus

Clock : A clock is a square wave used to synchronize various devices in

the microprocessor and in the system. Every microprocessor
system requires a clock for its functioning. The time taken for
the microprocessor and the system to execute an instruction or
program are measured only in terms of the time period of its
clock.

A clock has three edges : rising edge (positive edge), level e

dge and falling edge (negative edge). The device is made
sensitive to any one of the edges for better functioning (it
means that the device will recognize the clock only when the
edge is asserted or arrived).

Tristate Logic : Almost all the devices used in a microprocessor-based system

use tristate logic. In devices with tristate logic, three logic
levels will be available : High state, Low state and High
impedance state.

The high and low level states are normal logic levels for data,
address or control signals.
 The high impedance state is an electrical open-circuit condition.
The high impedance state is provided to keep the device
electrically isolated from the system.

The tristate devices will normally remain in high impedance

state and their pins are physically connected in the system bus
but electrically isolated. In high impedance state, they cannot
receive or send any signal or information. These devices are
provided with chip enable/chip select pins. When the signal at
this pin is asserted to the right level, they come out from high
impedance state to normal levels.

Microcomputer:

The term microcomputer is generally synonymous with personal computer, or a

computer that depends on a microprocessor.

• Microcomputers are designed to be used by individuals, whether in the form of

PCs, workstations or notebook computers.

• A microcomputer contains a CPU on a microchip (the microprocessor), a

memory system (typically ROM and RAM), a bus system and I/O ports, typically
housed in a motherboard.

Microprocessor:

 A microprocessor is a clock-driven semiconductor device consisting of

electronic logic circuits manufactured by using either a large-scale
integration (LSI) or very-large-scale integration (VLSI) technique.

 The microprocessor is capable of performing various computing functions

and making decisions to change the sequence of program execution.

 In large computers, a CPU performs these computing functions. The

Microprocessor resembles a CPU exactly. The microprocessor is in many
ways similar to the CPU, but includes all the logic circuitry including the
control unit, on one chip.
 The microprocessor can be divided into three segments for the sake of
clarity. – They are: arithmetic/logic unit (ALU), register array, and control
unit. A comparison between a microprocessor, and a computer is shown
below:

 Arithmetic/Logic Unit: This is the area of the microprocessor where

various computing functions are performed on data. The ALU unit performs
such arithmetic operations as addition and subtraction, and such logic
operations as AND, OR, and exclusive OR.
  Register Array: This area of the microprocessor consists of various
registers identified by letters such as B, C, D, E, H, and L. These registers
are primarily used to store data temporarily during the execution of a
program and are accessible to the user through instructions.

 Control Unit: The control unit provides the necessary timing and control
signals to all the operations in the microcomputer. It controls the flow of
data between the microprocessor and memory and peripherals.
 Memory: Memory stores such binary information as instructions and data,
and provides that information to the microprocessor whenever necessary. To
execute programs, the microprocessor reads instructions and data from
memory and performs the computing operations in its ALU section. Results
are either transferred to the output section for display or stored in memory
for later use. Read-Only memory (ROM) and Read/Write memory (R/WM),
popularly known as Random- Access memory (RAM).
 I/O (Input/Output): It communicates with the outside world. I/O includes
two types of devices: input and output; these I/O devices are also known as
peripherals.

 System Bus: The system bus is a communication path between the

microprocessor and peripherals: it is nothing but a group of wires to carry
bits.

Evolution of Microprocessors

The first µP was introduced in 1971 by Intel Corporation. This was the Intel 4004,
a processor on a single chip. It had the capability of performing simple arithmetic
and logical operations.

The first 8 bit µP, which would perform arithmetic and logic operations on 8 bit
words, was introduced in 1973, by Intel. This was 8008 that was followed by an
improved version- the 8080 from the same company.

The µPs introduced between 1971and 1972 were the first generation systems
They were designed using the PMOS technology. This technology provided low
cost, slow speed and low output currents and was compatible with TTL

After 1973, the second generation µPs such as Motorola 6800 and 6809, Intel
8085 and Zilog Z80 evolved. These µPs were fabricated using NMOS technology
The distinction between the 1st & 2nd generation devices was primarily the use of
new a semiconductor technology to fabricate the chips

After 1978, the 3rd generation microprocessors were introduced. Typical µPs
were Intel 8086/ 80186/ 80286 and Motorola 68000/ 68010. These µPs were
designed using HMOS technology. HMOS provides the following advantages over
NMOS.

The third generation introduced in 1978 was typically separated by the Intel 8086
iAPX8086, iAPX80186, iAPX80286, Zilog 8000, and the Motorola 68000 which
are 16- bit µPs with minicomputer like performance.
.
In 1980, the fourth generation µPs were evolved. Intel introduced the first
commercial 32 bit microprocessor, Intel 432. Since 1985, more 32-bit µPs have
been introduced. These include Intel iAPX80386, Intel 80486, Motorola
MC68020/68030/68040, National semiconductor NS 32032.

These processors were fabricated using the low power version of HMOS
technology called HCMOS, and they include an on-chip RAM called the cache
memory to speed up program execution.

Processor Year of No. of Initial clock Data Address Memory

launch transistor bus Bus addressing
(bit) (bit) Capacity

4004 1971 2300 108 KHz 4-bit 12-bit 4K

8008 1972 3500 200KHz 8-bit 14-bit 16K

8080 1974 6000 2MHz 8-bit 16 -bit 64 K

8085 1976 6500 5 MHz 8-bit 16 -bit 64 K

8086 1978 29000 5-10MHz 16-bit 20-bit 1M

80186 1982 55000 6 MHz 16-bit 20-bit 1MB

80286 1982 1,34000 8 MHz 16-bit 24-bit 16M

 80386 1985 2,75000 16 MHz 32-bit 32-bit 4G

80486 1989 1.2 25 MHz 32-bit 32-bit 4G

million(M)

Pentium 1993 3.1M 60MHz 32/64 32-bit 4G

Pentium Pro 1995 5.5M 150MHz 32/64 36-bit 64G

Pentium II 1997 8.8M 233MHz 64-bit 36-bit 64G

Pentium III 1999 9.5M 650MHz 64-bit 36-bit 64G

Pentium IV 2000 42M 1.4GHz 64-bit 36-bit 64G

Dual core 2006 291M 1.2GHz- 64-bit 32-bit 4G

3GHz

Core i7 2008 781M 2.66GHz 64-bit 32-bit 4G

Core i5 2009 781M 3.6GHz 64-bit 32-bit 4G

Core i3 2010 781M 3.3GHz 64-bit 32-bit 4G

Microcomputer

Microprocessor is a central processing unit (CPU) with its related timing functions
on a single chip. A microprocessor combined with memory and input/output
devices forms a microcomputer. Therefore, the basic components of a
microcomputer are:
 CPU
 Program memory
 Data memory
 Output ports
 Input ports
 Clock generator
 Data Program
Memory Memory

Clock CPU Output

Generator
Ports

Input Ports

Figure: Basic Components of Microcomputer

Central Processing Unit: The CPU consists of ALU (Arithmetic and Logic Unit),
register unit and control unit. The CPU fetches the stored instructions from the
program memory, data word from data memory or from an input device and after
processing the data stores the result in data memory or sends it to an output device.

Program Memory: The basic task of a microcomputer system is to ensure that its
CPU executes the desired instructions sequence i.e., the program properly. The
instructions sequence is stored in the program memory. On initialization- usually
on power up or manual reset the processor starts executing the instructions from a
predetermined location in program memory.

Data Memory: A microcomputer manipulates data according to the algorithm

given by the instruction in the program in the program memory. These instructions
may require intermediate results to be stored. The functional block in the
microcomputer used for this storage is the data memory. Microprocessors also
have a small amount of memory in the form of internal registers which can also be
used if available for such storage. External data memory is needed if the storage
requirement is more.
Input/Output Ports: The input & output ports provide the microcomputer the
capability to communicate with the outside world.
The input ports allow data to pass from the outside world to the µc data which will
be used in the data manipulation being done by the microcomputer to send data to
output devices.
The user can enter instruction (i.e. program) and data in memory through input
devices such as keyboard, or simple switches, CRT, disk devices, tape or card
readers

Clock Generator: Operations inside the microprocessor as well as in other parts

of the microcomputer are usually synchronous by nature. This is done so that
events in different parts of the system can proceed in a systematic fashion.
The clock needed to perform this synchronous operation is provided by the clock
generator. The clock generator generates the appropriate clock periods during
which instruction executions are carried out by the microprocessor.

8085 Microprocessor

The salient features of 8085 microprocessor are:

 It is an 8 bit microprocessor.
 It is manufactured with N-MOS technology.
 It has 16-bit address bus and hence can address up to 2 16 = 65536 (64K)
memory locations through A0 –A15 .
 The lower 8 lines of address bus and 8 lines of data bus are multiplexed AD 7 –
AD0 .
 Data bus is a group of 8 lines D0 to D7
 It supports external interrupt request.
 A Program counter (PC) of 16-bit
 A stack pointer (SP) of 16-bit
 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3MHZ single phase
clock.
 It is enclosed with 40 pins DIP (Dual in line package).
Architecture of INTEL 8085/8085A

 Intel 8085A is one of the most popular 8-bit microprocessors capable of

addressing 64KB of memory and its architecture is simple. The architecture
of 8085 includes the ALU, timing and control unit, instruction

 register and decoder, register array, interrupt control and serial I/O control in
a package of 40 pins, requires +5V single power supply and can operate with
a 3MHz single phase clock.

Figure: Internal Architecture of 8085/8085A

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as „add‟,
„subtract‟, „AND‟, „OR‟, etc. Uses data from memory and from Accumulator to
perform arithmetic. Always stores result of operation in Accumulator.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical
operations. The result of an operation is stored in the accumulator. The
accumulator is also identified as register „A‟.

Flags
The ALU includes five flip-flops, which are set or reset after an operation
according to data conditions of the result in the accumulator and other registers.
They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry
(AC) flags; they are listed in the Table and their bit positions in the flag register are
shown in the Figure below. The most commonly used flags are Zero, Carry, and
Sign. The microprocessor uses these flags to test data conditions.
These flags have critical importance in the decision-making process of the
microprocessor. The conditions (set or reset) of the flags are tested through the
software instructions. For example, the instruction JC (Jump on Carry) is
implemented to change the sequence of a program when CY flag is set. The
thorough understanding of flag is essential in writing assembly language programs.

Control Unit
Generates signals within microprocessor to carry out the instruction, which has
been decoded. In reality causes certain connections between blocks of the uP to be
opened or closed, so that data goes where it is required, and so that ALU
operations occur.

Registers
The 8085/8080A-programming model includes six registers, one accumulator, and
one flag register, as shown in Figure. In addition, it has two 16-bit registers: the
stack pointer and the program counter. They are described briefly as follows.
 Fig: Programming model of 8085 microprocessor

The 8085/8080A has six general-purpose registers(GPR) to store 8-bit data; these
are identified as B, C, D, E, H, and L as shown in the above figure. They can be
combined as register pairs - BC, DE, and HL
 to perform some16-bit operations. The programmer can use these registers to
store or copy data into the registers by using data copy instructions

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This
register is a memory pointer. Memory locations have 16-bit addresses, and that is
why this is a 16-bit register. The microprocessor uses this register to sequence the
execution of the instructions. The function of the program counter is to point to the
memory address from which the next byte is to be fetched. When a byte (machine
code) is being fetched, the program counter is incremented by one to point to the
next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer. The stack concept is
explained in the chapter "Stack and Subroutines."

Instruction Register/Decoder
Temporary storage for the current instruction of a program. Latest instruction sent
here from memory prior to execution. Decoder then takes instruction and „decodes‟
or interprets the instruction. Decoded instruction then passed to next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the address
bus with addresses of location of the program under execution.

Control Generator
Generates signals within microprocessor to carry out the instruction which has
been decoded. In reality causes certain connections between blocks of the uP to be
opened or closed, so that data goes where it is required, and so that ALU
operations occur

Memory
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch
and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB. All jump/branch instructions use absolute addressing.
Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.
• First 64 bytes in a zero memory page should be reserved for vectors used by RS
instructions
Interrupts
INTR is maskable 8085 compatible interrupt. When the interrupt occurs the
processor fetches from the bus one instruction, usually one of these instructions

One of the 8 RST instructions (RST0 - RST7). The processor saves current
program counter into stack and branches to memory location N * 8 (where N 3-bit
number from 0 to 7 supplied with the RST instruction).

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves
the contents of the PC register into stack and branches to 002CH (hexadecimal)
address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves
the contents of the PC register into stack and branches to 0034H (hexadecimal)
address.

RST7.5 is a maskable interrupt. When this interrupt is received the processor saves
the contents of the PC register into stack and branches to 003CH (hexadecimal)
address.

TRAP is a non-maskable interrupt. When this interrupt is received the processor

saves the contents of the PC register into stack and branches to 0024H
(hexadecimal) address.
All maskable interrupts RST 5.5, RST6.5 and RST7.5 can be enabled or disabled
individually using SIM instruction.

Serial communication Signal

SID - Serial Input Data Line: The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD – Serial Output Data Line: The SIM instruction loads the value of bit 7 of the
accumulator into SOD latch if bit 6 (SOE) of the accumulator is 1.

RESET IN
  When this signal goes low, the program counter (PC) is set to Zero µp is reset
and resets the interrupt enable and HLDA flip-flops
 The data and address buses and the control lines are tri-stated during RESET
because of asynchronous nature of RESET, the processor internal registers
and flags may be altered by RESET with unpredictable results

 Upon power-up, RESET IN must remain low for at least 10 ms after minimum
Vcc has been reached.

• For proper reset operation after the power – up duration, RESET IN should be
kept low a minimum of three clock periods.

RESET OUT:

This signal indicates that µp is being reset. This signal can be used to reset other
devices. The signal is synchronized to the processor clock and lasts an integral
number of clock periods

DMA Signals
HOLD:
Indicates that another master is requesting the use of the address and data buses.
The CPU, upon receiving the hold request, will relinquish the use of the bus as
soon as the completion of the current bus transfer.

• Internal processing can continue. The processor can regain the bus only after the
HOLD is removed.
• When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines
are tri-stated.

HLDA:

Hold Acknowledge: Indicates that the CPU has received the HOLD request and
that it will relinquish the bus in the next clock cycle.

• HLDA goes low after the Hold request is removed. The CPU takes the bus one
half-clock cycle after HLDA goes low.
READY:

This signal Synchronizes the fast CPU and the slow memory, peripherals.

• If READY is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data.

• If READY is low, the CPU will wait an integral number of clock cycle for
READY to go high before completing the read or write cycle. • READY must
conform to specified setup and hold times.

8085 microprocessor Pin diagram

X1 1 40 VCC
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST 7.5 7 34 𝐼𝑂 𝑀
RST 6.5 8 33 S1
RST 5.5 9 8085/ 32 RD
INTR 10 31
8085A WR
INTA 11 30 ALE
AD0 12 29 s0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A
3 12
AD5 17 24 A
3 11
AD6 18 23 A
3 10
AD7 19 22 A
39
VSS, GND 20 21 A8
AD7 – AD0 (Input/Output tri-state) Multiplexed Address/Data Bus; Lower 8 bits
of the memory address (or I/0 address) appear on the bus during the first clock
cycle of a machine state. It then becomes the data bus during the second and third
clock cycles. 3 stated during Hold and Halt modes.

De-multiplexing address and data bus

ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a
machine state and enables the address to get latched into the on chip latch of
peripherals. The falling edge of ALE is set to guarantee setup and hold times for
the address information. ALE can also be used to strobe the status information.
ALE is never tri-stated.

𝐈𝐎 𝐌 : This is a status signal used to differentiate I/O and memory operations.

When it is high it indicates I/O operations and low indicates memory operations.
This signal is combined with RD and WR to generate I/O and memory control
signals.

SO, S1 (Output) Data Bus Status. Encoded status of the bus cycle:

Machine Cycle Status Control Signals

𝐼𝑂 𝑀 S1 S0

Opcode fetch 0 1 1 𝑅𝐷 = 0

Memory Read 0 1 0 𝑅𝐷 = 0

Memory Write 0 0 1 𝑊𝑅 = 0
I/O Read 1 1 0 𝑅𝐷 = 0
I/O Write 1 0 1 𝑊𝑅 = 0
Interrupt Acknowledge 1 1 1 𝐼𝑁𝑇𝐴 = 0
HALT Z 0 0 𝑅𝐷, 𝑊𝑅 = 𝑍 𝑎𝑛𝑑 𝐼𝑁𝑇𝐴 = 1
HOLD Z X X 𝑅𝐷, 𝑊𝑅 = 𝑍 𝑎𝑛𝑑 𝐼𝑁𝑇𝐴 = 1
RESET Z X X 𝑅𝐷, 𝑊𝑅 = 𝑍 𝑎𝑛𝑑 𝐼𝑁𝑇𝐴 = 1

𝐑𝐞𝐚𝐝 𝐒𝐢𝐠𝐧𝐚𝐥( 𝑹𝑫) (𝑶𝒖𝒕𝒑𝒖𝒕); It is low active read control signal, this signal
indicates that the selected memory or I/0 or memory device is to be read and data
are available on data bus..

Write Signal (𝑾𝑹) 𝑶𝒖𝒕𝒑𝒖𝒕 : It is low active write control signal; This indicates
the data on the data bus to be written into the selected memory or I/0 location.

Address Bus:
 The 8085 has 16 signal lines(pins) that are used as the address bus.
  These lines are breaks into two segments : (A15 – A8) and : (AD7 – AD0)
 The eight lines, (A15 – A8) are unidirectional and used for most significant
bits, called the high order address of 16 bit address.
 The signal lines AD7 – AD0 are used for dual purpose.

Data Bus:
 This is used for the exchange of data between processor, memory and
peripherals
 It is bidirectional so that it allows data flow in both directions
 The signal lines AD7 – AD0 are bidirectional: they serve a dual purpose.
These lines are used as low–order address bus as well as data bus. The low
order address bus can be separated from data signals using the latch.

Memory Range of 8085

 8085 has 16-bit address bus (A0 – A15).

 It means, it can access 216 memory locations.
216 = 26 X 210 = 26 X 1K = 64 X 1K = 64K
So, 8085 can access up to 64K memory locations.
At every memory location, 8-bits i.e. 1-Byte is stored.
Hence, 8085 can access up to 64KB of memory data.
 The memory address range is

0000 0000 0000 0000B 0000H 00 00H

0000 0000 0000 0001B 0001H 00 01H
: :
: :
1111 1111 1111 1110B FFFEH FF FEH
1111 1111 1111 1111B FFFFH FF FFH

8085 Interrupts:
A microprocessor has only two ways to determine the condition that exist in
internal & external circuitry.

• Using Software, called Status Check or Polling.

Occupy the processor. Processor has to execute instructions continuously in

a loop, until the desired state is identified.
 • Using Interrupt.
•
Does not engage the processor. After initialization, device informs the
processor that desired state is achieved. This information is given by a special
signal called interrupt

A processor can normally be interrupted by two methods, either by an

instruction or by hardware. Accordingly the interrupts may be classified
as
– Software Interrupts
• Execution of an instruction causes an interrupt to processor.

– Hardware Interrupts
• Application of an appropriate logic status (HIGH/LOW) on a
hardware pin of processor causes an interrupt to processor.

Software Interrupts:
8085 has a special instruction “RST n” that can be used as software interrupt.

– RST n means Restart (RST) execution from a memory

location addressed by the integer n.
– n is an integer that can vary from 0 to 7.
– Memory address given by n can be calculated as,
Address = n * 8.
– E.g. RST 3 Address = 3 * 8 = 24D = 18H = 0018H. So RST 3
means restart execution from memory location 0018 H.
– RST n is normally used as Software Breakpoint Interrupt.
– Such interrupts can be used to store status of program which
is many times useful for debugging.
– Recall the use of RST 5 in Lab
– In order for processor to resume exactly from the same point
where it has left it is necessary that last instruction of ISS
should be RET.
RST n
– E.g. RST 3
– Calculate address for RST 3 i.e. 0018H
(SP-1) ← PCH(higher byte of program counter)
(SP-2) ← PCL(lower byte of program counter)
SP ← SP – 2
PC ← 0018H
– Execution of RST n takes 3 Machine cycles namely, Opcode
Fetch, Memory Write and Memory Write.
– Opcode Fetch takes 6 T-States, since it not only fetches &
decode the instruction, but also calculates the address for n.
 – Rest of the two write cycles stores return address into the
stack so that processor can resume its normal execution
sequence.
– It is clear that, RST 3 means Restart (RST) execution from
memory location 0018H after storing return address in stack.
– RST 3 can equivalently be said CALL 0018H.
Hence, RST n is sometimes, also called as 1-byte CALL
instruction
– Restart address 0018H for RST 3 is also called Vector
Address for RST 3 i.e. Interrupt Vector Address for RST 3 is
0018H.
– In the similar analogy the restart number “n,” in RST n, is
called Interrupt Vector.
Since both the Interrupt Vector and Interrupt Vector Address
represents same thing, the memory address, the two terms are
used synonymously
 A table comprising all the vector addresses for instruction RST n
(n=0 to 7) is called Interrupt Vector Table and is shown next.
Interrupt Vector Table
Vector RST n Instruction Vector Address
(n)

0 RST 0 0000H

1 RST 1 0008H

2 RST 2 0010H

3 RST 3 0018H

4 RST 4 0020H
 5 RST 5 0028H

6 RST 6 0030H

7 RST 7 0038H

Hardware Interrupts:
8085 has several hardware pins through which, an interrupt request can be lodged.
Below are list of interrupt signals offered by 8085

– TRAP (RST 4.5)

– RST 7.5
– RST 6.5
– RST 5.5
– INTR & INTA
Interrupt Vector Table
 Vector addresses for hardware interrupts are in boldface. Non
boldface addresses are for software interrupts.
 Note that only 4-byte memory space is available between RST 4.5
& RST 5 and so on

Vector
RST n Instruction Vector Address
(n)

0 RS T 0 0000
HH

1 RS T 1 0008
HH

2 RS T 2 0010
HH
 3 RS T 3 0018
H
H

4 RS T 4 0020
H
H

TRAP 0024
4.5 H
RST 4.5 H

5 RS T 5 0028
H
H

5.5 RST 5.5 002C

H H

6 RS T 6 0030
H

6.5 RST 6.5 0034

H
H

7 RS T 7 0038
H
H

7.5 RST 7.5 003C

H H

Interrupts can be divided in three categories

– Vectored Interrupts & Non-Vectored Interrupts
– Maskable Interrupts & Non-Maskable Interrupts
– Edge Triggered Interrupts & Level Triggered Interrupts
Vectored interrupts- These type of interrupts have fixed memory
address :
Example: TRAP, RST7.5, RST6.5 , RST5..5 and RST 0 to RST 7
Non-vectored Interrupts: In this type of interrupt, the interrupt address
is not known to the processor so, the interrupt address needs to be sent
externally by the device to perform interrupts.
Example: INTR
Maskable Interrupts : These type interrupts can be disabled by writing
instruction in program.
Example: RST7.5, RST6.5, RST5.5 , INTR
Non-Maskable Interrupts: These type interrupts cannot be disabled by
writing instruction in program.
Example: TRAP

Edge Triggered Interrupts : TRAP , RST7.5

Level Triggered Interrupts: TRAP, RST6.5, RST5.5 and INTR

Interrupt Priority Trigger

TRAP 1(highest) Edge and level triggered
RST7.5 2 Edge triggered
RST6.5 3 level triggered
RST5.5 4 level triggered
RST4.5 5(lowest) level triggered

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the
corresponding interrupting source is called an ISR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By
default, it is enabled until it gets acknowledged. In case of failure, it executes as
ISR and sends the data to backup memory. This interrupt transfers the control to
the location 0024H.

RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 003CH address.

RST 6.5 It is a maskable interrupt, having the third highest priority among all
interrupts. When this interrupt is executed, the processor saves the content of the
PC register into the stack and branches to 0034H address.
 RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.

INTRs It is a maskable interrupt, having the lowest priority among all interrupts.
It can be disabled by resetting the microprocessor.

When INTR signal goes high, the following events can occur −

 The microprocessor checks the status of INTR signal during the execution of
each instruction.

 When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.

 When instructions are received, then the microprocessor saves the address of
the next instruction on stack and executes the received instruction.

Interrupt Structure
VECTOR
MASK LOCATION
TRAP 0024
1

RST D Q I 7.5
2 7.5
003C
CLR
R 7.5 M 7.5

RST 7.5 INTERRUPT RECOGNISED

0038

RST
3 6.5 0034

M 6.5
0030

RST
4 5.5 002C

M 5.5 0028

EI S Q
0020
DI
RESET R 0018
ANY INTERRUPT RECOGANISED INTERRUPT
ENABLE 0010
GET RST CODE
FROM EXTERNAL 0008
INTR HARDWARE
5
0000
SIM Instruction:
Opcode Operand Description
SIM None Set Interrupt Mask

 This is a multipurpose instruction and used to implement the 8085 interrupts

RST7.5, RST6.5, RST5.5, and serial data output.
 The contents of SIM register is called the SIM word.
 The instruction interprets the accumulator contents as given below.

 Example: SIM

RIM Instruction:
Opcode Operand Description
RIM None Read Interrupt Mask
 This is a multipurpose instruction used to read the status of pending
interrupts RST7.5, RST6.5, RST5.5 and read serial data input bit.

 The instruction loads eight bits in the accumulator with the following
interpretations.

 Example: RIM
Think over it:

Why is data bus bidirectional?

The microprocessor has to fetch (read) the data from the memory or input device
for processing and after processing it has to store (write) the data in the memory or
output device. Hence, the data bus is bidirectional.
Why is address bus unidirectional?
The address is an identification number used by the microprocessor to identify or
access a memory location or IO device. It is an output signal from the processor.
Hence, the address bus is unidirectional.
What is the difference between CPU bus and system bus?
The CPU bus has multiplexed lines but the system bus has separate lines for each
signal. (The multiplexed CPU lines are demultiplexed by the CPU interface circuit
to form the system bus.)

What is multiplexing and what is its advantage?

Multiplexing is transferring of different information at different well-defined times
through the same lines. A group of such lines is called a multiplexed bus. The
advantage of multiplexing is that fewer pins are required for microprocessors to
communicate with the outside world.

What is T-state?
T-state is the time period of the internal clock signal of the processor. The time
taken by the processor to execute a machine cycle is expressed in T-state.
What is the need for timing diagram?
The timing diagram provides information regarding the status of various signals,
when a bus cycle is executed. The knowledge of timing diagram is essential for
system designer to select matched peripheral devices like memories, latches, ports,
etc., to form a microprocessor system