41130399_P.

SAIVISWATEJA

DATE:
STUDY ON VERIFICATION OF 01.02.20
EXPT. NO:
01 LOGIC GATES 24

PAGE NO:

AIM:

To develop the source code for logic gates using VHDL/VERILOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1
 41130399_P.SAIVISWATEJA

1. AND GATE:

EXPRESSI DIAGRAM OR SYMBOL TRUTH TABLE

ON
INPUTS OUTPUT
A B Y
0 0 0
Y = A.B 0 1 0
1 0 0
1 1 1

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ANDGATE_214 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end ANDGATE_214;
architecture dataflow ANDGATE_214 is
begin
Y <= A AND B;
end dataflow;

● SIMULATED OUTPUT:

2
 41130399_P.SAIVISWATEJA

2. OR GATE:

EXPRESSIO DIAGRAM OR SYMBOL TRUTH TABLE

N
INPUTS OUTPUT
A B Y
0 0 0
Y = A+B 0 1 1
1 0 1
1 1 1

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ORGATE_214 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end ORGATE_214;
architecture dataflow ORGATE_214 is
begin
Y <= A OR B;
end dataflow;

● SIMULATED OUTPUT:

3
 41130399_P.SAIVISWATEJA

3. NAND GATE:

EXPRESSIO DIAGRAM OR SYMBOL TRUTH TABLE

N
INPUTS OUTPUT
A B Z
0 0 1
Z = (A.B)’ 0 1 1
1 0 1
1 1 0

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NANDGATE_214 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end NANDGATE_214;
architecture dataflow NANDGATE_214 is
begin
Z <= A NAND B;
end dataflow;

● SIMULATED OUTPUT:

4
 41130399_P.SAIVISWATEJA

4. NOR GATE:

EXPRESSIO DIAGRAM OR SYMBOL TRUTH TABLE

N
INPUTS OUTPUT
A B Q
0 0 1
Q = (A+B)’ 0 1 0
1 0 0
1 1 0

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NORGATE_214 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end NORGATE_214;
architecture dataflow NORGATE_214 is
begin
Y <= A NOR B;
end dataflow;

● SIMULATED OUTPUT;

5
 41130399_P.SAIVISWATEJA

5. XOR GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Y
0 0 0
Y = AB’ + A’B
0 1 1
1 0 1
1 1 0

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XORGATE_214 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end XORGATE_214;
architecture dataflow XORGATE_214 is
begin
Y <= A XOR B;
end dataflow;

● SIMULATED OUTPUT:

6
 41130399_P.SAIVISWATEJA

6. XNOR GATE:

EXPRESSIO DIAGRAM OR SYMBOL TRUTH TABLE

N
INPUTS OUTPUT
A B Y
0 0 1
A Y 0 1 0
Y = (AB’ +
A’B)’ B 1 0 0
1 1 1

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XNORGATE_214 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end XNORGATE_214;
architecture dataflow XNORGATE_214 is
begin
Y <= A XNOR B;
end dataflow;

● SIMULATED OUTPUT:

7
 41130399_P.SAIVISWATEJA

7. NOT GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUT
OUTP
Y = (X)’ UT X Y
0 1
1 0

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOTGATE_214 is
port (X: in STD_LOGIC; Y: out STD_LOGIC);
end NOTGATE_214;
architecture dataflow NOTGATE_214 is
begin
Y <= NOT X;
end dataflow;

● SIMULATED OUTPUT:

8
 41130399_P.SAIVISWATEJA

VERILOG CODES:

1. AND GATE:

module and1(a,b,c);
input a,b;
output c;
assign c = a&b;
endmodule

2. OR GATE:

module or1(a,b,c);
input a,b;
output c;
assign c = a|b;
endmodule

3. NAND GATE:

module nand1(a,b,c);
input a,b;
output c;
assign c = ~(a&b);
endmodule

9
 41130399_P.SAIVISWATEJA

4. NOR GATE:

module nor1(a,b,c);
input a,b;
output c;
assign c = ~(a|b);
endmodule

5. XOR GATE:

module xor1(a,b,c);
input a,b;
output c;
assign c = a^b;
endmodule

6. XNOR GATE:

module xnor1(a,b,c);
input a,b;
output c;
assign c = ~(a^b);
endmodule

10
 41130399_P.SAIVISWATEJA

7. NOT GATE:

module and1(a,b);
input a;
output b;
assign b = ~a;
endmodule

RESULT:

The output of Logic Gates is verified by stimulating and synthesizing the VHDL
/VERILOG code.

11
 41130399_P.SAIVISWATEJA

DATE:
01.02.20
EXPT. NO: ADDERS AND SUBTRACTORS
02 24

PAGE NO:

AIM:

To develop the source code for adders and subtractors using VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. HALF ADDER:

● CIRCUIT DIAGRAM:

12
 41130399_P.SAIVISWATEJA

● EXPRESSIONS:

❖ SUM (S) = A XOR B

❖ CARRY (C) = A AND B

● TRUTH TABLE:

INPUTS OUTPUTS
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

● VHDL CODE:

⮚ DATAFLOW MODELING:

use IEEE.STD_LOGIC_1164.ALL; use

IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFADDER_214 is
port (A, B: in STD_LOGIC; S, C: out STD_LOGIC);
end HALFADDER_214;
architecture dataflow of HALFADDER_214 is
begin
S <= A XOR B;
C <= A AND B;
end dataflow;

⮚ STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALFADDER_214is
port (A, B: in STD_LOGIC; S, C: out STD_LOGIC);
end HALFADDER_214;
architecture structural of HALFADDER_214 is

13
 41130399_P.SAIVISWATEJA

component xor1
port (a1, b1: in STD_LOGIC; c1: out STD_LOGIC);
end component;
component and1
port (a2, b2: in STD_LOGIC; c2: out STD_LOGIC);
end component;
begin
ag: and1 port map(A, B, C);
ng: xor1 port map(A, B, S);
end structural;

--COMPONENT SOURCE CODE

--XOR1:
entity xor1 is
port (a1, b1: in STD_LOGIC; c1: out STD_LOGIC);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;

--AND1:
entity and1 is
port (a2, b2: in STD_LOGIC; c2: out STD_LOGIC);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;

⮚ BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFADDER_214 is
port (A, B: in STD_LOGIC; S, C: out STD_LOGIC);
end HALFADDER_214
architecture behavioural of HALFADDER_214 is
begin
process (A, B)
begin
S <= A XOR B;
C <= A AND B;
end process;
end behavioural;

14
 41130399_P.SAIVISWATEJA

 SIMULATEDOUTPUT:

● VERILOG CODE:

⮚ DATAFLOW MODELING:

module ha_d214(a,b,s,c);
input a,b;
output s,c;
assign s = a^b;
assign c = a&b;
endmodule

⮚ STRUCTURAL MODELING:

module ha_d214(a,b,s,c);
input a,b;
output s,c;
xor(s,a,b)
and(c,a,b)
endmodule

⮚ BEHAVIOURAL MODELING:

module ha_d214(a,b,s,c);
input a,b;
output reg s,c;
always @(*)
begin
s = a+b;
assign c = a&b;
end
endmodule

15
 41130399_P.SAIVISWATEJA

 SIMULATEDOUTPUT:

2. FULL ADDER:

● CIRCUIT DIAGRAM:

● EXPRESSIONS:

❖ SUM (S) = X XOR Y XOR Cin

❖ CARRY (C) = (X AND Y) OR (X AND Cin) OR (Y AND Cin)

16
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

INPU OUTPU
TS TS
X Y C S Co
i ut
n
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

● VHDL CODE:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER_214 is
port (X, Y, Cin: in std_logic;
S, Cout: out std_logic);
end FULLADDER_214;
architecture dataflow of FULLADDER_214 is
begin
S <= (X XOR Y) XOR Cin;
Cout <= ((X AND Y) OR (Y AND Cin)) OR (Cin AND X);
end dataflow;

● STRUCTURAL MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER_214 is
port (X, Y, Cin: in std_logic;
S, Cout: out std_logic);

17
 41130399_P.SAIVISWATEJA
end FULLADDER_214;

18
 41130399_P.SAIVISWATEJA

architecture structural of FULLADDER_214 is

component xor1
port (a1, b1, c1: in std_logic; d1:out std_logic);
end component;
component and1
port (a2, b2: in std_logic; c2:out std_logic);
end component;
component or1
port (a3, b3: in std_logic; c3:out std_logic);
end component;
signal s1, s2, s3: std_logic;

begin
x1: xor1 port map (X, Y, Cin, S);
a1: and1 port map (X, Y, s1);
a2: and1 port map (X, Y, s2);
a3: and1 port map (Cin, X, s3);
o1: or1 port map (s1, s2, s3, Cout);
end structural;

--COMPONENT SOURCE CODE:

--XOR1
entity xor1 is
port (a1, b1, c1: in std_logic;
d1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
d1<= <= a1 XOR b1 XOR c1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic;
c2: out std_logic);
end and1;
architecture dataflow of and1 is
begin
c2<= <= a2 AND b2;
end dataflow;

--OR1
entity or1 is
port (a3, b3, c3: in std_logic;
d3: out std_logic);
end or1;
architecture dataflow of or1 is

19
 41130399_P.SAIVISWATEJA

begin
d3 <= (a3 OR b3) OR c3;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FULLADDER_214 is
port (X, Y, Cin: in std_logic;
S, Cout: out std_logic);
end FULLADDER_214;
architecture behavioural of FULLADDER_214 is
begin
process (X, Y,
Cin) begin
S <= (X XOR Y) XOR Cin;
Cout <= ((X AND Y) OR (Y AND Cin)) OR (Cin AND X);
end process; end
behavioural;

● SIMULATED OUTPUT:

● VERILOG CODE:

● DATAFLOW MODELING:

module fa_d214(x,y,z,s,c);
input x,y,z;
output s,c;
assign s=x^y^z;
assign c=(x&y)|(y&z)|(z&x);
endmodule

20
 41130399_P.SAIVISWATEJA

● STRUCTURAL MODELLING:

module fa_s214(x,y,z,s,c);
input x,y,z;
output s,c;
wire i,j,k;
xor(s,x,y,z);
and
a1(i,x,y),
a2(j,y,z),
a3(k,z,x);
or(c,i,j,k);
endmodule

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FULLADDER_214 is
port (X, Y, Cin: in std_logic;
S, Cout: out std_logic);
end FULLADDER_214;
architecture behavioural of FULLADDER_214 is
begin
process (X, Y,
Cin) begin
S <= (X XOR Y) XOR Cin;
Cout <= ((X AND Y) OR (Y AND Cin)) OR (Cin AND X);
end process; end
behavioural;

21
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

3. HALF SUBTRACTOR:

● CIRCUIT DIAGRAM:

● EXPRESSIONS:

❖ Difference (D) = A XOR B

❖ Borrow (Bo) = (NOT A) AND B

● TRUTH TABLE:

INPUTS OUTPUTS
A B D B
o
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

22
 41130399_P.SAIVISWATEJA

● VHDL CODE:

⮚ DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFSUBT_214 is
port (A, B: in std_logic;
D, Bo: out std_logic);
end HALFSUBT_214;
architecture dataflow of HALFSUBT_214 is
begin
D <= A XOR B;
Bo <= (NOT A) AND B;
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFSUBT_214 is
port (A, B: in std_logic;
D, Bo: out std_logic);
end HALFSUBT_214;
architecture structural of HALFSUBT_214 is
component xor1
port (a1, b1: in std_logic; c1: out std_logic);
end component;
component and1
port (a2, b2: in std_logic; c2: out std_logic);
end component;
component not1
port (a3: in std_logic; b3: out std_logic);
end component;
signal s1: std_logic;
begin
a1: and1 port map (s1, B, Bo);
x1: xor1 port map (A, B, D);
n1: not1 port map (A, s1);
end structural;

--COMPONENT SOURCE CODE

--XOR1

23
 41130399_P.SAIVISWATEJA

entity xor1 is
port (a1, b1: in std_logic;
c1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic;
c2: out std_logic);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;

--NOT1
entity not1 is
port (a3: in std_logic; b3: out std_logic);
end not1;
architecture dataflow of not1 is
begin
b3 <=not a3;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFSUBT_214 is
port (A, B: in std_logic;
D, Bo: out std_logic);
end HALFSUBT_214;
architecture behavioural of HALFSUBT_214 is
begin
process (A, B)
begin
D <= A XOR B;
Bo <= (NOT A) AND B;
end process;
end behavioural;

24
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

● VERILOG CODE:

● DATAFLOW MODELING:

module hs_d214(x,y,d,b);
input x,y;
output d,b;
assign d=x^y;
assign b=(~x)&y;
endmodule

● STRUCTURAL MODELING

module hs_s214(x,y,d,b);;
input x,y;
output d,b;
xor(d,x,y);
and(b,(~x),y);
endmodule

● BEHAVIOURAL MODELING:

module hs_b214(x,y,d,b);
input x,y;
output d,b;
reg d,b;
always @(*)
begin
d=y-x;
assign b=(~x)&y;
end
endmodule

25
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

4. FULL SUBTRACTOR:

● CIRCUIT DIAGRAM:

● EXPRESSIONS:

❖ Difference (D) = (A XOR B) XOR C

❖ Borrow (Bo) = ((NOT (A XOR B)) AND C) OR ((NOT A) AND B)

26
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

INPU OUTPU
TS TS
A B C D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

● VHDL CODE:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBT_214 is
port (A, B, C: in std_logic; D, Bo: out std_logic);
end FULLSUBT_214;
architecture dataflow of FULLSUBT_214 is
begin
D <= (A XOR B) XOR C;
Bo <= ((NOT A) AND B) OR (B AND C) OR (C AND
(NOT A));
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBT_214 is
port (A, B, C: in std_logic;

27
 41130399_P.SAIVISWATEJA

D, Bo: out std_logic);

end FULLSUBT_214;
architecture structural of FULLSUBT_214 is
component xor1
port (a1, b1: in std_logic; c1: out: std_logic);
end component;
component and1
port (a2, b2: in std_logic; c2: out: std_logic);
end component;
component or1
port (a3, b3: in std_logic; c3: out: std_logic);
end component;
component not1
port (a4: in std_logic; b4: out: std_logic);
end component;
signal s1, s2, s3, s4, s5: std_logic;
begin
x1: xor1 port map (A, B, s1);
x2: xor1 port map (s1, C, D);
a1: and1 port map (s2, C, s4);
a2: and1 port map (s3, B, s5);
o1: or1 port map (s4, s5, Bo);
n1: not1 port map (s1, s2);
n2: not1 port map (A, s3);
end structural;

--COMPONENT SOURCE CODE

--XOR1
entity xor1 is
port (a1, b1: in std_logic; c1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic; c2: out std_logic);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;

--NOT1
entity not1 is

28
 41130399_P.SAIVISWATEJA

port (a4: in std_logic; b4:out std_logic);

end not1;
architecture dataflow of not1 is
begin
b4 <= NOT a4;
end dataflow;

--OR1
entity or1 is
port (a3, b3: in std_logic; c3: out std_logic);
end or1;
architecture dataflow of or1 is
begin
c3 <= a3 OR b3;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBT_214 is
port (A, B, C: in std_logic; D, Bo: out std_logic);
end FULLSUBT_214;
architecture behavioural of FULLSUBT_214 is
begin
process (A, B, C)
begin
D <= (A XOR B) XOR C;
Bo <= ((NOT A) AND B) OR (B AND C) OR (C AND
(NOT A));
end process;
end behavioural;

● SIMULATED OUTPUT:

29
 41130399_P.SAIVISWATEJA

● VERILOG CODE:

⮚ DATAFLOW MODELING:

module fs_d214(x,y,z,d,b);
input x,y,z;
output d,b;
assign d=x^y^z;
assign b=((~x)&(y))|((~(x^y))&(z));
endmodule

⮚ STRUCTURAL MODELING:

module fs_s214(x,y,z,d,b);
input x,y,z;
output d,b;
wire i,j,k;
xor(d,x,y,z);
and
a1(i,(~x),y),
a2(j,(~(x^y)),z);
or(b,i,j);
endmodule

⮚ BEHAVIOURAL MODELING:

module fs_b214(x,y,z,d,b);
input x,y,z;
output d,b;
reg d,b;
always @(*)
begin
d=z-y-x;
assign b=((~x)&(y))|((~(x^y))&(z));
end
endmodule

30
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

RESULT:

The output of Adders and Subtractors is verified by stimulating and synthesizing

the VHDL/VERILOG code.

31
 41130399_P.SAIVISWATEJA

DATE:
08.02.20
EXPT. NO: ENCODER AND DECODER
03 24

PAGE NO:

AIM:

To develop the source code for encoder and decoder using VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. 8*3 ENCODER:

● CIRCUIT DIAGRAM:

Y0

32
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

INPUTS OUTPUTS
Y Y Y Y Y Y Y Y A A A
7 6 5 4 3 2 1 0 2 1 0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

● VHDL CODE:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER_214 is
port (Y: in STD_LOGIC_VECTOR (0 to 7);
A2, A1, A0: out STD_LOGIC);
end ENCODER_214;
architecture dataflow of ENCODER_214 is
begin
A0 <= ((Y (1) OR Y (3)) OR Y (5)) OR Y (7);
A1 <= ((Y (2) OR Y (3)) OR Y (6)) OR Y (7);
A2 <= ((Y (4) OR Y (5)) OR Y (6)) OR Y (7);
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER_214 is
port (Y: in STD_LOGIC_VECTOR (0 to 7);
A2, A1, A0: out STD_LOGIC);

33
 41130399_P.SAIVISWATEJA

end ENCODER_214;
architecture structural of ENCODER_214 is
component or1
port (a, b, c, d: in std_logic;
z: out std_logic);
end component;
begin
o1: or1 port map (Y(7), Y(6), Y(5), Y(4), A2);
o2: or1 port map (Y(7), Y(6), Y(2), Y(3), A1);
o2: or1 port map (Y(7), Y(5), Y(3), Y(1), A0);
end structural;

--COMPONENT SOURCE CODE

--OR GATE
entity or1 is
port (a, b, c, d: in std_logic;
z: out std_logic);
end or1;
architecture dataflow of or1 is
begin
z <= ((a OR b) OR c) OR d;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER_214 is
port (Y: in STD_LOGIC_VECTOR (0 to 7);
A2, A1, A0: out STD_LOGIC);
end ENCODER_214;
architecture behavioural of ENCODER_214 is
begin
process (Y)
begin
A0 <= ((Y(1) OR Y(3)) OR Y(5)) OR Y(7);

A1 <= ((Y(2) OR Y(3)) OR Y(6)) OR Y(7);

A2 <= ((Y(4) OR Y(5)) OR Y(6)) OR Y(7);
end process;
end dataflow;

34
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

● VERILOG CODE:

⮚ DATAFLOW MODELING:

module encoder_d214(input[7:0]a,output[2:0]y);
assign y[0]= a[1]| a[3]| a[5]| a[7];
assign y[1]= a[3]| a[2]| a[6]| a[7];
assign y[2]= a[4]| a[5]| a[6]| a[7];
endmodule

⮚ STRUCTURAL MODELING:

module encoder_s214(input[7:0]a,output[2:0]y);
or(y[0],a[1],a[3],a[5],a[7]);
or(y[1],a[3], a[2], a[6], a[7]);
or(y[2], a[4], a[5], a[6], a[7]);
endmodule

⮚ BEHAVIOURAL MODELING:

module encoder_b214(input[7:0]a,output reg[2:0]y);

always @(*)
begin
case(a)
8'b00000000:y=3'd0;
8'b00000001:y=3'd0;
8'b00000010:y=3'd1;
8'b00000100:y=3'd2;
8'b00001000:y=3'd3;
8'b00010000:y=3'd4;
8'b00100000:y=3'd5;
8'b01000000:y=3'd6;

35
 41130399_P.SAIVISWATEJA

8'b10000000:y=3'd7;
endcase
end
endmodule

● SIMULATED OUTPUT:

2. 3*8 DECODER:

● CIRCUIT DIAGRAM:

36
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

OUTPU INPUTS
TS
Y Y Y Y Y Y Y Y A A A
7 6 5 4 3 2 1 0 2 1 0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

● VHDL CODE:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_214 is
port (A: in std_logic_vector (2 downto 0);
Y: out std_logic_vector (7 downto 0));
end DECODER_214;
architecture dataflow of DECODER_214 is
begin
Y(0)<=((not A(2)) and (not A(1))) and (not A(0));
Y(1)<=((not A(2)) and (not A(1))) and A(0);
Y(2)<=((not A(2)) and A(1)) and (not A(0));
Y(3)<=((not A(2)) and A(1)) and A(0);
Y(4)<=(A(2) and (not A(1))) and (not A(0));
Y(5)<=(A(2) and (not A(1))) and A(0);
Y(6)<=(A(2) and A(1)) and (not A(0));
Y(7)<=(A(2) and A(1)) and A(0);
end dataflow;

37
 41130399_P.SAIVISWATEJA

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_214 is
port (A: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC_VECTOR (7 downto 0));
end DECODER_214;
architecture structural of DECODER_214 is
component not1
port (x1: in STD_LOGIC;
y1: out STD_LOGIC);
end component;

component and1
port (x2, y2, z2: in STD_LOGIC;
a2: out STD_LOGIC);
end component;
begin
n1: not1 port map (A(2), not A(2));
n2: not1 port map (A(1), not A(1));
n3: not1 port map (A(0), not A(0));
i: and1 port map (not A(2), not A(1), not A(0), Y(0));
j: and1 port map (not A(2), not A(1), A(0), Y(1));
k: and1 port map (not A(2), A(1), not A(0), Y(2));
l: and1 port map (not A(2), A(1), A(0), Y(3));
m: and1 port map (A(2), not A(1), not A(0), Y(4));
n: and1 port map (A(2), not A(1), A(0), Y(5));
o: and1 port map (A(2), A(1), not A(0), Y(6));
p: and1 port map (A(2), A(1), A(0), Y(7));
end structural;

--COMPONENT SOURCE CODE:

--NOT GATE
entity not1 is
port (x1: in STD_LOGIC;
y1: out STD_LOGIC);
end not1;
architecture dataflow of not1 is
begin
y1 <= (not x1);
end dataflow;

--AND GATE
entity and1 is

38
 41130399_P.SAIVISWATEJA

Port (x2, y2, z2: in STD_LOGIC;

a2: out STD_LOGIC);
end and1;
architecture dataflow of and1 is
begin
a2 <= (x2 and y2) and z2;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_214 is
port (A: in std_logic_vector (2 downto 0);
Y: out std_logic_vector (7 downto 0));
end DECODER_214;
architecture behavioural of DECODER_214 is
begin
process (A)
begin

Y(0)<=((not A(2)) and (not A(1))) and (not A(0));

Y(1)<=((not A(2)) and (not A(1))) and A(0);
Y(2)<=((not A(2)) and A(1)) and (not A(0));
Y(3)<=((not A(2)) and A(1)) and A(0);
Y(4)<=(A(2) and (not A(1))) and (not A(0));
Y(5)<=(A(2) and (not A(1))) and A(0);
Y(6)<=(A(2) and A(1)) and (not A(0));
Y(7)<=(A(2) and A(1)) and A(0);
end process;
end behavioural;

39
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

● VERILOG CODE:

⮚ DATAFLOW MODELING:

module decoder_d214(input[2:0]a,output[7:0]y);
assign y[0]=(~a[2])&(~a[1])&(~a[0]);
assign y[1]=(~a[2])&(~a[1])&(a[0]);
assign y[2]=(~a[2])&(a[1])&(~a[0]);
assign y[3]=(~a[2])&(a[1])&(a[0]);
assign y[4]=(a[2])&(~a[1])&(~a[0]);
assign y[5]=(a[2])&(~a[1])&(a[0]);
assign y[6]=(a[2])&(a[1])&(~a[0]);
assign y[7]=(a[2])&(a[1])&(a[0]);
endmodule

⮚ STRUCTURAL MODELING:

module decoder_s214(input[2:0]a,output[7:0]y);
and(y[0],(~a[2]),(~a[1]),(~a[0]));
and(y[1],(~a[2]),(~a[1]),(a[0]));
and(y[2],(~a[2]),(a[1]),(~a[0]));
and(y[3],(~a[2]),(a[1]),(a[0]));
and(y[4],(a[2]),(~a[1]),(~a[0]));
and(y[5],(a[2]),(~a[1]),(a[0]));
and(y[6],(a[2]),(a[1]),(~a[0]));
and(y[7],(a[2]),(a[1]),(a[0]));
endmodule

40
 41130399_P.SAIVISWATEJA

⮚ BEHAVIOURAL MODELING:

module decoder_b214(input[2:0]a,output reg[7:0]y);

always @(*)
begin
y=8'd0;
case(a)
3'd0:y[0]=1'b1;
3'd1:y[1]=1'b1;
3'd2:y[2]=1'b1;
3'd3:y[3]=1'b1;
3'd4:y[4]=1'b1;
3'd5:y[5]=1'b1;
3'd6:y[6]=1'b1;
3'd7:y[7]=1'b1;
endcase
end
endmodule

● SIMULATED OUTPUT:

RESULT:

The output of Encoder and Decoder is verified by stimulating and synthesizing the
VHDL/VERILOG code.

41
 41130399_P.SAIVISWATEJA

DATE:
08.02.20
EXPT. NO: MULTIPLEXER AND DEMULTIPLEXER
04 24

PAGE NO:

AIM:

To develop the source code for multiplexer and demultiplexer using VHDL /
VERILOG and obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG and Debug the error if found.
Step4: Verify the output by simulating the source code.
Step5: Write all possible combinations of input using the test bench
Step6: Obtain the synthesis report.

1. 8*1 MULTIPLEXER:

● CIRCUIT DIAGRAM:

42
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

INPUTS (SELECT LINES) OUTP

UT
S S S0 Y
2 1
0 0 0 A0
0 0 1 A1
0 1 0 A2
0 1 1 A3
1 0 0 A4
1 0 1 A5
1 1 0 A6
1 1 1 A7

● VHDL CODE:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_214 is
port (S:in std_logic_vector (2 downto 0);
A: in std_logic_vector (7 downto 0);
Y: out std_logic);
end MUX_214;
architecture dataflow of MUX_214 is
signal s00,s11,s22,i,j,k,l,m,n,o,p:std_logic;
begin
s00<=(not S(0));
s11<=(not S(1));
s22<=(not S(2));
i<=((A(0) and s22) and s11) and s00;
j<=((A(1) and s22) and s11) and S(0);
k<=((A(2) and s22) and S(1)) and s00;
l<=((A(3) and s22) and S(1)) and S(0);
m<=((A(4) and S(2)) and s11) and s00;
n<=((A(5) and S(2)) and s11) and S(0);

43
 41130399_P.SAIVISWATEJA

o<=((A(6) and S(2)) and S(1)) and s00;

p<=((A(7) and S(2)) and S(1)) and S(0);
Y<=((((((i or j) or k) or l) or m) or n) or o) or p;
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_214 is
port (S:in std_logic_vector (2 downto 0);
A: in std_logic_vector (7 downto 0);
Y: out std_logic);
end MUX_214;
architecture structural of MUX_214 is
component not1
port(s1:in std_logic; s2: out std_logic);
end component;
component and1
port(a1, b1, c1, d1:in std_logic;
e1: out std_logic);
end component;
component or1
port(a,b,c,d,e,f,g,h:in std_logic;
z1: out std_logic);
end component;
signal s00, s11, s22, i,j,k,l,m,n,o,p: std_logic;
begin
s00<=not S(0);
s11<=not S(1);
s22<=not S(2);
i<=((A(0) and s22) and s11) and s00;
j<=((A(1) and s22) and s11) and S(0);
k<=((A(2) and s22) and S(1)) and s00;
l<=((A(3) and s22) and S(1)) and S(0);
m<=((A(4) and S(2)) and s11) and s00;
n<=((A(5) and S(2)) and s11) and S(0);
o<=((A(6) and S(2)) and S(1)) and s00;
p<=((A(7) and S(2)) and S(1)) and S(0);
n1:not1 port map (S(0), s00);
n2:not1 port map (S(1), s11);
n3:not1 port map(S(2),s22);
an1:and1 port map(A(0), s22, s11, s00, i);
an2:and1 port map(A(1), s22, s11, S(0), j);
an3:and1 port map(A(2), s22, S(1), s00, k);

44
 41130399_P.SAIVISWATEJA

an4:and1 port map(A(3), s22, S(1), S(0), l);

an5:and1 port map(A(4), S(2), s11, s00, m);
an6:and1 port map(A(5), S(2), s11, S(0), n);
an7:and1 port map(A(6), S(2), S(1), s00, o);
an8:and1 port map(A(7), S(2), S(1), S(0), p);
o1:or1 port map(i,j,k,l,m,n,o,p,Y);
end structural;

--COMPONENT SOURCE CODE:

--NOT GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
port (s1:in std_logic; s2: out std_logic);
end not1;
architecture dataflow of not1 is
begin
s2<= (not s1);
end dataflow;

--AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and1 is
port (a1, b1, c1, d1:in std_logic;
e1: out std_logic);
end and1;
architecture dataflow of and1 is
begin
e1<= ((a1 and b1) and c1) and d1;
end dataflow;

--OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or1 is
port (a,b,c,d,e,f,g,h:in std_logic;
z1: out std_logic);
end or1;
architecture dataflow of or1 is
begin

45
 41130399_P.SAIVISWATEJA

z1<=((((((a or b) or c) or d) or e) or f) or g) or
h;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_B_214 is
port(S:in std_logic_vector(2 downto 0);
A: in std_logic_vector (7 downto 0); Y: out
std_logic);
end MUX_B_214;
architecture behavioural of MUX_B_214 is
begin
process(S,A)
begin
if (S = "000") then Y<=A(0);
elsif (S = "001") then Y<=A(1);
elsif (S = "010") then Y<=A(2);
elsif (S = "011") then Y<=A(3);
elsif (S = "100") then Y<=A(4);
elsif (S = "101") then Y<=A(5);
elsif (S = "110") then Y<=A(6);
else Y<=A(7);
end if;
end process;
end behavioural;

● SIMULATED OUTPUT:

46
 41130399_P.SAIVISWATEJA

● VERILOG CODE:

⮚ DATAFLOW MODELING:

module mux_d214(input[7:0]a, input[2:0]s, output y);

assign
y=((~s[2])&(~s[1])&(~s[0])&a[0])|((~s[2])&(~s[1])&(s[0]
)&a[1])|((~s[2])&(s[1])&(~s[0])&a[2])|((~s[2])&(s[1])&(
s[0])&a[3])|((s[2])&(~s[1])&(~s[0])&a[4])|((s[2])&(~s[1
])&(s[0])&a[5])|((s[2])&(s[1])&(~s[0])&a[6])|((s[2])&(
s [1])&(s[0])&a[7]);
endmodule

⮚ STRUCTURAL MODELING:

module mux_s214(input[7:0]a, input[2:0]s, output y);

wire[7:0]x;
and(x[0],(~s[2]),(~s[1]),(~s[0]),a[0]);
and(x[1],(~s[2]),(~s[1]),(s[0]),a[1]);
and(x[2],(~s[2]),(s[1]),(~s[0]),a[2]);
and(x[3],(~s[2]),(s[1]),(s[0]),a[3]);
and(x[4],(s[2]),(~s[1]),(~s[0]),a[4]);
and(x[5],(s[2]),(~s[1]),(s[0]),a[5]);
and(x[6],(s[2]),(s[1]),(~s[0]),a[6]);
and(x[7],(s[2]),(s[1]),(s[0]),a[7]);
or(x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7]);
endmodule

⮚ BEHAVIOURAL MODELING:

module mux_b214(input[7:0]a, input[2:0]s, output reg

y);
always @(*)
begin
case(s)
3'b000:y=a[0];
3'b001:y=a[1];
3'b010:y=a[2];
3'b011:y=a[3];
3'b100:y=a[4];
3'b101:y=a[5];
3'b110:y=a[6];
3'b111:y=a[7];
endcase
end
endmodule

47
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

2. 1*8 DEMULTIPLEXER:

● CIRCUIT DIAGRAM:

48
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

OUTPU INPU
TS TS
Y Y Y Y Y Y Y Y S S S A
7 6 5 4 3 2 1 0 2 1 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 1
0 0 0 0 0 1 0 0 0 1 0 1
0 0 0 0 1 0 0 0 0 1 1 1
0 0 0 1 0 0 0 0 1 0 0 1
0 0 1 0 0 0 0 0 1 0 1 1
0 1 0 0 0 0 0 0 1 1 0 1
1 0 0 0 0 0 0 0 1 1 1 1

● VHDL CODE:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX_214 is
port(A: in std_logic;
S:in std_logic_vector(2 downto 0);
Y:out std_logic_vector(7 downto 0));
end DEMUX_214;
architecture dataflow of DEMUX_214 is
begin
Y(0)<=((A and (not S(2)))and(not S(1)))and(not S(0));
Y(1)<=((A and (not S(2)))and (not S(1))) and S(0);
Y(2)<=((A and (not S(2))) and S(1)) and (not S(0));
Y(3)<=((A and (not S(2))) and S(1)) and S(0);
Y(4)<=((A and S(2)) and (not S(1))) and (not S(0));
Y(5)<=((A and S(2)) and (not S(1))) and S(0);
Y(6)<=((A and S(2)) and S(1)) and (not S(0));
Y(7)<=((A and S(2)) and S(1)) and S(0);
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

49
 41130399_P.SAIVISWATEJA

entity DEMUX_214 is
port(A:in std_logic;
S:in std_logic_vector(2 downto 0);
Y:out std_logic_vector(7 downto 0));
end DEMUX_214;
architecture structural of DEMUX_214 is
component and1
port(a,b,c,d: in std_logic;
e: out std_logic);
end component;
component not1
port(i: in std_logic; j:out std_logic);
end component;
signal s2,s1,s0:std_logic;
begin
n1:not1 port map(S(2),s2);
n2:not1 port map(S(1),s1);
n3:not1 port map(S(0),s0);
a1:and1 port
map(A,s2,s1,s0,Y(0));
a2:and1 port map(A,s2,s1,S(0),Y(1));
a3:and1 port map(A,s2,S(1),s0,Y(2));
a4:and1 port map(A,s2,S(1),S(0),Y(3));
a5:and1 port map(A,S(2),s1,s0,Y(4));
a6:and1 port map(A,S(2),s1,S(0),Y(5));
a7:and1 port map(A,S(2),S(1),S0,Y(6));
a8:and1 port map(A,S(2),S(1),S(0),Y(7));
end structural;

--COMPONENT SOURCE CODE

--AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is
port(a,b,c,d: in std_logic;
e: out std_logic);
end and1;
architecture dataflow of and1 is
begin
e<=((a and b)and c)and d;
end dataflow;

--NOT GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not1 is
port(i:in std_logic; j:out std_logic);
end not1;

50
 41130399_P.SAIVISWATEJA

architecture dataflow of not1 is

begin
j<= not i;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX_214 is
port(A:in std_logic;
S:in std_logic_vector(2 downto 0);
Y:out std_logic_vector(7 downto 0));
end DEMUX_214;
architecture behavioural of DEMUX_214 is
begin
process(A,S)
begin
Y<= "00000000";
case S is
when "000" => Y(0)<= A;
when "001" => Y(1)<= A;
when "010" => Y(2)<= A;
when "011" => Y(3)<= A;
when "100" => Y(4)<= A;
when "101" => Y(5)<= A;
when "110" => Y(6)<= A;
when "111" => Y(7)<= A;
when others => Y<= "00000000";
end case;
end process;
end behavioural;

● SIMULATED OUTPUT:

51
 41130399_P.SAIVISWATEJA

● VERILOG CODES:

⮚ DATAFLOW MODELING:

module demux_d214(output reg [7:0] Y, input [2:0] A,

input din);
assign Y[0]=din && (~S[2])&&(~S[1])&&(~S[0]);
assign Y[1]=din && (~S[2])&&(~S[1]) && S[0];
assign Y[2]=din && (~S[2])&& S[1] && (~S[0]);
assign Y[3]=din && (~S[2]) && S[1]) && S[0];
assign Y[4]=din && S[2] && (~S[1]) && (~S[0]);
assign Y[5]=din && S[2] && (~S[1]) && S[0];
assign Y[6]=din && S[2] && S[1] && (~S[0]);
assign Y[7]=din && S[2] && S[1] && S[0];
endmodule

⮚ STRUCTURAL MODELING:

module demux_d214(output reg [7:0] Y, input [2:0] A,

input din);
and (Y[0],din,(~S[2]),(~S[1]),(~S[0]));
and (Y[1],din,(~S[2]),(~S[1]),S[0]);
and (Y[2],din,(~S[2]),S[1],(~S[0]));
and (Y[3],din,(~S[2]),S[1],S[0]);
and (Y[4],din,S[2],(~S[1]),(~S[0]));
and (Y[5],din,S[2],(~S[1]),S[0]);
and (Y[6],din,S[2],S[1],(~S[0]));
and (Y[7],din,S[2],S[1],S[0]);
endmodule

⮚ BEHAVIOURAL MODELING:

module demux_d214(output reg [7:0] Y, input [2:0] A,

input din);
always @(*)
begin
Y=8'b00000000;
case (A)
3'b000: Y[0] = din;
3'b001: Y[1] = din;
3'b010: Y[2] = din;
3'b011: Y[3] = din;
3'b100: Y[4] = din;
3'b101: Y[5] = din;
3'b110: Y[6] = din;
3'b111: Y[7] = din;
endcase

52
 41130399_P.SAIVISWATEJA

end
endmodule

● SIMULATED OUTPUT:

RESULT:

The output of Multiplexer and Demultiplexer is verified by stimulating and

synthesizing the VHDL/VERILOG code.

53
 41130399_P.SAIVISWATEJA

DATE:
22.02.20
EXPT. NO: RIPPLE CARRY ADDER
05 24

PAGE NO:

AIM:

To develop the source code for Ripple Carry Adder using VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

CIRCUIT DIAGRAM:

54
 41130399_P.SAIVISWATEJA

TRUTH TABLE:

INPU OUTPUTS
TS
C A A A A B B B B S S S S C
0 3 2 1 0 3 2 1 0 3 2 1 0 4
0 0000 0000 0000 0
0 0001 0001 0010 0
0 0010 0010 0100 0
0 0011 0011 0110 0
0 0100 0100 1000 0
0 010 1 010 1 1010 0
0 0110 0110 1100 0
0 0111 0111 1110 0
0 1000 1000 0000 1
0 1001 1001 0010 1
0 1010 1010 0100 1
0 1011 1011 0110 1
0 1100 1100 1000 1
0 1101 1101 1010 1
0 1110 1110 1100 1
0 1111 1111 1110 1
1 1111 1111 1111 1

55
 41130399_P.SAIVISWATEJA

VHDL CODES:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RCA_214 is port(C0:
in STD_LOGIC;
A,B: in std_logic_vector(3 downto 0);
C4: out STD_LOGIC;
S: out std_logic_vector(3 downto 0));
end RCA_214;
architecture dataflow of RCA_214 is
signal C1,C2,C3:STD_LOGIC;
begin
C1<=((A(0)and B(0))or (B(0)and C0))or (C0 and
A(0));
C2<=((A(1)and B(1))or (B(1)and C1)) or (C1 and
A(1));
C3<=((A(2)and B(2))or (B(2)and C2)) or (C2 and
A(2));
S(0)<= ((A(0) xor B(0)) xor C0);
S(1)<= ((A(1) xor B(1)) xor C1);
S(2)<= ((A(2) xor B(2))xor C2);
S(3)<= ((A(3) xor B(3))xor C3);
C4<= ((A(3) and B(3))or(B(3) and C3)) or (C3 and
A(3));
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RCA_214 is port(C0:
in STD_LOGIC;
A,B: in std_logic_vector(3 downto 0);
C4: out STD_LOGIC;
S: out std_logic_vector(3 downto 0));
end RCA_214;
architecture structural of RCA_214 is
component fa
port(x,y,z:in std_logic;
s,c:out std_logic);
end component;
signal C1,C2,C3: std_logic;

56
 41130399_P.SAIVISWATEJA

begin
C1<=((A(0)and B(0))or (B(0)and C0))or (C0 and A(0));
C2<=((A(1)and B(1))or (B(1)and C1)) or (C1 and A(1));
C3<=((A(2)and B(2))or (B(2)and C2)) or (C2 and A(2));
x1: fa port map (A(0),B(0),C0,S(0),C1);
x2: fa port map (A(1),B(1),C1,S(1),C2);
x3: fa port map (A(2),B(2),C2,S(2),C3);
x4: fa port map (A(3),B(3),C3,S(3),C4);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa is
port (x,y,z:in STD_LOGIC;s,c:out STD_LOGIC);
end fa;
architecture dataflow of fa is
begin
s <=(x xor y) xor z;
c <= (x and y) or (y and z) or (z and x);
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RCA_214 is port(C0:
in STD_LOGIC;
A,B: in std_logic_vector(3 downto 0);
C4: out STD_LOGIC;
S: out std_logic_vector(3 downto 0));
end RCA_214;
architecture behavioural of RCA_214 is
begin
process(A,B,C0)
begin
S<=A+B+C0;
if (A > "0111" or B > "0111")then
C4<='1';
else
C4<='0';
end if;
end process;
end behavioural;

57
 41130399_P.SAIVISWATEJA

SIMULATED OUTPUT:

VERILOG CODE:

⮚ DATAFLOW MODELING:

module rca_d214(a,b,c0,c4,s);
input c0;
input [3:0]a,b;
output [3:0]s;
output c4;
wire[3:1]c;
assign c1=(a[0]&b[0])|(b[0]&c0)|(c0&a[0]);
assign c2=(a[1]&b[1])|(b[1]&c[1])|(c[1]&a[1]);
assign c3=(a[2]&b[2])|(b[2]&c[2])|(c[2]&a[2]);
assign s[0]= (a[0] ^ b[0]) ^ c0;
assign s[1]= (a[1] ^ b[1]) ^ c[1];
assign s[2]= (a[2] ^ b[2]) ^ c[2];
assign s[3]= (a[3] ^ b[3]) ^ c[3];
assign c4 = (a[3] & b[3])|(b[3] & c[3])|(c[3] &
a[3]);
endmodule

⮚ STRUCTURAL MODELING:

module RCA_214(input[3:0]a,b, input cin,

output[3:0]s ,output cout);
wire [2:0]c;
FA_adder1(a[0],b[0],cin,s[0],c[0]),
adder2(a[1],b[1],c[0],s[1],c[1]),
adder3(a[2],b[2],c[1],s[2],c[2]),
adder4(a[3],b[3],c[2],s[3],cout);

58
 41130399_P.SAIVISWATEJA

endmodule
module FA(input a,b,c, output s,cout);
assign s=a^b^c;
assign cout= (a&b)|(b&c)|(c&a);
endmodule

⮚ BEHAVIOURAL MODELING:

module rca_b214(input[3:0]a,b,input cin, output

reg[0:3]s, output reg co);
always @(*)
begin
s = a+b+cin;
if (a > 4'b0111 || b > 4'b0111)
begin
co = 1;
end
else
begin
co = 0;
end
end
endmodule

SIMULATED OUTPUT:

59
 41130399_P.SAIVISWATEJA

RESULT

The output of 4-bit Ripple Carry Adder is verified by stimulating and synthesizing
the VHDL/VERILOG code.

60
 41130399_P.SAIVISWATEJA

DATE:
22.02.20
EXPT. NO: CODE CONVERTERS
06 24

PAGE NO:

AIM:

To develop the source code for code converters using VHDL/VERILOG and obtain
the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. BINARY TO GRAY CODE CONVERTER:

⮚ CIRCUIT DIAGRAM:

4 – bit Binary to Gray code converter

61
 41130399_P.SAIVISWATEJA

⮚ TRUTH TABLE:

BINARY INPUT GRAY OUTPUT

B3 B2 B1 B0 G3 G2 G3 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

⮚ VHDL CODES:

● DATAFLOW MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECOV_214 is
port(B:in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
end CODECOV_214;
architecture dataflow of CODECOV_214 is
begin
G(3)<=B(3);
G(2)<=(B(2) XOR B(3));

62
 41130399_P.SAIVISWATEJA

G(1)<=(B(1) XOR B(2));

G(0)<=(B(0) XOR B(1));
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECOV_214 is
port(B:in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
end CODECOV_214;
architecture structural of CODECOV_214 is
component xor1
port(a,b:in std_logic; c:out std_logic);
end component;
begin
x1:xor1 port map (B(3),'0',G(3));
x2:xor1 port map (B(2),B(3),G(2));
x3:xor1 port map (B(1),B(2),G(1));
x4:xor1 port map (B(0),B(1),G(0));
end structural;

--COMPONENT SOURCE CODE

--XOR GATE
library IEEE;
use IEEE.std_logic_1164.ALL;
entity xor1 is
port(a,b:in std_logic; c:out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c <= a XOR B;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECOV_214 is
port(B:in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
end CODECOV_214;
architecture behavioural of CODECOV_214 is
begin
process(B)
begin

63
 41130399_P.SAIVISWATEJA

G(3)<=B(3);
G(2)<=(B(2) XOR
B(3));
G(1)<=(B(1) XOR B(2));
G(0)<=(B(0) XOR B(1));
end process;
end behavioural;

⮚ SIMULATED OUTPUT:

⮚ VERILOG CODE:

● DATAFLOW MODELING:

module codeconv_d214(input [3:0]b,output [3:0]g);

assign g[3] = b[3];
assign g[2] = b[3]^b[2];
assign g[1] = b[2]^b[1];
assign g[0] = b[1]^b[0];
endmodule

● STRUCTURAL MODELING:

module codeconv_s214(input [3:0]b,output [3:0]g);

xor(g[3],b[3]);
xor(g[2],b[3],b[2]);
xor(g[1],b[2],b[1]);
xor(g[0],b[1],b[0]);
endmodule

● BEHAVIOURAL MODELING:

module codeconv_s214(input [3:0]b,output reg [3:0]g);

always @(*)
begin

64
 41130399_P.SAIVISWATEJA

g[3] = b[3];
g[2] = b[3]^b[2];
g[1] = b[2]^b[1];
g[0] = b[1]^b[0];
end
endmodule

⮚ SIMULATED OUTPUT:

2. GRAY TO BINARY CODE CONVERTER:

⮚ CIRCUIT DIAGRAM:

4 – bit Binary to Gray code converter

65
 41130399_P.SAIVISWATEJA

⮚ TRUTH TABLE:

BINARY OUTPUT GRAY INPUT

B3 B2 B1 B0 G3 G2 G3 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

⮚ VHDL CODES:

● DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CODECONVGTB_214 is
port(G:in std_logic_vector(3 downto 0);
B:out std_logic_vector(3 downto 0));
end CODECONVGTB_214;
architecture dataflow of CODECONVGTB_214 is
begin
B(3)<=G(3);
B(2)<=G(3) XOR G(2);

66
 41130399_P.SAIVISWATEJA

B(1)<=G(1) XOR (G(3) XOR G(2));

B(0)<=G(0) XOR (G(1) XOR (G(3) XOR G(2)));
end dataflow;

● STRUCTURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECONVGTB_214 is
port(G:in std_logic_vector(3 downto 0);
B:out std_logic_vector(3 downto 0));
end CODECONVGTB_214;
architecture structural of CODECONVGTB_214 is
component xor1
port(a,b:in std_logic; c:out std_logic);
end component;
begin
x1:xor1 port map (G(3),'0',B(3));
x2:xor1 port map (G(2),G(3),B(2));
x3:xor1 port map (G(1),G(3),G(2),B(1));
x4:xor1 port map (G(0),G(1),G(3),G(2),B(0));
end structural;

--COMPONENT SOURCE CODE

--XOR GATE
library IEEE;
use IEEE.std_logic_1164.ALL;
entity xor1 is
port(a,b:in std_logic; c:out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c <= a XOR B;
end dataflow;

● BEHAVIOURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECONVGTB_214 is
port(G:in std_logic_vector(3 downto 0);
B:out std_logic_vector(3 downto 0));
end CODECONVGTB_214;
architecture behavioural of CODECONVGTB_214 is
begin
process(G)
begin

67
 41130399_P.SAIVISWATEJA

B(3)<=G(3);
B(2)<=G(3) XOR G(2); B(1)<=G(1)
XOR (G(3) XOR G(2));
B(0)<=G(0) XOR (G(1) XOR (G(3) XOR G(2)));
end process;
end behavioural;

⮚ SIMULATED OUTPUT:

⮚ VERILOG CODES:

● DATAFLOW MODELING:

module codeconvgtb_d214(input [3:0]b,output [3:0]g);

assign b[3] = g[3];
assign b[2] = g[3]^g[2];
assign b[1] = g[1]^g[3]^g[2];
assign b[0] = g[0]^g[1]^g[3]^g[2];
endmodule

● STRUCTURAL MODELING:

module codeconvgtb_s214(input [3:0]b,output [3:0]g);

xor(b[3],g[3]);
xor(b[2],g[3],g[2]);
xor(b[1],g[3],g[2],g[1]);
xor(b[0],g[0],g[1],g[3],g[2]);
endmodule

● BEHAVIOURAL MODELING:

module codeconvgtb_s214(input [3:0]b,output reg

[3:0]g);

68
 41130399_P.SAIVISWATEJA

always @(*)
begin
b[3] = g[3];
b[2] = g[3]^g[2];
b[1] = g[1]^g[3]^g[2];
b[0] = g[0]^g[1]^g[3]^g[2];
end
endmodule

⮚ SIMULATED OUTPUT:

RESULT:

The output of Code Converters is verified by stimulating and synthesizing the

VHDL/VERILOG code.

69
 41130399_P.SAIVISWATEJA

DATE:
22.02.20
EXPT. NO: FLIP
07 24
FLOPS
PAGE NO:

AIM:

To develop the source code for flip flops using VHDL /VEROLOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. SR FLIP FLOP:

● CIRCUIT SCHEMATIC:

70
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

R C S R Q Q1
S
T
1 - - - 0 1
0 1 0 0 NO NO
CHANGE CHANGE
0 1 0 1 0 1
0 1 1 0 1 0
0 1 1 1 X X

● VHDL CODE:

BEHAVIOUR MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SRFF_B214 is
port(s,r,c,rst:in std_logic;
q,q1:inout std_logic);
end SRFF_B214;
architecture behavioural of SRFF_B214 is
begin
process(s,r,c,rst)
begin
if(rst='1')then
q<='0';q1<='1';
elsif(c='1' and c'event)then
if(s='0' and r='0')then
q<=q; q1<=q1;
elsif(s='0' and r='1')then
q<='0'; q1<='1';
elsif(s='1' and r='0')then
q<='1';q1<='0';
else
q<='X';q1<='X';
end if;
end if;
end process;
end behavioural;

71
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

2. JK FLIP FLOP:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

R C J K Q Q1
S
T
1 - - - 0 1
0 1 0 0 NO NO
CHANGE CHANGE
0 1 0 1 0 1
0 1 1 0 1 0
0 1 1 1 TOGGLE TOGGLE

72
 41130399_P.SAIVISWATEJA

● VHDL CODE:

BEHAVIOURAL MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JKFF_214 is
port(j,k,c,rst:in std_logic;
q,q1:inout std_logic);
end JKFF_214;
architecture behavioural of JKFF_214 is
begin
process(j,k,c,rst)
begin
if(rst='1') then
q<='0';q1<='1';
elsif(c='1' and c'event)then
if(j='0' and k='0')then
q<=q;q1<=q1;
elsif(j='0' and k='1')then
q<='0';q1<='1';
elsif(j='1' and k='0')then
q<='1';q1<='0';
else
q<=not q;
q1<=not q1;
end if;
end if;
end process;
end behavioural;

● SIMULATED OUTPUT:

73
 41130399_P.SAIVISWATEJA

3. D FLIP FLOP:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

RST C D Q Q1
1 - - 0 1
0 1 0 0 1
0 1 1 1 0

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_214 is
port(d,c,rst:in std_logic;
q,q1:inout std_logic);
end DFF_214;
architecture behavioural of DFF_214 is
begin
process(d,c,rst)
begin
if(rst='1') then
q<='0';q1<='1';
elsif(c='1' and c'event)then
if(d='0')then
q<='0';q1<='1';
else
q<='1';q1<='0';
end if;
end if;
end process;
end behavioural;

74
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

4. T FLIP FLOP:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

RST C T Q Q1
1 - - 0 1
NO NO
0 1 0
CHAN CHAN
GE GE
0 1 1 TOGG TOGG
LE LE

75
 41130399_P.SAIVISWATEJA

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF_214 is
port(t,c,rst:in std_logic;
q,q1:inout std_logic);
end TFF_214;
architecture behavioural of TFF_214 is
begin
process(t,c,rst)
begin
if(rst='1') then
q<='0';q1<='1';
elsif(c='1' and c'event)then
if(t='0')then
q<=q;q1<=q1;
else
q<=not q;q1<=not q1;
end if;
end if;
end process;
end behavioural;

● SIMULATED OUTPUT;

76
 41130399_P.SAIVISWATEJA

VERILOG CODE:

1. SR FLIP FLOP:

module srff_214(input s,r,clk,output reg q,qbar);

always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(s==0 && r==0)
begin
q=q; qbar=qbar;
end
else if(s==0 && r==1)
begin
q=1'b0; qbar=1'b1;
end
else if(s==1 && r==0)
begin
q=1'b1; qbar=1'b0;
end
else if(s==1 && r==1)
begin
q=1'bx; qbar=1'bx;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end

77
 41130399_P.SAIVISWATEJA

2. JK FLIP FLOP:

module jkff_214(input j,k,clk,output reg q,qbar);

always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(j==0 && k==0)
begin
q=q; qbar=qbar;
end
else if(j==0 && k==1)
begin
q=1'b0; qbar=1'b1;
end
else if(j==1 && k==0)
begin
q=1'b1; qbar=1'b0;
end
else if(j==1 && k==1)
begin
q=~q; qbar=~qbar;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
endmodule

78
 41130399_P.SAIVISWATEJA

3. D FLIP FLOP:

module dff_214(input d,clk,output reg q,qbar);

always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(d==0)
begin
q=1'b0; qbar=1'b1;
end
else
if(d==1)
begin
q=1'b1; qbar=1'b0;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
endmodule

79
 41130399_P.SAIVISWATEJA

4. T FLIP FLOP:

module tff_214(input t,clk,output reg q,qbar);

always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(t==0)
begin
q=1'b1; qbar=1'b0;
end
else if(t==1)
begin
q=1'b0; qbar=1'b1;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
endmodule

RESULT:

The output of Flip Flops is verified by stimulating and synthesizing the VHDL/
VERILOG code.

80
 41130399_P.SAIVISWATEJA

DATE:
07.03.20
EXPT. NO: SHIFT REGISTERS
08 24

PAGE NO:

AIM:

To develop the source code for shift registers using VHDL/VERILOG and obtain
the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. SISO SHIFT REGISTER:

● CIRCUIT SCHEMATIC:

81
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

C R D (DATA Q Q1
(CLK) (RESET) IN)
- 1 - - 00
00
1 0 10
00
2 0 1 0 11
00
3 0 11
10
4 1 11
11

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SISO_214 is
port(c,d,r:in std_logic;
q: out std_logic);
end SISO_214;
architecture behavioural of SISO_214 is
signal q1: std_logic_vector(3 downto 0);
begin
process(c,d,r)
begin
if (r='1') then
q1<="0000";
elsif(c='1' and c'event) then
q1(3)<=d;
q1(2 downto 0)<=q1(3 downto 1);
q<=q1(1);
end if;
end process;
end behavioural;

● SIMULATED OUTPUT:

82
 41130399_P.SAIVISWATEJA

83
 41130399_P.SAIVISWATEJA

2. SIPO SHIFT REGISTER:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

C R D (DATA Q Q1
(CLK) (RESET) IN)
- 1 - - 00
00
1 01 10
11 00
2 0 1 00 11
11 00
3 00 11
01 10
4 00 11
00 11

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SR_SIPO_214 is
port(c,d,r: in std_logic;
q:out std_logic_vector(3 downto 0));
end SR_SIPO_214;
architecture behavioural of SR_SIPO_214 is
signal q1: std_logic_vector(3 downto 0);
begin

84
 41130399_P.SAIVISWATEJA
process(c,d,r)
begin

85
 41130399_P.SAIVISWATEJA

if(r='1')then
q1<="0000";
elsif(c='1' and c'event)then
q1(3)<=d;
q1(2)<=q1(3);
q1(1)<=q1(2);
q1(0)<=q1(1);
end if;
end process;
q<=(not q1);
end behavioural;

● SIMULATED OUTPUT:

86
 41130399_P.SAIVISWATEJA

3. PISO SHIFT REGISTER:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

C RES Sin Pin So Shifts

L ET (Load) ut (sr)
K
- 1 - - 0 0000
1 0 0000
2 0 0001
3 1111 0 0011
0 1 (Sam
4 ple 0 0111
5 Data) 0 1111
6 1 1111

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
entity PISO_214 is

87
 41130399_P.SAIVISWATEJA

port (clk,reset,sin: in std_logic;

pin: in std_logic_vector(3 downto 0);
sout: out std_logic);
end PISO_214;
architecture behavioral of PISO_214 is
signal sr: std_logic_vector(3 downto 0);
begin
process (clk, reset)
begin
if reset = '1' then
sr <= (others => '0');
sout <= '0';
elsif rising_edge(clk) then
sr <= pin;
sout <= sr(3);
sr <= sr(2 downto 0) & sin;
end if;
end process;
end behavioral;

● SIMULATED OUTPUT:

88
 41130399_P.SAIVISWATEJA

4. PIPO SHIFT REGISTER:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

C R Din Dout
L S
K T
- 1 - 0000
1 0000
0000
2 0000
3 0000
0001
4 0001
0
5 0001
0010
6 0010
7 0010
0011
8 0011

● VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PIPO_214 is
port(clk,rst: in std_logic;

89
 41130399_P.SAIVISWATEJA

din: in std_logic_vector(3 downto 0);

dout: out std_logic_vector(3 downto 0));
end PIPO_214;
architecture behavioural of PIPO_214 is
begin
process(rst,clk,din)
begin
if (rst='1') then
dout<="0000";
elsif (rst='0') then
if (rising_edge(clk))then
dout<=din;
end if;
end if;
end process;
end behavioural;

● SIMULATED OUTPUT:

VERILOG CODE:

1. SISO SHIFT REGISTER:

module siso_214(input si,rst,clk,output reg so);

reg [3:0]q;
always@(si,rst,clk)
begin
if(rst == 1)
begin
so = 1'bZ;
q = 4'b0000;
end

90
 41130399_P.SAIVISWATEJA

else
begin
q[3] = si;
q[2] = q[3];
q[1] = q[2];
q[0] = q[1];
so = q[1];
end
end
endmodule

2. SIPO SHIFT REGISTER:

module sipo_214(si,rst,clk,po);
input si,rst,clk;
output [0:3]po; reg
[0:3]po;
always@(si,rst,clk)
begin
if(rst == 1)
begin
po = 4'bZ;
end
else
begin
po[0] = si;
po[1] = po[0];
po[2] = po[1];
po[3] = po[2];
end
end
endmodule

91
 41130399_P.SAIVISWATEJA

3. PISO SHIFT REGISTER:

module piso_214(pi,rst,clk,so);
input [3:0]pi;
input rst,clk;
output so; reg
so;
reg [3:0]d;
always@(rst,clk)
begin
if(rst == 1)
begin
so = 1'b0;
d = pi;
end
else
begin
d = d>>1'b1;
so = d;
end
end
endmodule

92
 41130399_P.SAIVISWATEJA

4. PIPO SHIFT REGISTER:

module pipo_214(pi,rst,clk,po);
input[0:3]pi;
input rst,clk;
output reg[0:3]po;
always@(pi,rst,clk)
begin
if (rst==1)
begin
po=4'bZ;
end
else
begin
po=pi;
end
end
endmodule

RESULT:

The output of Shift Registers is verified by stimulating and synthesizing the

VHDL/VERILOG code.

93
 41130399_P.SAIVISWATEJA

DATE:
07.03.20
EXPT. NO: COUNTER
09 24
S
PAGE NO:

AIM:

To develop the source code for synchronous and asynchronous counters using
VHDL/VERILOG and obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. SYNCHRONOUS COUNTER:

● CIRCUIT SCHEMATIC:

94
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

RESE C Q Q_BAR
T L
K
1 - 0000 1111
1 0000 1111
2 0001 1110
3 0010 1101
4 0011 1100
0
5 1000 0111
6 0101 0101
7 0110 1001
8 0111 1000

● VHDL CODE:

⮚ BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SCOUNTER_214 is
port (clk,reset : in STD_LOGIC;
q,q_bar: out STD_LOGIC_VECTOR (3 downto 0));
end SCOUNTER_214;
architecture Behavioral of SCOUNTER_214 is
begin
process(clk, reset)
variable count : std_logic_vector(3 downto 0);
begin
if (reset = '1') then
count := "0000";
elsif (rising_edge(clk)) then
count := count + 1;
end if;
q <= count;
q_bar <= not count;
end process;
end Behavioral;

95
 41130399_P.SAIVISWATEJA

⮚ STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SCOUNTER_214 is
port(rst,clk : in std_logic;
q,qbar : inout std_logic_vector(3 downto 1));
end SCOUNTER_214;
architecture structural of SCOUNTER_214 is
component jk_ff
port(j,k,clk,rst : in std_logic;
q,qbar : inout std_logic);
end component; component
and_gate port(a,b : in
std_logic;
c : out std_logic);
end component;
signal p : std_logic;
begin
jk1 : jk_ff port map('1','1',clk,rst,q(1),qbar(1));
jk2 : jk_ff port map(q(1),q(1),clk,rst,q(2),qbar(2));
a1 : and_gate port map(q(1),q(2),p);
jk3 : jk_ff port map(p,p,clk,rst,q(3),qbar(3));
end structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is port(j,k,clk,rst
: in std_logic;
q,qbar : inout std_logic);
end jk_ff;
architecture behavioural of jk_ff is
begin
process(j,k,clk,rst)
begin
if(rst='1')then
q<='0';
qbar<='1';
elsif(clk='1'and clk'event)then
if(j='0' and k='0')then
q<=q;
qbar<=qbar;
elsif(j='0' and k='1')then

96
 41130399_P.SAIVISWATEJA

q<='0';
qbar<='1';
elsif(j='1' and k='0')then
q<='1';
qbar<='0';
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end behavioural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and_gate is
port(a,b : in std_logic;
c : out std_logic);
end and_gate;
architecture dataflow of and_gate is
begin
c <= a and b;
end dataflow;

● SIMULATED OUTPUT:

97
 41130399_P.SAIVISWATEJA

2. ASYNCHRONOUS COUNTER:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

RESE C Q Q_BAR
T L
K
1 - 0000 1111
1 0001 1110
2 0010 1101
3 0011 1100
0 4 1000 0111
5 0101 0101
6 0110 1001
7 0111 1000

● VHDL CODE:

⮚ BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

98
 41130399_P.SAIVISWATEJA

entity ASCOUNTER_214 is
port (clk,reset : in STD_LOGIC;
q,q_bar : out STD_LOGIC_VECTOR (3 downto 0));
end ASCOUNTER_214;
architecture Behavioral of ASCOUNTER_214 is
begin
process(clk, reset)
variable count : std_logic_vector(3 downto 0);
begin
if (reset = '1') then
count := "0000";
elsif (clk'event and clk = '1') then
count := count + 1;
end if;
q <= count;
q_bar <= not count;
end process;
end Behavioral;

⮚ STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ASCOUNTER_214 is
port(rst,clk : in std_logic;
q,qbar : inout std_logic_vector(3 downto 0));
end ASCOUNTER_214;
architecture structural of ASCOUNTER_214 is
component t_ff
port(t,clk,rst : in std_logic;
q,qbar : inout std_logic);
end component;
begin
t0 : t_ff port map('1',clk,rst,q(0),qbar(0));
t1 : t_ff port map('1',q(0),rst,q(1),qbar(1));
t2 : t_ff port map('1',q(1),rst,q(2),qbar(2));
t3 : t_ff port map('1',q(2),rst,q(3),qbar(3));
end structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t_ff is

99
 41130399_P.SAIVISWATEJA

port(t,clk,rst : in std_logic;
q,qbar : inout std_logic);
end t_ff;
architecture behavioural of t_ff is
begin
process(t,clk,rst)
begin
if(rst='1')then
q<='0';
qbar<='1';
elsif(clk='1'and clk'event)then
if(t='0')then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end behavioural;

● SIMULATED OUTPUT:

100
 41130399_P.SAIVISWATEJA

VERILOG CODE:

1. SYNCHRONOUS COUNTER:

⮚ BEHAVIOURAL MODELING:

module scounter_214(input clk,input rst,output reg

[3:0]count);
always @(posedge clk)
begin
if (rst)
begin
count = 4'b0000;
end
else
begin
count = count + 1;
end
end
endmodule

⮚ STRUCTURAL MODELING:

module scounter_214rst,clk,q,qbar);
input rst,clk;
output [3:1]q,qbar;
wire p;
jk_ff
JK1(1'b1,1'b1,rst,clk,q[1],qbar[1]),
JK2(q[1],q[1],rst,clk,q[2],qbar[2]);
and_gate1
A1(q[1],q[2],p);
jk_ff
JK3(p,p,rst,clk,q[3],qbar[3]);
endmodule
module jk_ff(j,k,rst,clk,q,qbar);
input j,k,rst,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
if(rst==1)
begin
q=1'b0;qbar=1'b1;
end
else if(j==0 && k==0)

101
 41130399_P.SAIVISWATEJA

begin
q=q;qbar=qbar;
end
else if(j==0 && k==1)
begin
q=1'b0;qbar=1'b1;
end
else if(j==1 && k==0)
begin
q=1'b1;qbar=1'b0;
end
else
begin
q=~q;qbar=~qbar;
end
end
endmodule

module and_gate1(a,b,p);
input a,b;
output p;
reg p;
always@(a,b)
begin
p = a & b;
end
endmodule

2. ASYNCHRONOUS COUNTER:

⮚ BEHAVIOURAL MODELING:

module acounter_214(clk,rst,count);
input clk,rst;
output [3:0]count;
reg [3:0]q;

102
 41130399_P.SAIVISWATEJA

always @(posedge clk or posedge rst)

begin
if (rst)
q = 4'b0000;
else
q = q + 1'b1;
end
assign count = q;
endmodule

⮚ STRUCTURAL MODELING:

module acounter_214 (rst,clk,q,qbar);

input rst,clk;
output [3:0]q,qbar;
t_ff
T1(1'b1,rst,clk,q[0],qbar[0]),
T2(1'b1,rst,qbar[0],q[1],qbar[1]),
T3(1'b1,rst,qbar[1],q[2],qbar[2]),
T4(1'b1,rst,qbar[2],q[3],qbar[3]);
endmodule

module t_ff(t,rst,clk,q,qbar);
input t,rst,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
if(rst==1)
begin
q=1'b0;qbar=1'b1;
end
else if(t==0)
begin
q=q;qbar=qbar;
end
else
begin
q=~q;qbar=~qbar;
end
end
endmodule

103
 41130399_P.SAIVISWATEJA

RESULT:

The output of Synchronous and Asynchronous counter is verified by stimulating

and synthesizing the VHDL/VERILOG code.

104
 41130399_P.SAIVISWATEJA

DATE:
14.03.20
EXPT. NO: FINITE STATE MACHINES
10 24

PAGE NO:

AIM:

To develop the source code for Moore and Mealy FSM in VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. MOORE FSM:

● CIRCUIT SCHEMATIC:

105
 41130399_P.SAIVISWATEJA

● TRUTH TABLE:

IN O PRESE NEX
CLK UT COMMENTS
NT T
X Y STAT STA
E TE
1 0 a b
2 0 b c
Transition Occurs
3 1 0 c d
4 1 d a
5 0 a b Transition Stops
Here
0
The state transition
6 0 b b stops unless the
input is 1
regardless of clk.

● VHDL CODE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MOOREFSM_214 is
port(x,clk:in std_logic;
y:out std_logic);
end MOOREFSM_214;
architecture behavioural of MOOREFSM_214 is
type state is (a,b,c,d);
signal p_state,n_state: state;
begin
process(clk)
begin
if (clk='1') then
p_state<=n_state;
end if;
end process;
process(clk)
begin
if (clk='1') then
case n_state is
when a=>y<='0';
if x='1' then
y<='0';
n_state<=b;

106
 41130399_P.SAIVISWATEJA
else

107
 41130399_P.SAIVISWATEJA

n_state<=a;
end if;
when b=>y<='0';
if x='1' then
n_state<=c;
else
n_state<=b;
end if;
when c=>y<='0';
if x='1' then
n_state<=d;
else
n_state<=c;
end if;
when d=>y<='1';
if x='1' then
n_state<=a;
else
n_state<=d;
end if;
end case;
end if;
end process;
end behavioural;

● SIMULATED OUTPUT:

● VERILOG CODE:

module moorefsm_214(x,clk,y);
input x,clk;
output y;
reg y;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]moore_state=0;
always @ (posedge clk)
begin

108
 41130399_P.SAIVISWATEJA

case(moore_state)
st0:
begin
if(x==1'b1)
begin
moore_state=st1;
y=0;
end
end
st1:
begin
if(x==1'b1)
begin
moore_state=st2;
y=0;
end
end
st2:
begin
if(x==1'b1)
begin
y=0;
moore_state=st3;
end
end
st3:
begin
if(x==1'b1)
begin
moore_state=st0;
y=1;
end
end
endcase
end
endmodule

● SIMULATED OUTPUT:

109
 41130399_P.SAIVISWATEJA

2. MEALY FSM:

● CIRCUIT SCHEMATIC:

● TRUTH TABLE:

IN O PRESE NEX
CLK UT COMMENTS
NT T
X Y STAT STA
E TE
1 0 a b
2 1 b c
Transition Occurs
3 1 0 c d
4 1 d a
5 0 a a The state transition
0 stops unless the
6 0 a a input is 1
regardless of clk.

● VHDL CODE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MEALYFSM_214 is
port(x,clk:in std_logic;
y:out std_logic);
end MEALYFSM_214;
architecture behavioural of MEALYFSM_214 is

110
 41130399_P.SAIVISWATEJA

type state is (a,b,c,d);

signal p_state,n_state: state;
begin
process(clk)
begin
if (clk='1') then
p_state<=n_state;
end if;
end process;
process(p_state,x)
begin
case p_state is
when a=>
if x='1' then
y<='0';
n_state<=b;
else
y<='0';
n_state<=a;
end if;
when b=>
if x='1' then
y<='1';
n_state<=c;
else
y<='0';
n_state<=b;
end if;
when c=>
if x='1' then
y<='0';
n_state<=d;
else
y<='0';
n_state<=c;
end if;
when d=>
if x='1' then
y<='1';
n_state<=a;
else
y<='1';
n_state<=d;
end if;
end case;
end process;
end behavioural;

111
 41130399_P.SAIVISWATEJA

● SIMULATED OUTPUT:

● VERILOG CODE:

module mealyfsm_214(x,clk,y);
input x,clk;
output reg y;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]mealy_state=0;
always @(posedge clk)
begin
case(mealy_state)
st0:
begin
if(x==1'b1)
begin
mealy_state=st1;
y=1;
end
else
begin
y=0;
end
end
st1:
begin
if(x==1'b1)
begin
mealy_state=st2;
y=1;
end
else
begin
y=0;
end
end
st2:

112
 41130399_P.SAIVISWATEJA

begin
if(x==1'b1)
begin
mealy_state=st3;
y=1;
end
else
begin
y=0;
end
end
st3:
begin
if(x==1'b1)
begin
mealy_state=st0;
y=1;
end
else
begin
y=1;
end
end
endcase
end
endmodule

● SIMULATED OUTPUT:

RESULT:

The output of Mooley and Mealy FSM is verified by stimulating and synthesizing
the VHDL/VERILOG code.

113
 41130399_P.SAIVISWATEJA

DATE:
14.03.20
EXPT. NO: ARITHMETIC AND LOGIC UNIT
11 24
DESIGN
PAGE NO:

AIM:

To develop the source code for Arithmetic and Logic Unit in VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

CIRCUIT SCHEMATIC:

114
 41130399_P.SAIVISWATEJA

TRUTH TABLE:

CLK OPR ANS(a,b)

000 Addition (a+b)
001 Subtraction (a-b)
010 2s Complement of ‘a’
011 2s Complement of ‘b’
1
100 Increment ‘a’ (a+1)
101 Increment ‘b’ (b+1)
110 Decrement ‘a’ (a-1)
111 Decrement ‘b’ (b-1)
000 Logical AND (a AND b)
001 Logical OR (a OR b)
010 Logical NAND (a NAND
b)
0 011 Logical NOR (a NOR b)
100 Logical XOR (a XOR b)
101 Logical XNOR (a XNOR
b)
110 Complement of ‘a’ (NOT
a)
111 Complement of ‘b’ (NOT
b)

115
 41130399_P.SAIVISWATEJA

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_214 is
port(clk: in std_logic;
a,b: in std_logic_vector(7 downto 0);
opr: in std_logic_vector(2 downto 0);
ans: out std_logic_vector(7 downto 0));
end ALU_214;
architecture behavioural of ALU_214 is
begin
process(a,b,opr,clk)
begin
if(clk='1')then
case opr is
when "000" =>ans<= a+b;
when "001" =>ans<= a-b;
when "010" =>ans<= (not a)+1;
when "011" =>ans<= (not b)+1;
when "100" =>ans<= a+1;
when "101" =>ans<= b+1;
when "110" =>ans<= a-1;
when "111" =>ans<= b-1;
when others =>ans<= "00000000";
end case;
elsif(clk='0')then
case opr is
when "000" =>ans<= a and b;
when "001" =>ans<= a or b;
when "010" =>ans<= a nand b;
when "011" =>ans<= a nor b;
when "100" =>ans<= a xor b;
when "101" =>ans<= a xnor b;
when "110" =>ans<= not a;
when "111" =>ans<= not b;
when others =>ans<= "00000000";
end case;
end if;
end process;
end behavioural;

116
 41130399_P.SAIVISWATEJA

SIMULATED OUTPUT:

VERILOG CODE:
module alu_214(clk,a,b,opr,ans);
input clk;
input [7:0]a,b;
input [2:0]opr;
output reg[7:0]ans;
always@(a,b,opr,clk)
begin
if(clk == 1)
begin
case(opr)
3'b000 : ans = a + b;
3'b001 : ans = a - b;
3'b010 : ans = (~a) + 1;
3'b011 : ans = (~b) + 1;
3'b100 : ans = a + 1;
3'b101 : ans = b + 1;
3'b110 : ans = a - 1;
3'b111 : ans = b - 1;
default : ans = 8'bZ;
endcase
end
else
begin
case(opr)
3'b000 : ans = a & b;
3'b001 : ans = a | b;

117
 41130399_P.SAIVISWATEJA

3'b010 : ans = ~(a & b);

3'b011 : ans = ~(a | b);
3'b100 : ans = a ^ b;
3'b101 : ans = ~(a ^ b);
3'b110 : ans = ~a;
3'b111 : ans = ~b;
default : ans = 8'bZ;
endcase
end
end
endmodule

SIMULATED OUTPUT:

RESULT:

The output of 8 – bit Arithmetic and Logic Unit is verified by stimulating and
synthesizing the VHDL/VERILOG code.

118
 41130399_P.SAIVISWATEJA

DATE:
04.04.20
EXPT. NO: BARREL SHIFTER
12 24

PAGE NO:

AIM:

To develop the source code for Barrel Shifter in VHDL/VERILOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.

Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

CIRCUIT SCHEMATIC:

119
 41130399_P.SAIVISWATEJA

TRANSITION TABLE:

Shi DATA
ft
S Dout( Dout( Dout( Dout(
3) 2) 1) 0)
0 Din Din(2) Din(1) Din(0)
(3)
1 Din(2) Din(1) Din(0) Din(3)
2 Din(1) Din(0) Din(3) Din(2)
3 Don(0 Din(3) Din(2) Din(1)
)

● TRUTH TABLE WITH SAMPLE DATA:

Shi DATA
ft
S 0 0 0 1
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 1 0 0 0

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity BARREL_SHIFTER_214 is
port(din: in std_logic_vector(3 downto 0);
s: in integer range 0 to 3;
dout: inout std_logic_vector(3 downto 0));
end BARREL_SHIFTER_214;
architecture behavioural of BARREL_SHIFTER_214 is
begin
process(din,s)
variable a:std_logic_vector(3 downto 0);
begin
a:=din;
for i in 1 to s loop
a:=a(2 downto 0)& a(3);

120
 41130399_P.SAIVISWATEJA
end loop;

121
 41130399_P.SAIVISWATEJA

dout<=a;
end process; end
behavioural;

SIMULATED OUTPUT:

VERILOG CODE:
module barrelshifter_214(data, count, dout);
input [3:0] data;
input [2:0] count;
output [3:0] dout;
reg[3:0]dout,x;
integer k;
always@(data,count)
begin
x=data;
for(k=0;k<count;k=k+1)
begin
x={x[2:0],x[3]};
end
dout=x;
end
endmodule

122
 41130399_P.SAIVISWATEJA

SIMULATED OUTPUT:

RESULT:

The output of Barrel Shifter is verified by stimulating and synthesizing the VHDL/
VERILOG code.

123
 41130399_P.SAIVISWATEJA

124