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DigitalLogic ComputerOrganization L24 VirtualMemory Handout

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16 views30 pages

DigitalLogic ComputerOrganization L24 VirtualMemory Handout

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 24: Virtual Memory
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

2
COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
3
CAN YOU DO IT?
What are the configurations of your computer?
- CPU:
▪ Name
▪ Clock frequency
▪ Number of cores, number of threads
▪ Size of L1, L2, L3 caches
- Memory:
▪ Type
▪ Size
- Secondary storage
▪ Type
▪ Size
- Operating system

4
MOTIVATION EXAMPLE 1

▪ Click Start > Control Panel > System.


▪ In the left panel, click Advanced system settings.
▪ Next, in System Properties box, select the Advanced tab,
and under Performance, click Settings
▪ In Performance Options box, click the Advanced tab, then
under Virtual Memory select Change.

5
MOTIVATION EXAMPLE 2

6
EXTENDING AND SHARING MAIN MEMORY?

❑What if one program needs more than the amount of


installed main memory (i.e., physical memory)?
❑How do multiple programs share the same main memory
address space (multiprogramming / multitasking) ?
7
EXTENDING MEMORY HIERARCHY

❑Main memory (MM) is managed similar to a cache


▪ Data are brought into MM as requested
▪ If MM is full, older data get swapped out to disk

8
SHARING MAIN MEMORY

❑How to enable multiple programs share the same


physical MM?
❑Requirements
▪ Transparency: a program should not know other programs
are sharing the same MM
▪ Protection: a program must not be able to corrupt other
programs
❑Solutions (Virtualizing MM)
▪ Each program operates in its own virtual address space
▪ The set of physical MM addresses for each program is dynamically
allocated and managed
9
VIRTUAL MEMORY

❑The hardware and software mechanisms that dynamically


manage the memory hierarchy
❑Extends memory hierarchy to incorporate large permanent
storage
▪ Hide physical size of MM from the program
▪ Moves large blocks (in unit of pages) between MM and permanent storage
as needed
❑ Allows multiple programs to share the main memory and
provides protection among programs
▪ Programs run in virtual address space
10
MULTIPROGRAMMING WITH VIRTUAL MEMORY

❑In this example,


each application
starts at virtual
address 0
❑Without virtual
memory, could
have only one
program in MM at
a time
11
VIRTUAL AND PHYSICAL ADDRESSES
❑Virtual addresses refer to the addresses used by the
programs
▪ When a program is compiled, the instructions and data addresses
are virtual
• Do not correspond to where they will be placed in MM
▪ With a N-bit virtual address, the size of the virtual address space is
2N bytes
❑Physical addresses refer to the real addresses used by
hardware to access the physical MM
▪ With a M-bit physical address, the size of the physical address space
is 2M bytes (typically, M < N)

12
PAGING

❑Virtual/physical address space is divided into equal sized


pages
▪ A page contains N bytes where N is a power of 2
• N = 4096(4 KB) is a typical size
▪ A whole page is read or written during data transfer between MM
and disk
▪ Each page in virtual memory space has a unique index called virtual
page number (VPN)
▪ Similarly, each page in physical memory space has a unique
physical page number (PPN)

13
VIEW OF VIRTUAL MEMORY WITH 32 BIT ADDRESS

14
VIRTUAL MEMORY AND PHYSICAL MM
❑ When requested, a page is brought into a physical MM location
❑ The correspondence (mapping) between virtual to physical
addresses is saved
▪ When the same virtual address is encountered, it is translated using
this saved mapping information

15
ADDRESS TRANSLATION

16
CAN YOU DO IT?
Question 1:
Page size is 16KB → how many bits is page offset?
(a) 12 (b) 13 (c) 14 (d) 15 (e) 16

Question 2:
Page size 4KB, Main Memory 512 MB
→ how many bits is PPN?
(a) 14 (b) 15 (c) 16 (d) 17 (e) 18

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ADDRESS TRANSLATION USING A PAGE TABLE

18
PAGE TABLE OPERATION (1)

19
PAGE TABLE OPERATION (2)

20
PAGE TABLE OPERATION (3)

21
PAGE TABLE OPERATION (4)

22
PAGE FAULTS AND PAGE REPLACEMENT

❑Miss penalty on a page fault is significant


▪ Up to ~100M cycles

❑Low miss (page fault) rates are essential


▪ Fully associative page placement (put anywhere in MM)
▪ LRU replacement of a page when MM is full

❑ The Operating System (OS) handles page placement

23
EXAMPLE: PAGE TABLE ACCESS

❑Given the following page table and virtual address stream (in
decimal), identify the potential page faults 128, 2048, 4096,
8193

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EXAMPLE: PAGE TABLE ACCESS
❑Given the following page table and virtual address stream (in
decimal), identify the potential page faults 128 (VPN=0), 2048
(VPN=0), 4096 (VPN=1), 8193 (VPN=2)

25
PAGE REPLACEMENT AND WRITE POLICY

❑Too expensive to do true LRU (100K-1M pages); Use LRU


approximation
▪ Each PTE has a Reference bit (ref)
▪ Reference bit is set when a page is accessed
▪ OS periodically clears all Reference bits
▪ OS chooses a page with a Reference bit of 0
❑ Write back policy is used (instead of write through)
▪ Dirty bit in PTE is set on a write to main memory
▪ Page with set Dirty bit is written to disk if replaced

26
FASTER ADDRESS TRANSLATION

❑Have to access the page table before an instruction can be


fetched and before data cache/memory can be accessed

❑Page table accesses have good locality


⇒ Cache the most recent PTEs within the CPU

27
TRANSLATION LOOKASIDE BUFFER (TLB)

❑Small cache of recently accessed PTE (typically 16-512


entries, fully associative)

28
TLB MISS SCENARIOS

❑TLB miss, page table hit


▪ Bring in the PTE information from page table to TLB
▪ Retry the access
▪ Usually completely performed by hardware
❑ TLB miss, page fault
▪ Bring in the page from disk (orchestrated by OS)
▪ Load the page table and TLB (orchestrated by OS)
▪ Retry the access
• Cache miss will definitely occur!

29
BEFORE NEXT CLASS

• H&H 6.7.2, 7.7


• Next time:
Exceptions
Inputs/Outputs

30

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