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DigitalLogic ComputerOrganization L18 PipelinedProcessorP2 Handout

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Phan Tuấn Khôi
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23 views36 pages

DigitalLogic ComputerOrganization L18 PipelinedProcessorP2 Handout

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 18: Pipelined Microprocessor (P2)
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

2
COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
3
PIPELINED MICROPROCESSOR

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REVIEW: DATA HAZARD PROBLEM

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REVIEW: COMPILER INSERTS NOPS (SOLUTION 1)

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EXAMPLE: DATA HAZARDS
❑ How many NOPs need to be inserted to avoid data
hazards in the following instruction sequence

SUB R4, R2, R3


SUB R4, R2, R3 NOP
ADD R1, R1, 1 NOP
ADDI R2, R4, 1 ADD R1, R1, 1
OR R5, R3, R4 ADDI R2, R4, 1
OR R5, R3, R4
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REVIEW: HW STALLS THE PIPELINE (SOLUTION 2)

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SOLUTION 3: HW FORWARDING (BYPASSING)

How to forward to the AND instruction?


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SOLUTION 3: HW FORWARDING (BYPASSING)

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PIPELINED MICROPROCESSOR W/O FORWARDING

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PIPELINED PROCESSOR WITH FORWARDING

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FORWARDING IN ACTION

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FORWARDING IN ACTION

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FORWARDING IN ACTION

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HW FORWARDING

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EXAMPLE: DATA HAZARDS W/O FORWARDING
❑ Identify all data hazards in the following instruction
sequences by circling each source register that is read
before the updated value is written back

ADD R1, R2, R3


OR R4, R1, R3
SUB R5, R2, R1
AND R6, R1, R2

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EXAMPLE: DATA HAZARDS W/ FORWARDING
❑ Identify all data hazards in the following instruction
sequences by circling each source register that is read
before the updated value is written back

ADD R1, R2, R3


OR R4, R1, R3
SUB R5, R2, R1
AND R6, R1, R2

Data hazards resolved by R-type to R-type forwarding


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ANOTHER EXAMPLE: DATA HAZARDS W/
FORWARDING
❑ Identify all data hazards in the following instruction
sequences by circling each source register that is read
before the updated value is written back

LW R1, 0(R2)
OR R4, R1, R3
SUB R5, R2, R1

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DATA HAZARDS CAUSED BY LOAD

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LOAD INSTRUCTIONS AND FORWARDING

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SOLUTION 2: HW STALLS THE PIPELINE

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SOLUTION 3: DELAY SLOTS

❑ A delay slot is a location in the program where the compiler


is required to insert an instruction between dependent
instructions
❑ The ISA defines the delay slots
❑ The compiler can fill delay slots with NOPs
❑ Even better: Move a non-dependent instruction from
elsewhere in the program into the delay slot
– Doing so must not change the function of the program

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EXAMPLE 1: FILLING THE LOAD DELAY SLOT

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EXAMPLE 2: FILLING THE LOAD DELAY SLOT ?

The ADDI instruction cannot be moved to the delay slot due to data dependence on AND
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THE PROBLEM WITH BRANCHES

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THE PROBLEM WITH BRANCHES

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CONTROL HAZARD

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REDUCING THE BRANCH DELAY

❑We already calculate the branch target in ID

❑Put dedicated hardware to also evaluate the condition


in ID

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EVALUATING BRANCH CONDITION IN ID STAGE

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BRANCH DELAY SLOT

❑ If the ISA defines a branch delay slot, the instruction


immediately following a branch is always executed after
the branch
❑ The compiler finds an instruction to put there, or puts in
a NOP
❑ The hardware must execute the instruction immediately
following the branch, regardless of whether the branch is
taken or not

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FILLING THE BRANCH DELAY SLOT WITH A NOP

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FILLING THE BRANCH DELAY SLOT

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BRANCH TARGET ADDRESS (PC+2+OFF)

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CAN YOU DO IT?

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BEFORE NEXT CLASS

• Next time:
More Pipelined Microprocessor

36

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