Scribd
Upload
10 views23 pages

DigitalLogic ComputerOrganization L5 CombinationalLogic Handout

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
10 views23 pages

DigitalLogic ComputerOrganization L5 CombinationalLogic Handout

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 23

DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 5: Combinational Building Blocks
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

2
COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
3
COMBINATIONAL BUILDING BLOCKS

❑ More complex functions built from basic gates


– Comparators
– Multiplexers
– Decoders
– Encoders
– Tri-state Buffers

4
EQUALITY COMPARATORS USING XOR

5
MULTIPLEXER (“MUX”)
❑ Connects one of n inputs to the output
– Select control signals pick one of the n sources
• log2n select bits
❑ Useful when multiple data sources need to be routed to a
single destination
– Often arises from resource sharing
– Example: select 1-of-n data inputs to an adder

6
2-TO-1 MUX
❑ Selects one of two inputs to appear at the output

❑ Y = S’•I0 + S•I1

7
4-TO-1 MUX
❑ Selects one of four inputs to appear at the output

❑ Y = S1’•S0’•I0 + S1’•S0•I1 + S1•S0’•I2 + S1•S0•I3

8
CASCADING MULTIPLEXERS
❑ Large multiplexers can be implemented by cascading
smaller ones

9
LOGIC FUNCTIONS USING MUXES
❑ Any function of n variables can be implemented with a
2n:1 multiplexer
❑ Logic Functions Using Muxes
– Input variables connected to select inputs
– Data inputs tied to 0 or 1 according to truth table

10
LOGIC FUNCTIONS USING MUXES
❑ Can use 2n-1:1 multiplexer and at most one inverter
– Connect n-1 input variables to select inputs
– Data inputs tied to 0, 1, nth variable, or inverted nth variable

11
DECODER
❑ Binary decoders
– n inputs, 2n outputs
– Each output corresponds to a unique input value
– At most one output asserted at a time

❑ Example: A 1-to-2 decoder

12
2-TO-4 DECODER

13
LOGIC FUNCTIONS USING DECODERS
❑ Any function of n variables can be implemented with a n: 2n
decoder and extra gates
– Connect variables to inputs
– Appropriate minterms summed using
extra gates to form the function

14
LOGIC FUNCTIONS USING DECODERS
❑ F1 = A’B’C’D’ + AB’CD’ + ABC’D’
❑ F2 = A’B’C’ + A’B’CD
❑ F3 = A+B+C+D = (A’B’C’D’)’

15
DECODER WITH ENABLE

16
DECODER WITH ENABLE

17
ENCODERS
❑ Opposite of decoders
❑ Binary encoders: 2n inputs and n outputs

18
4-TO-2 ENCODER
❑ Exactly one input is asserted at any given time

19
PRIORITY ENCODER
❑ Highest numbered inputs have priority when multiple
inputs are asserted at the same time
❑ Example: 4-to-2 priority encoder

20
PRIORITY ENCODER
❑ Example: Microprocessor Interrupts
▪ In order for devices to get service, they interrupt
the microprocessor
▪ Most important requests are given priority

21
TRI-STATE BUFFERS
❑ Bus with tristate buffers

D3 D2 D1 D0 S1 S0
E Y

Decoder
0 Z
Z: high-impedant
1 D

22
BEFORE NEXT CLASS

• Textbook: 3.1, 3.2

23

You might also like