ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028

An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

USN
II INTERNAL TEST ANSWER KEY
Subject : Verilog HDL Sections : A&B
Subject code : 18EC56 Semester : V
Date : 20/12/2021 Duration : 1 Hr 30 Min
Time : 2.00 pm – 3.30 pm Max Marks : 50

Answer any 5 full questions.

Marks
Q.No Question
Allocated

1. Develop a 2-to-1 multiplexer using bufif0 and bufif1 gates. The delay 10
specifications for these gates as follows:

Delay Min Typ Max

Rise 1 2 3

Fall 3 4 5

Turn-off 5 6 7

Write gate-level description and stimulus in Verilog.

Ans:
Verilog Code:
module mux2_1(out,in1,in0,s);
output out;

input in1,in0,s;
bufif1 #(1:3:5,2:4:6,3:5:7) b2 (out, in1, s);
bufif0 #(1:3:5,2:4:6,3:5:7) b1 (out, in0, s);
endmodule (5 Marks)

Stimulus code:
module tes;
reg in1,in0,s;
wire out;
mux2_1 U1 (out,in1,in0,s);
initial
 ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

begin
in1=1'b0;
in0=1'b1;
s=1'b0;
#10 s=1'b1;
#10 s=1'b0;
end
initial
begin
$display("\t time \t in1 \t in0 \t s \t out ");
$monitor("\t %4d \t %3d \t %3d \t %2d \t %3d ",$time,in1, in0, s, out);
end
endmodule (5 Marks)

2. What would be the output of the following a = 4’b1110, b = 4’b1001 10

a) a & b b) a&&b c) |a d) a>>>2

e) y={2{ a },b[0] } f) a <= b g) a%b

h) a/b i) a?1:0 j) a = = b

Ans:

a) 1000 b)1 c) 1 d) 1111 e) y = 9’b111011101

f) 0 g) 53 or 4’b0101 h)1 i) 1 j) 0
(Each carries 1 Mark)

3. Explain Procedural assignments used in behavioral Modeling with relevant

examples.

Ans:

Two types of procedural assignment statements:

1. blocking
2. nonblocking
Blocking Assignments:
Blocking assignment statements are executed in the order they are specified in a
sequential block. A blocking assignment will not block execution of statements that
follow in a parallel block. The = operator is used to specify blocking assignments.
(1 Mark)
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
 ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

begin
x = 0; y = 1; z = 1;
count = 0;
reg_a = 16'b0; reg_b = reg_a;
#15 reg_a[2] = 1'b1;
#10 reg_b[15:13] = {x, y, z} ;
count = count + 1;
end ( 3 Marks)
Output:
 All statements x = 0 through reg_b = reg_a are executed at time 0
 Statement reg_a[2] = 1 at time = 15
 Statement reg_b[15:13] = {x, y, z} at time = 25
 Statement count = count + 1 at time = 25
 Since there is a delay of 15 and 10 in the preceding statements, count = count
+ 1 will be executed at time = 25 units ( 1 Mark)
Nonblocking Assignments:
Nonblocking assignments allow scheduling of assignments without blocking
execution of the statements that follow in a sequential block. A <= operator is used
to specify nonblocking assignments. ( 1 Mark)
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x = 0; y = 1; z = 1;
count = 0;
reg_a = 16'b0; reg_b = reg_a;
reg_a[2] <= #15 1'b1;
reg_b[15:13] <= #10 {x, y, z};
count <= count + 1;
end ( 3 Marks)
Output:
 The statements x = 0 through reg_b = reg_a are executed sequentially at time 0.
 Then the three nonblocking assignments are processed at the same simulation
time.
1. reg_a[2] = 1 is scheduled to execute after 15 units (i.e., time = 15)
2. reg_b[15:13] = {x, y, z} is scheduled to execute after 10 time units (i.e.,
time = 10)
3. count = count + 1 is scheduled to be executed without any delay (i.e., time
= 0) (1 Mark)
 ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

4. 6+4
a. Design a clock with time period = 50 and a duty cycle of 75% by using the
always and initial statements. The value of clock at time = 0 should be
initialized to 0. Finish the simulation by 200 time units. Draw the waveform
of generated clock signal.
Ans:
module clock;
reg clock;
initial
clock =1'b0;
always
begin
#13 clock= ~clock;
#37 clock= ~clock;
# 200 finish;
end
endmodule (4 Marks)
Output:

(2 Marks)

b. Using the wait statement, design a level-sensitive latch that takes clock and
d as inputs and q as output. q = d whenever clock = 1.
Ans:
module d_latch(q,clk,d);
output reg q;
input clk, d;
always
wait (clk)q= d;
endmodule (4 Marks)

5. A full subtractor has three 1-bit inputs x, y, and z (previous borrow) and two 1- 10
bit outputs D (difference) and B (borrow). The logic equations for D and B are
as follows:

D = x'.y'.z + x'.y.z' + x.y'.z' + x.y.z

B = x'.y + x'.z + y.z
 ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

Write the Verilog description using dataflow modeling. Instantiate the

subtractor module inside a stimulus block and test all possible combinations of
inputs x, y, z.
Ans:
Design block code:
module fs(D,B,x,y,z);
output D,B;
input x,y,z;
assign D= (~x &~y&z) | (~x &y&~z) | (x&~y&~z) | (x&y&z);
assign B= (~x&y) | (~x&z)| (y&z);
endmodule (5 Marks)

Stimulus block code:

module fs_tb();
wire D,B;
reg x,y,z;
fs u0(D,B, x,y,z);
initial
begin
x=1’b0; y=1’b0;z=1’b0;
# 5 z=1’b1;
# 5 y=1’b1; z=1’b0;
# 5 z=1’b1;
# 5 x=1’b1;y=1’b0; z=1’b0;
# 5 z=1’b1;
# 5 y=1’b1;
# 5 z=1’b0;
# 5 z=1’b1;
# 100 finish;
end
endmodule (5 Marks)

6. a) List the characteristics of continuous assignments with an example. 5+5

Ans:
1. The left hand side of an assignment must always be a scalar or vector net or a
concatenation of scalar and vector nets. It cannot be a scalar or vector
register.
2. Continuous assignments are always active. The assignment expression is
evaluated as soon as one of the right-hand-side operands changes and the
value is assigned to the left-hand-side net.
3. The operands on the right-hand side can be registers or nets or function calls.
Registers or nets can be scalars or vectors.
4. Delay values can be specified for assignments in terms of time units. Delay
 ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

values are used to control the time when a net is assigned the evaluated value.
( 1 Mark each)
Example:
assign out=i1&i2;// out is net: i1 and i2 are nets (1 Mark)

b) Design and write a Verilog code for 4-to-1 mux using Conditional operator
Ans:

s1 s0 out

0 0 i0

0 1 i1

1 0 i2

1 1 i3

(2 Marks)
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule (3 Marks)