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ISSUE: June 2018

The Engineer’s Guide To EMI In DC-DC Converters (Part 5): Mitigation Techniques
Using Integrated FET Designs
by Timothy Hegarty, Texas Instruments, Phoenix, Ariz.

Parts 1 through 4 of this article series offer a detailed perspective on conducted and radiated emissions from
switching power regulators, including a description of the mechanisms for noise generation, measurement
requirements, frequency ranges, applicable test limits, propagation modes and parasitic effects.[1,2,3,4] Based on
that theoretical foundation, here in part 5 I will present practical circuit techniques to mitigate electromagnetic
interference (EMI).

In general, the circuit schematic and printed circuit board (PCB) design are pivotal to achieving excellent EMI
performance. Part 3 underscored the imperative to minimize “power loop” parasitic inductance through careful
component selection and PCB layout.[3] The power converter integrated circuit (IC) has an outsized impact here,
both in terms of its package technology and the EMI-specific features it offers. As outlined in part 2, differential-
mode (DM) filtering is mandatory to sufficiently reduce the input ripple current amplitude to the required level
for EMI regulatory compliance.[2] Meanwhile, common-mode (CM) filtering is generally required to curtail
emissions above approximately 10 MHz. Shielding also offers excellent results at high frequencies.

This article delves into these aspects, offering practical examples and guidelines to mitigate EMI, specifically for
converter solutions with integrated power MOSFETs and controller. In general, a converter should pass
conducted EMI by a reasonable margin to have any chance of meeting radiated limits. Fortunately, most steps
taken to abate conducted emissions are correspondingly effective in mitigating radiated EMI.[5]

Understanding The EMI Challenge

The major source of EMI in dc-dc converters is the fast switching of voltages and currents. The EMI related to a
converter’s discontinuous input or output current is relatively easy to deal with, but a greater concern relates to
the harmonic content of the switching waveforms, in terms of ringing as well as the rise and fall times (dv/dt
and di/dt).[3]

Buck converter
VIN LO VOUT
Q1 SW
TRing1

CIN Q2 CO
Control Resonant frequency
1
Voltage f Ring1  =160MHz
overshoot 2 LLOOP COSS2

GND GND

Equivalent RLC circuit Equivalent RLC circuit VIN

after Q1 turns ON after Q1 turns OFF
LLOOP LLOOP Damping
RLOOP 1
  f Ring 2 
2 LLOOP 2 LLOOP COSS1
RLOOP Q1 on Q1 off COSS1
RLOOP
High Z High Z
VSW
VIN VSW
Voltage
VIN undershoot
Q2 off COSS2 Q2 on

Fig. 1. Switch-node voltage waveform and equivalent circuits during MOSFET turn-on and turn-off
switching transitions for a synchronous buck converter.

Fig. 1 shows the switch-(SW) voltage waveform of a noisy synchronous buck converter. The ringing frequency
ranges from 50 MHz to 200 MHz depending on parasitics. Such high-frequency content can propagate by near-
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field coupling[4] to the input supply lines, to nearby components or to the output bus (for example, a USB
cable). Body-diode reverse recovery presents a similar issue, exacerbating the ringing voltage as the recovery
current flows in the parasitic loop inductance.

The schematic in Fig. 2 identifies the two critical loops for a buck converter circuit. Minimizing the power-loop
area is essential because of its proportionality to parasitic inductance and related H-field propagation. The main
design goal is to push the resonant frequency of the parasitic LC tank as high as possible by curtailing the
parasitic inductance. This decreases the total stored reactive energy and lowers the switch-voltage peak
overshoot.

Reduce loop area with high di/dt switching current

High-side
gate driver Reduce loop area with high di/dt gate drive current
RBOOT Shorten traces with high slew rate voltage (dv/dt)

CBOOT
VIN Q1 LO VOUT
SW

CIN Q2 CSNUB

CO
RSNUB

Snubber circuit
(optional)

GND GND
Fig. 2. Simplified synchronous buck converter schematic with highlighting of the loops and traces
critical to generation of EMI.

In the boot capacitor loop shown in Fig. 2, an optional series boot resistor, designated RBOOT, controls the turn-
on speed of the high-side MOSFET. The boot resistor changes the drive-current transient rate and thus reduces
the switch voltage and current slew rates during MOSFET turn-on. Another option is a snubber circuit from SW
to GND. Similarly, this snubber should also occupy a minimal loop area based on its transient current spike at
each switching transition.

Of course, snubbers and gate resistors increase switching power loss, leading to a tradeoff between efficiency
and EMI. Other techniques are required to solve the EMI challenge if efficiency and thermal performance are
also important.

Converter PCB Layout

Items 1 through 5 summarize the essential guidelines for PCB layout and component placement for a reduced
dc-dc converter EMI signature. I’ll provide a PCB layout case study for an EMI-optimized buck converter later in
this article.

1. Routing and component placement.

 Route all power-stage components on the top side of the PCB. Avoid locating the inductor on the bottom
side, where it can radiate to the reference plane of the EMI test setup.
 Place VCC, VDD and/or BIAS bypass capacitors close to their respective pins. Ensure that the AGND pin
“sees” the CVCC and CBIAS capacitors first before connecting it to GND.
 Connect the bootstrap capacitor close to the BOOT and SW pins. Shield the CBOOT capacitor and switch
node with adjacent ground copper to reduce CM noise.

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2. Ground plane design.

 Position a layer 2 ground plane in the PCB layer stackup as close as possible to the top layer. This
provides H-field cancellation, parasitic inductance reduction and noise shielding.
 Use low z-axis spacing between the top layer and second layer for optimal image plane effectiveness.
Define a 6-mil intralayer spacing in the PCB stackup specification.

3. Input and output capacitors.

 Place CIN to minimize the loop area formed by CIN connections to the VIN and PGND pins.
 Ground return paths for both CIN and COUT should consist of localized top-side planes. Connect dc
current routes using multiple external or internal ground planes.
 Use 0402 or 0603 case size ceramic input capacitors near the VIN and PGND pins to minimize parasitic
loop inductance.

4. Inductor and switch-node layout.

 Locate the inductor close to the SW pin of the IC. Minimize the switch-node copper surface area to
prevent excessive capacitive coupling.
 Confine switch-node noise using adjacent ground guarding and via shielding.
 Check the inductor dot position to ensure that the end of the inductor winding tied to SW is on the
bottom and inside of the winding geometry and shielded by the outer turns of the winding connected to
VOUT.
 Use an e-field-shielded inductor if possible. Connect the shield terminals to the PCB ground plane.
 Select an inductor with terminations underneath the package. Avoid large sidewall terminations that can
act as radiating antenna.

5. EMI management.
 Route the EMI filter components away from the switch node. Place the EMI filter on the opposite side of
the board from the converter if it cannot be sufficiently separated from the power stage.
 Place cutouts on all layers below the EMI filter to prevent parasitic capacitive paths impacting the filter
attenuation characteristic.
 Place a resistor (preferably less than 10 Ω) in series with CBOOT, if needed, to slow down a buck
converter’s high-side MOSFET turn-on, reducing the switch-node voltage slew rate, overshoot and
ringing.
 If a switch-node RC snubber is required, connect the smallest footprint component to SW (usually the
capacitor).
 Use a four-layer PCB with inner ground planes to achieve much improved performance relative to a two-
layer design. Avoid disruption of the high-frequency current paths near the IC.

EMI Input Filter

Fig. 3 shows a typical multistage EMI input filter. Low- and high-frequency sections provide DM noise
attenuation, and an optional -stage with a CM choke delivers CM attenuation. An electrolytic capacitor,
designated CBULK, has an inherent equivalent series resistance (ESR) that sets the required damping to reduce
the effective Q-factor at the converter input and maintain input filter stability.[6]

The self-resonant frequency (SRF) of the DM inductor limits the achievable high-frequency DM attenuation of
the first filter stage. A second filter stage is often essential to provide supplemental DM attenuation at a high
frequency using a ferrite bead, with impedance typically rated at 100 MHz. Ceramic capacitors, designated CF1
and CF2, shunt noise to ground.

In general, the DM filter inductance is sized to attenuate the fundamental- and low-frequency harmonics. Use
the minimum inductance possible to meet the low-frequency filtering demands, as a higher inductance with
more turns increases the inductor’s equivalent parallel capacitance (EPC) and thus the SRF, compromising its
performance at high frequencies.
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Multi-stage EMI filter

Common-mode filter High-frequency Low-frequency

(optional) differential-mode filter differential-mode filter VIN
IN+
LFB LDM
LCM
CIN1 CHF1 CHF2 CF1 CF2 CBULK CIN
DC/DC
Converter

IN–

Fig. 3. Three-stage EMI input filter with DM and CM stages.

The CM choke, designated LCM, offers a high impedance to CM currents, and its leakage inductance also
provides DM attenuation. Nevertheless, this component is undesirable in certain applications where the ground
connection must remain intact, making quieter converter designs that obviate the need for a CM choke more
favorable.

To demonstrate the effectiveness of a CM choke, Fig. 4 illustrates the Texas Instruments LM53603, a 36-V, 3-A
dc-dc converter solution using a two-layer PCB.[7] The power stage is located on the top layer and the EMI input
filter is on the bottom. As the layouts in Fig. 4 show, via stitching the ground plane copper around the filter
provides a shielding effect. Also, inserting copper plane cutouts on all layers underneath the filter stage avoids
any parasitic capacitance that may form between VIN and GND traces, providing a path for noise currents to
bypass the CM choke and compromising the filter’s impedance characteristic.

Fig. 5 presents CISPR 25 conducted emissions measurements from 150 kHz to 108 MHz for the converter
design in Fig. 4. The results are provided with and without the CM choke. Using a Rohde & Schwarz spectrum
analyzer, peak and average detector scans are denoted in yellow and blue, respectively. The limit lines in red
are the Class 5 peak and average limits (peak limits are generally 20 dB higher than the average limits).

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Power stage and EMI input filter

PCB layout implementation

Fig. 4. Dc-dc converter schematic and PCB layout implementation.

2MHz
switching
frequency

RBW 10kHz RBW 100kHz

(a)

RBW 10kHz RBW 100kHz

(b)
Fig. 5. CISPR 25 conducted EMI measurements with CM choke (a) and without CM choke (b).
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Metal Case Shielding

Another very effective way to optimize high-frequency EMI performance is to add a metal case shield[5] to block
the radiated electric field. The case is typically made of aluminum and implemented as a frame (open-top) or
closed-top design. The shield covers all power-stage components except the EMI filter and is connected to
ground on the PCB, essentially forming a Faraday cage with the PCB ground plane.

The result is a dramatic reduction in radiated noise coupling from the switching cell to the EMI filter or onto long
input wire connections (which also act as an antenna). Of course, additional component and assembly costs are
incurred, and thermal management and testing are more difficult. The case of an aluminum can electrolytic
capacitor may also provide e-field shielding and can be tactically positioned on the board for this purpose.

DC-DC Converter Case Study

Fig. 6 is a schematic of a 60-V, 1.5-A monolithically integrated synchronous buck converter circuit[8] with
several features in place for optimal EMI performance. The schematic also shows a two-stage EMI input filter
stage designed to meet EMI specifications for automotive or noise-sensitive industrial applications. To help
translate to an optimized PCB layout, the schematic highlights the high-current traces (VIN, PGND, SW
connections), noise-sensitive nets (FB) and high dv/dt circuit nodes (SW, BOOT).

VOUT = 5 V
IOUT = 1.5 A
High-current trace
Noise-sensitive trace
CO1 CO2
High dv/dt node 47 mF LF 47 mF
10 mH

U1
12

SW
1 PGND PGND 11

CIN4 CIN3 CIN1 CIN2

2.2 mF 47 nF 47 nF 2.2 mF
2 VIN VIN 10
EMI filter
LMR36015
VIN = LFB LDM
3 SW EN 9
3.8V to 60V 600 W @ 100 MHz 400 nH
CBOOT
0.1 mF
4 BOOT PGD 8
CF1 CF2 CD
2 ´ 2.2 mF 3 ´ 2.2 mF 68 mF VCC AGND FB
+ 1 ´ 47 nF + 1 ´ 47 nF 5 6 7

CVCC
VOUT
1 mF
RFBB RFBT
24.9 kW 100 kW

Fig. 6. Dc-dc converter with EMI-optimized package and pinout. Included is a two-stage
EMI input filter.

Pinout Design
The converter IC in Fig. 6 has the benefit of a symmetrical and balanced pin arrangement for VIN and PGND. It
uses two input loops in parallel that result in effectively half the parasitic loop inductance. These loops are
labeled IN1 and IN2 in the PCB layout shown in Fig. 7.

Two capacitors with a small 0402 or 0603 case size, designated as C IN1 and CIN3 in Fig. 6, are placed as close as
possible to the IC to configure the minimum input loop area. The circulating currents create opposing magnetic
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moments that result in H-field cancellation and hence lower effective inductance. To further reduce parasitic
inductance, a continuous ground plane for return current underneath the IN1 and IN2 loops on layer 2 of the
PCB (immediately below the top layer power circuit) supports a field self-cancellation effect.

Using two ceramic output caps, CO1 and CO2, one on each side of the inductor, similarly optimizes the output
current loops. Having two parallel ground return paths from the output splits the return current in two, helping
to mitigate the “ground bounce” effect.

Butterfly arrangement of
input and output capacitors Shielded inductor with terminations
minimizes loop areas underneath the package

Minimum area SW node trace

connection to the inductor
0603 input capacitors (CIN1
and CIN3) located close to the
VIN and PGND pins
IN1 IN2
BOOT capacitor in 0402 case
size located close to the BOOT
and SW pins

VCC capacitor located close to Feedback resistors located

the VCC and AGND pins away from the SW node
Fig. 7. Power-stage layout routed only on the top layer of the PCB.

The SW pin is located at the center of the IC such that the radiated e-field is shielded by adjacent VIN and
PGND pins on both sides of the IC. Ground plane copper shields the polygon pour connecting the IC’s SW pin to
the inductor terminal. The single-layer SW and BOOT layout implies that vias with high dv/dt do not appear on
the bottom side of the PCB. This avoids e-field coupling to the reference ground plane during the EMI test.

Package Design
In tandem with optimized pinout, power converter IC package design is a key attribute in the quest to improve
EMI signature. For example, the HotRod package technology from TI uses a flipped-chip-on-leadframe (FCOL)
technique that eliminates power device wire bonds that typically cause high package parasitic inductance.

Fig. 8 shows that the IC is flipped upside down and copper posts (otherwise known as bumps or pillars) on the
IC are soldered directly to the lead frame. This construction method enables high density and a low profile, as
each pin is attached directly to the lead frame. Most important from an EMI standpoint, the HotRod package
lowers package parasitic inductance versus traditional wire-bond packages.[9]

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Traditional wire-bond QFN package HotRod FCOL package

Copper/gold/aluminum bond wires connect IC to pins Die is flipped and placed directly onto the leadframe
Þ high package parasitic resistance and inductance Þ low package parasitic resistance and inductance
Þ higher density, smaller package
Mold compound
Mold compound

Cu/Au/Al
DC/DC Converter IC (Silicon Die)
DC/DC Converter IC (Silicon Die) Copper post
bond wire
Die Attach Solder (Sn-Ag)
Pin Exposed Thermal Pad Pin Leadframe Leadframe
Solder
PCB PCB Solder

(a) (b)

Fig. 8. Comparing the package construction of a conventional wire-bond QFN (a) with
that of TI’s HotRod FCOL (b).

Not only does the HotRod package result in much lower ringing at the switching commutations (50-MHz to 200-
MHz frequency range), it also reduces both conduction and switching losses. Fig. 9 shows the concomitant
improvement in switch-node voltage ringing. Fig. 10 shows the conducted emissions measured from 150 kHz to
108 MHz for the converter in Fig. 6. The results are in compliance with CISPR 25 Class 5 requirements.[10]

Wire-bond package HotRod package

(a) (b)
Fig. 9. Switch-node voltage waveform with a traditional wire-bond converter (a) versus the same
waveform with a HotRod FCOL converter (b).

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410kHz
switching
frequency

(a) (b)
Fig. 10. CISPR 25 conducted emission results, 150 kHz to 30 MHz (a) and 30 MHz to 108 MHz
(b).

Summary
In this article I discussed EMI abatement techniques for dc-dc regulator circuits that use a power converter IC.
PCB layout steps to reduce EMI are to minimize the current “hot loop” area in the layout, avoid disruption of the
current path, use a four-layer PCB with inner ground planes for shielding (yielding much better performance
than a two-layer PCB), and route minimal switch-node copper area to reduce e-field radiated coupling.

Converter package type is an important selection criterion, as new device generations show significantly
improved performance in terms of switch-node ringing and pinout design for optimal capacitor placement. From
an input filtering standpoint, low-frequency noise (generally less than 10 MHz) is relatively straightforward to
suppress with a conventional LC filter stage, whereas high-frequency noise (above 10 MHz) typically needs an
additional CM choke and/or a ferrite bead filter stage. A metal case shield soldered to the PCB ground plane also
effectively mitigates high-frequency emissions.

In the next installment of this series, I’ll explore EMI abatement techniques for dc-dc regulator circuits using a
controller driving discrete power MOSFETs, which is more challenging from an EMI perspective.

References

1. “The Engineer’s Guide to EMI in DC-DC Converters (Part 1): Standards Requirements and Measurement
Techniques,” by Timothy Hegarty, How2Power Today, December 2017 issue.
2. “The Engineer’s Guide to EMI in DC-DC Converters (Part 2): Noise Propagation and Filtering,” by
Timothy Hegarty, How2Power Today, January 2018 issue.
3. “The Engineer’s Guide to EMI in DC-DC Converters (Part 3): Understanding Power Stage Parasitics,” by
Timothy Hegarty, How2Power Today, March 2018 issue.
4. “The Engineer’s Guide to EMI in DC-DC Converters (Part 4): Radiated Emissions,” by Timothy Hegarty,
How2Power Today, April 2018 issue.
5. “There are more ways than you think to reduce conducted EMI,” by Vental Mao, TI E2E Community
Behind the Wheel blog, April 17, 2018.
6. “Input filter design for switching power supplies,” by Michele Sclocchi, Texas Instruments application
report SNVA538, 2010.
7. “EMI Optimized 2-Layer 15W Power Supply for Automotive with CISPR 25 Class 5 Compliance,” TI
Designs reference design.
8. LMR36015 60-V, 1.5-A synchronous stepdown converter in HotRod package.

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9. “Reduce EMI and shrink solution size with HotRod packaging,” by Frank De Stasi, Texas Instruments
training video, March 7, 2018.
10. “Eliminate High-Frequency Switch-Node Ringing and Pass CISPR 25 Class 5 without Metallic Shielding or
a Common-Mode Choke,” by Katelyn Wiggenhorn, Texas Instruments EMI training webinar, Sept. 11,
2017.

About The Author

Timothy Hegarty is an applications engineer for Power Products
Solutions at Texas Instruments. With 20 years of power
management engineering experience, he has written numerous
conference papers, articles, seminars, white papers, application
notes and blogs.

Tim’s current focus is on enabling technologies for high-frequency,

low-EMI, isolated and nonisolated regulators with wide input voltage
range, targeting industrial, communications and automotive
applications in particular. He is a senior member of the IEEE and a
member of the IEEE Power Electronics, Industrial Applications and
EMC Societies.

For more information on EMI, see How2Power’s Power Supply EMI Anthology. Also see the How2Power’s Design
Guide, locate the Design Area category and select “EMI and EMC”.

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