Unit-4 Logic Families

Logic Families: The basic logic gates discussed above were designed using discrete components like diodes,
transistors and resistances etc. In the recent past, it has been possible to fabricate many hundreds of thousands of
active and passive components on a small silicon chip. Such fabricated devices are known as integrated circuits
(ICs). The Integrated circuits are broadly classified in two categories namely Linear or analog ICs and digital ICs.
The analog ICs mainly contain amplifiers, operational amplifiers, audio and power amplifiers etc. However, the
digital ICs contain logic gates etc. The variety of logic gates are fabricated in digital ICs using various
technologies. The digital ICs may further be classified into following categories depending upon their level of
integration:
(i) Small Scale Integrated Circuits (SSI): Twelve gates per IC are fabricated in SSI and total number of
components per chip is less than 100.
(ii) Medium Scale Integrated Circuits (MSI): These ICs contain 12 to 100 gates per IC and total number of
components per IC is 100 to 1000.
(iii) Large Scale Integrated Circuits (LSI): The large scale integrated circuits contain 100 to 1000 gates per IC
and number of components is 1000 to 10000 per IC.
(iv) Very Large Scale Integrated Circuits (LSI): These ICs contain more than 1000 and less than 10000 gates
per IC and total number of components per chip is 10000 to 100000.
(v) Ultra Large Scale Integrated Circuits (LSI): More than 10000 gates per IC are fabricated and total
components are more than 100000 per chip.
The logic families are classified into two categories depending upon the technologies used for fabrication.
1. Bipolar Logic Families
2. Uni-polar Logic Families
The bipolar logic families are mainly of two types.
a. Saturated Logic Circuits: In which the transistors are driven into saturation.
b. Non-Saturated Logic: In non-saturated transistor logic circuits, the transistors are avoided to go into
saturation.
The Saturated logic circuits may further be classified into the following categories:
1. Resistor – Transistor Logic (RTL)
2. Direct Coupled Transistor Logic (DCTL)
3. Integrated Injection Logic (IIL or I2L)
4. Diode – Transistor Logic (DTL)
5. High Threshold Logic (HTL)
6. Transistor – Transistor Logic (TTL) The non-saturated logic families are:
1. Schottky Transistor – Transistor Logic (STTL) 2. Emitter Coupled Logic (ECL)
The Uni-polar logic families contains MOS FETs, these are:
1. NMOS or PMOS Logic
2. CMOS (Complementary MOS) logic
 Before discussing the details of logic families mentioned above, it is necessary to explain the following
characteristics related to them. These parameters will help in comparing the performances of the logic families.
(i) Fan – in: The maximum number of inputs that can be applied to a logic gate is known as Fan – in. Thus a
three input AND has fan – in as three.
(ii) Fan – out: The fan –out of logic gate is the number of gates that can be driven by it. Thus, if a fan-out of a
typical gate is 10, then it implies that this gate can drive 10 such gates.
(iii) Propagation Delay Time: The propagation delay time of a gate is defined as the time interval between the
application of the inputs to a gate and appearance of the signal at the output of the gate. In other words it is defined
as the time interval between a change in input state and the resulting change in output state of the gate. This delay
is a very small quantity; it is of the order of few nano second say 20 nsec (20x10-9 sec) or 50 nsec (50x10-9 sec).
The propagation delay of the gate also specifies the speed of the logic gate. The delay time is measured between
50% voltage levels of input and output waveforms. Figure 7.4 shows the input and output waveforms of an
inverter. If tPHL is the delay time when the output goes from low state (logic 0) to high state (logic 1) and t PLH is
the delay time when the output goes from high state (logic 1) to low state (logic 0), the propagation delay time of
the gate tpd expressed as the average of the two delays as:

Fig. 7.4
(iv) Power Dissipation: It is defined as the amount of power that can be dissipated in an IC. It is calculated as
the product of the d.c. voltage applied to an IC and the current drawn from the d.c. source. It is always desirable
to have low power dissipation per gate. The normal working power per gate is required from few micro-watts to
few milli-watts. The product of speed and power dissipation per gate is known as the figure of merit of the logic
family. A low value of this product is desirable.
(v) Operating Temperature: The temperature range in which an IC functions properly is known as the
operating temperature of the gate. It is specified by the manufacturer. The acceptable temperature range of the
ICs is from 0 to +70 0C for commercial applications and this range is from – 55 0C to 125 0C for military purposes.
(vi) Noise Margin: Spurious signals called noise are sometimes generated in the connecting leads of the logic
circuits due to the stray electric and magnetic fields in the surroundings. This results the unpredictable operation
of the logic circuit. The noise margin is sometimes called Noise- immunity. It is defined as the difference between
the maximum permitted low input and the maximum guaranteed low output, and that
between the minimum permitted high input and the minimum guaranteed high output. The idea of noise margin
is illustrated in figure 7.5.

Fig. 7.5
Figure 7.5 shows that VOH(min) is the minimum high voltage for logic 1 and VOL(max) is the maximum
low voltage for logic 0. The output should not occur in the disallowed range. Similarly, VIH(min) is the minimum
high input voltage and VIL(max) is the maximum low input voltage and the voltage level between VIH(min) and
VIL(max) is the indeterminate range and this voltage range should not be applied to the inputs of the logic gate.
As per definition of the noise margin, the noise margin for high state (VNH) and the noise margin for low state
(VNL) are given by:
VNH = VOH(min) – VIH(min)
VNL = VOL(max) – VIL(max)
The large noise margin is always desirable.

7.10 Transistor – Transistor Logic (TTL): The TTL is the most popular amongst all logic families and
is widely used IC technology.. It is the modified form of DTL. The propagation delay time is reduced in TTL by
using multi-emitter transistor in place of diodes. Figure 7.11 (a) shows the schematic diagram of a basic TTL
positive logic NAND gate. It consists of a multi-emitter transistor T1. A two emitter transistor is equivalent to two
transistors with common base and common collector as shown in figure 7.11 (b).
The operation of TTL NAND gate may be explained as follows:
When either of two inputs A or both the inputs are at logic 0, emitter base junction of the multi-emitter
transistor will be in forward bias and base current is supplied by the resistor R 1. The transistor T1 saturates and
the voltage at the point will be equal to VCE,Sat of the transistor (≈ 0.2 V). The transistor T2 will be in cutoff and
output voltage will be high (logic 1).
 F
Fig. 7.11 (a) Fig. 7.11 (b)

When both the inputs are at logic 1 (+5 V), the emitter base junctions of transistor T 1 will be reverse biased and
current will flow, through R1 and through the forward biased base collector junction of transistor T1 into the base
of transistor T2. In this mode the transistor is said to be operated in the inverted mode, as the collector of transistor
T1 operates as emitter and the emitter as collector. The voltage at the point P will be sufficient to drive the transistor
T2 into saturation, the output voltage will therefore, be equal to VCE,Sat (≈ 0.2V) or logic 0.
The propagation delay time of this gate is smaller than that of DTL NAND gate, since when the transistor T 2
goes into cutoff region from saturation region, the transistor T1 saturates and provides a low impedance path to
ground. Thus the stored base charge of the transistor T2 is quickly removed thereby reducing the propagation
delay time.
The output resistance of the basic TTL circuit (fig. 7.11 a) is low when the transistor T2 saturates or output is low
(logic 0). However, the output resistance of this circuit is almost equal to the resistance R, when the transistor is
in cutoff or output is high (logic 1). This will restrict the fan out of the gate. The reduction in resistor R would
increase the power dissipation in R and in the gate. Also the reduction in the value of R would difficult to saturate
the transistor T2. To overcome this difficulty, TTL gate with totem pole arrangement is used.

7.10.1 TTL NAND Gate with Totem-pole Output: Figure 7.12 shows the standard form of a TTL circuit with
input NAND gate. The circuit works as follows:

Fig. 7.12
 When either the inputs or both the inputs are low (logic 0), the transistor T 2 goes into cutoff. The transistor T4
will also be in cutoff, as the voltage drop across the resistor R 3 is nearly zero. Now the transistor T3 conducts and
works as emitter follower. The output voltage available at the emitter of this transistor will be equal to the collector
voltage of the transistor T2, which is high (logic1). The emitter follower, however, provides a low output resistance
to the input of the driven gate.
When both the inputs are high (or at logic 1), transistor T2 conducts and acts as an emitter follower. The potential
across R3 will be sufficient to drive the transistor T4 into saturation. Because the transistor T4 saturates, the output
voltage will, therefore, be equal to VCE,Sat (≈ 0.2V) or logic 0. Since this output is taken at the collector of the
transistor T4, which is in saturation, so it provides the low output impedance. The diode D prevents the transistor
T3 from being conducting when the transistor T4 saturates. The potential across the emitter base junction of the
transistor T4 is approximately 0.8 V (VBE,Sat) and collector emitter voltage of T2 is 0.2 V (VCE,Sat). This means a
total of 1.0 V is applied to the base of transistor T3. In the absence of the diode D, this voltage would be sufficient
for the conduction of the transistor T3. The diode D, however, reduces the base emitter voltage of transistor T3
below 0.7 V, required voltage for the conduction of a transistor. Thus the diode D drives the transistor T 3 into
cutoff when T4 saturates.
Diodes D1 and D2 protect the transistor T1 from being damaged when the negative spikes of the voltage appears
at the inputs. When the negative spikes appear at the input terminals the diodes conducts and the spikes are
grounded. The transistors T3 and T4 and the diode D form the totem pole output, which provides the low output
impedance in every case. The TTL gates are faster having the propagation delay of about 15 nsec.

7.10.2 TTL Inverter: Figure 7.13 shows a TTL circuit for an inverter. The operation principle of this is same
as discussed for TTL NAND gate, with the difference that it has only one input. So when input A is at logic 0,
output will be high (logic 1) and if input is high (logic 1), output will be low (logic 0). This circuit also has the
totem-pole output.

Fig. 7.13

7.10.7 Tri-state TTL Gates: It has been observed from the above discussion that the open collector gate has the
facility for wire – AND, but they are slow in speed. However, the gates with totem pole outputs are faster in speed
but the connections for wire –AND are not possible. This led to the development of new device called tri-state
TTL gates. The tri-state devices allow three possible output states namely, High, Low and High impedance. The
high impedance state offers high impedance between the output terminal and ground or positive supply. Output
in this case is floating. A simple tri-state TTL circuit for inverter is shown in figure 7.19 (b) and its logical symbol
is given in figure 7.19 (b). In this circuit input A is the normal logic input while the ENABLE E terminal is an
enable input that can produce high impedance output.

Fig. 7.19 (a) Fig. 7.19 (b)

When ENABLE E terminal is high (logic 1), the diode D1 remains in reverse bias so it has no effect on
the working of transistors T3 and T4 and therefore circuit operates as normal inverter. When ENABLE E terminal
is low (logic 0), the diode D1 will be in
forward bias and it takes away the base current of transistor T3. So this transistor will be turned off. The forward
bias diode D1 also forward biases the emitter base junction of the transistor T1, transistor T2 will therefore be
turned off, which in turn turns off the transistor T4. So by applying logic 0 to the ENABLE E terminal both the
transistors T3 and T4 of totem pole output go in cutoff state.
The tri-state configuration is possible with other gates also with the similar circuits. The advantage of this
configuration is that wire –ANDing of the outputs of tristate ICs is possible and its speed is also fast.
7.10.8 More TTL Circuits: There are three families of TTL circuits, namely:
High Speed TTL circuits
Medium Speed TTL Circuits
Slow Speed TTL Circuits
The circuit of TTL NAND gate has been reproduced in figure 7.20 with three values of each resistor R 1,
R2, R3 and R4 for the three families. The low values of these resistances are for high speed but the power
dissipation will be larger because low values of resistances will draw large current from the supply. The 54H/74H
series for TTL gates are available and designed for high speed. The alphabet H represent for high speed. The
typical propagation delay for high speed gate is 6 nsec and power consumption is 22 mW. The medium values of
these resistances are for medium speed. The 54/74 series is available for medium speed TTL gates. This is the
standard series and the typical propagation delay for this series is 10 nsec and power consumption is 10 mW. For
slow speed TTL gates the values of resistances used are high and the series available for slow speed is 54L/74L.
The typical propagation delay for slow speed gate is 33 nsec and power consumption is 1 mW. The 54 series the
counterpart of 74 series and both are equivalent. The 54 series is used generally for military purposes, as this
series can be operated for wider temperature range and voltage ratings.
 Fig. 7.20
7.12 Emitter Coupled Logic (ECL): Emitter Coupled Logic (ECL) circuits fall in the category of non-
saturated digital logic family i.e. the transistors in this family do not saturate. This eliminates the storage time
delay, so the speed of operation of this family is increased. This logic family has the fastest speed and propagation
delay time per gate is approximately 1 nsec.
Figure 7.22 (a) shows the basic circuit of four-input ECL OR/NOR gate. The outputs provide both OR and NOR
functions. The transistors T1 through T5 form the differential amplifier circuit, transistor T6 forms the internal
temperature and voltage compensation bias network and the transistors T7 and T8 gives the emitter follower
outputs for OR and NOR functions. Logic levels for this family are negative, – 0.9 V is assumed for logic 1 and
– 1.75 V for logic 0. The operation of this circuit may be explained as follows:

Fig. 7.22 (a) Fig. 7.22 (b)

When all the inputs are at low (– 1.75 V), the transistors T1 through T4 are off, as emitter base junctions are reverse
biased. The transistor T5 is conducting not saturated. Due to the proper biasing of the transistor T 6, the base of
transistor T5 remains at – 1.29 V. Therefore its emitter is at – 2.09 V which is 0.8 V below the base voltage. The
transistor T5 therefore conducts. The differential voltage between base and emitter of the transistors T 1 through
T4 is about –0.34 V, so they are in cutoff. The emitter follower transistors T 7 and T8 give the outputs – 1.75 V
(logic 0) and – 0.9 V (logic1) respectively.
When any one or all the inputs are at – 0.9 V (logic1), in that condition the corresponding transistor or transistors
will conduct. The voltage at the emitters of T1 through T5 therefore rises to – 2.09 V. Since the base of transistor
T5 is held constant at – 1.29 V due to the bias network, it goes into cutoff. The emitter follower transistors T 7 and
T8 give the outputs – 0.9 V (logic1) and – 1.75 V (logic 0) respectively. Symbolic representation of OR/NOR ECL
gate is shown in figure 7.22 (b).
The wired logic can be formed by connecting together the outputs of two or more ECL gates as shown in figure
7.23. The external -wired connection of two NOR outputs produces a wired –OR function. The internal –wired
connection of two OR outputs in some ECL ICs is used to produce a wired –AND logic.

Fig. 7.23

7.14 Complementary MOS (CMOS) Logic: The complementary metal oxide semiconductor (CMOS)
logic family contains both enhancement type P-channel and Nchannel MOS FET’s arranged in a complementary
connection. The power consumption of CMOS logic family is very less as neither of P-channel or N-channel
MOS FET’s conducts simultaneously when no signal is applied to the input terminals of the logic. Thus only the
leakage current flows between the terminals of the supply. The CMOS gate can be operated on wide range of
supply voltage between 3 V to 15 V. It has good noise margin better than TTL devices. Fan-out of this is much
larger. The speed of the CMOS logic is comparable with that of TTL circuits but larger than Schottky TTL circuits.

7.14.1 CMOS Inverter: Figure 7.27 shows the circuit diagram of CMOS inverter which consist of a PMOS
transistor T1 and an NMOS transistor T2 which are connected in complementary mode. The drains of both the
transistors are connected together, through which the output is taken. The source terminal of PMOS transistor T 1
is connected to the positive supply, where as the source of the NMOS transistor T 2 is grounded.
When the input A is grounded (logic 0), the gate of PMOS transistor T1 is at the negative potential with respect
to its source, so it is ON. The gate of NMOS transistor T2 is at ground potential, so it is off. The output is, therefore,
high (+VDD), logic 1.
If on the other hand input A is high (logic 1), the gate of PMOS transistor T 1 is at zero potential with
respect to its source, so it is off. The gate of NMOS transistor T2 is at the positive potential with respect to ground,
so it is ON. The output is, therefore, low logic 0.
 Fig. 7.27
7.14.2 CMOS NAND Gate: The circuit diagram of CMOS NAND gate is shown in figure 7.28. The two PMOS
transistors T1 and T2 are connected in parallel with the sources connected together and two NMOS transistors T 3
and T4 are connected in series.
When both the inputs are at logic 0 (grounded), the gates of T1 and T2 are at negative potentials with respect to
their sources; the gates of T3 and T4 are at zero potential. So both PMOS transistors (T1 and T2) are ON and NMOS
transistors T3 and T4 are off. The output will, therefore, be high (logic 1).
When input A is at logic 0 (grounded) and input B is at logic 1, the gate of T1 is at negative potential with respect
to its source and the gate of T2 will be zero; the gates of T4 and T3 are at zero potential and VDD potential
respectively. So T1 and T3 are ON and T2 and T4 are off. The output will, therefore, be high (logic 1).

Fig. 7.28
When input A is at logic 1 and input B is at logic 0 (grounded), T1 and T3 will be off and T2 and T4 will be ON.
The output will, therefore, be high (logic 1).
When both the inputs are at logic 1 (+VDD), the gates of T1 and T2 are at zero potential; the gates of T3 and T4 are
at negative potentials with respect to their sources. So both PMOS transistors (T 1 and T2) are off and NMOS
transistors T3 and T4 are ON. The output will, therefore, be grounded (logic0).
 Problems
1. What is logic family? Give the classification of logic family.
2. Define the following parameters related to logic gates:
Fan-in, Fan-out, Propagation delay time, Power dissipation and Noise margin.
3. Draw and explain the circuit diagram of two-input TTL NAND gate. What are the advantages and
disadvantages of this logic family?
4. Discuss CMOS NAND gate. What are advantages of CMOS logic.
5. Discuss Emitter Coupled Logic (ECL). What are advantages of CMOS logic.