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AVR Microcontroller

The document provides an overview of AVR microcontrollers, including their architecture and memory organization. It discusses the ATmega32-8 microcontroller as an example, outlining its flash memory, SRAM, and peripherals. It also describes the program memory and data memory architecture of the ATmega328P microcontroller.

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22 views10 pages

AVR Microcontroller

The document provides an overview of AVR microcontrollers, including their architecture and memory organization. It discusses the ATmega32-8 microcontroller as an example, outlining its flash memory, SRAM, and peripherals. It also describes the program memory and data memory architecture of the ATmega328P microcontroller.

Uploaded by

23mz41
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AVR Microcontroller

Introduction
• AVR was developed in the year 1996 by Atmel Corporation.
• AVR derives its name from its developers and stands for Alf-Egil Bogen Vegard
Wollan RISC microcontroller, also known as Advanced Virtual RISC
• The AT90S8515 was the first microcontroller which was based on AVR architecture
• AVRs are about 4 times faster than PICs
– AVR microcontroller executes most of the instructions in single execution cycle
• They consume less power and can be operated in different power saving modes
• AVR is an 8-bit microcontroller belonging to the family of Reduced Instruction Set
Computer (RISC)
– This means that the microcontroller is capable of transmitting and receiving 8-bit data - The
input/output registers available are of 8-bits
• AVR microcontrollers are available in three categories:
1. TinyAVR – Less memory, small size, suitable only for simpler applications
2. MegaAVR – These are the most popular ones having good amount of memory (upto 256
KB), higher number of inbuilt peripherals and suitable for moderate to complex applications.
3. XmegaAVR – Used commercially for complex applications, which require large program
memory and high speed.
ATmega32-8
• The name of an ATmega 32-8 microcontroller can be broken down as follows:
– AT refers to Atmel the manufacturer
– Mega means that the microcontroller belong to MegaAVR category
– 32-8
• 32 signifies the memory of the controller, which is 32 KB
• 8 represents the 8-bit architecture
– p: Indicates pico power, which means it consumes the lowest power in standby and sleep mode
• Advanced Virtual RISC (AVR) microcontroller.
• Supports 8-bit data processing.
• 32kB internal flash memory.
• 1kB Electrically Erasable Programmable Read-Only Memory (EEPROM).
– This property shows if the electric supply supplied to the micro-controller is removed, even
then it can store the data and can provide results after providing it with the electric supply.
• 2kB Static Random Access Memory (SRAM)
• Number of ADC Channels : 8
• PWM Pins : 1
• Comparator: 1
• Timer : 3
AVR Architecture
ATmega328P Flash Program Memory

• The ATmega328P contains 32Kbytes


On-chip In-System Reprogrammable
Flash memory for program storage.
• The Flash is organized as 16K x 16.
• For software security, the Flash
Program memory space is divided
into two sections
– Boot Loader Section
– Application Program section.
• The ATmega328P Program Counter
(PC) is 14 bits wide and addresses the
16K program memory locations.
• The Range of memory address for
ATmega328P Flash Memory is 0x0000
– 0x3FFF.
ATmega328P SRAM Data Memory
• Data can be accessed through the standard data
bus (Load/Store Instructions).
• There is a secondary In/Out Bus for rapid direct
access to select locations.
– Registers (32 x 8-bit) (0000 16–001F16)
Consists of 32 8-bit general purpose working registers (R0-
R31)
– I/O Memory (64 x 8-bit) (002016–005F16)

• Contains a ddressable space for peripheral control registers and other I/O
regi sters
• Peri pheral units ca n be supported within the 64 l ocations reserved i n the
Opcode for the IN and OUT i nstructions.
– Extended I/O Memory (device dependent) (160 x 8-bit)
(006016–00FF16)

• Some AVR mi crocontrollers with more peripherals need more space than
the I/O memory
• s ome of the SRAM is used as Extended I/O memory to handle the extra
peri pherals control registers and other I/O functions
• the ST/STS/STD (Store) and LD/LDS/LDD (Load) i nstructions ca n be used
• The IN/OUT data bus has direct a ccess to the 64-byte I/O Memory s ection
(not Extended) using a 0x00 to 0x1F a ddress.
– Internal SRAM (2048 x 8-bit) (010016–08FF16)

• SRAM i s used for temporarily s toring i ntermediate results and va riables,


s tack within a software a pplication.

•
• There are five different data bus addressing modes for
the data memory:
– Direct – The direct addressing reaches the entire data
space.
– Indirect – In the Register File, registers R26 to R31 feature
the indirect addressing pointer registers.
– Indirect with Displacement – The Indirect with
Displacement mode reaches 63 address locations from the
base address given by the Y or Z register.
– Indirect with Pre-decrement – The address registers X, Y,
and Z are decremented.
– Indirect with Post-increment – The address registers X, Y,
and Z are incremented.

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