Features

Fast Read Access Time 150 ns Automatic Page Write Operation

Internal Address and Data Latches for 64 Bytes

Fast Write Cycle Times

Page Write Cycle Time: 10 ms Maximum (Standard) 2 ms Maximum (Option) 1 to 64-byte Page Write Operation Low Power Dissipation 40 mA Active Current 100 A CMOS Standby Current Hardware and Software Data Protection DATA Polling and Toggle Bit for End of Write Detection High Reliability CMOS Technology Endurance: 100,000 Cycles Data Retention: 10 Years Single 5 V 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Commercial and Industrial Temperature Ranges

Description
The AT28C64B is a high-performance electrically-erasable and programmable read only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device offers

64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection AT28C64B

Pin Configurations
Pin Name A0 - A12 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Dont Connect PLCC Top View
A7 A12 NC DC VCC WE NC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND

PDIP, SOIC Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3

TSOP Top View

OE A11 A9 A8 NC WE VCC NC A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2

Note:

PLCC package pins 1 and 17 are DONT CONNECT.

I/O1 I/O2 GND DC I/O3 I/O4 I/O5

14 15 16 17 18 19 20

A6 A5 A4 A3 A2 A1 A0 NC I/O0

5 6 7 8 9 10 11 12 13

4 3 2 1 32 31 30

29 28 27 26 25 24 23 22 21

A8 A9 A11 NC OE A10 CE I/O7 I/O6

Rev. 0270IPEEPR08/03

access times to 150 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 A. The AT28C64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmels AT28C64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

Block Diagram
VCC GND OE WE CE Y DECODER ADDRESS INPUTS X DECODER IDENTIFICATION DATA INPUTS/OUTPUTS I/O0 - I/O7

OE, CE and WE LOGIC

DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING CELL MATRIX

Absolute Maximum Ratings*

Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .................................-0.6 V to +6.25 V All Output Voltages with Respect to Ground ...........................-0.6 V to VCC + 0.6 V Voltage on OE and A9 with Respect to Ground ..................................-0.6 V to +13.5V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

AT28C64B
0270IPEEPR08/03

AT28C64B
Device Operation
READ: The AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state when either CE or OE is high. This dual line control gives designers flexibility in preventing bus contention in their systems. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded within 150 s (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28C64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same. The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle. TOGGLE BIT: In addition to DATA Polling, the AT28C64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a) VCC sense if VCC is below 3.8 V (typical), the write function is inhibited; (b) VCC power-on delay once V CC has reached 3.8 V, the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit holding any one of OE low, CE high, or WE high inhibits write cycles; and (d) noise filter pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C64B. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP disabled. SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (See Software Data Pro-

3
0270IPEEPR08/03

tection Algorithms on page 9.). After writing the 3-byte command sequence and waiting tWC, the entire AT28C64B will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28C64B by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP remains active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device. However, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12 V 0.5 V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.

DC and AC Operating Range

AT28C64B-15 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5 V 10% AT28C64B-20 0C - 70C -40C - 85C 5 V 10% AT28C64B-25 0C - 70C -40C - 85C 5 V 10%

Operating Modes
Mode Read Write
(2)

CE VIL VIL VIH X X X VIL

OE VIL VIH X
(1)

WE VIH VIL X VIH X X VIL

I/O DOUT DIN High Z

Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. 2. See AC Write Waveforms on page 7. 3. VH = 12.0 V 0.5 V.

X VIL VIH VH
(3)

High Z High Z

AT28C64B
0270IPEEPR08/03

AT28C64B
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 2.0 0.40 Condition VIN = 0 V to VCC + 1 V VI/O = 0 V to VCC CE = V CC - 0.3 V to VCC + 1 V CE = 2.0 V to VCC + 1 V f = 5 MHz; IOUT = 0 mA Com., Ind. Min Max 10 10 100 2 40 0.8 Units A A A mA mA V V V V

AC Read Characteristics
AT28C64B-15 Symbol tACC tCE
(1)

AT28C64B-20 Min Max 200 200 0 0 0 80 55

AT28C64B-25 Min Max 250 250 0 0 0 100 60 Units ns ns ns ns ns

Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first

Min

Max 150 150

tOE(2) tDF(3)(4) tOH

0 0 0

70 50

AC Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID

CE tCE OE tOE tOH tACC OUTPUT

Notes:

tDF

HIGH Z

OUTPUT VALID

1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.

5
0270IPEEPR08/03

Input Test Waveforms and Measurement Level

tR, tF < 5 ns

Output Test Load

Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0 V VOUT = 0 V

1. This parameter is characterized and is not 100% tested.

AC Write Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Min 0 50 0 0 100 50 0 Max Units ns ns ns ns ns ns ns

AT28C64B
0270IPEEPR08/03

AT28C64B
AC Write Waveforms
WE Controlled
OE tOES tOEH

ADDRESS tAS CE tCS WE tWP tDS DATA IN tDH tCH tAH

CE Controlled
OE tOES tOEH

ADDRESS tAS WE tCS CE tWP tDS DATA IN tDH tCH tAH

7
0270IPEEPR08/03

Page Mode Characteristics

Symbol tWC tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Write Cycle Time (option available; contact Atmel sales office for ordering part number) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 Min Max 10 2 Units ms ms ns ns ns ns ns s ns

Page Mode Write Waveforms(1)(2)

OE

CE tWP WE tAS tAH A0 -A12 VALID ADD tDS DATA VALID DATA tDH tWPH tBLC

tWC

Notes:

1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low.

AT28C64B
0270IPEEPR08/03

AT28C64B
Chip Erase Waveforms

tS

tH

tW
tS = tH = 1 s (min.) tW = 10 ms (min.) VH = 12.0 V 0.5 V

Software Data Protection Algorithms

Software Data Protection Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 1555

LOAD DATA 55 TO ADDRESS 0AAA

LOAD DATA A0 TO ADDRESS 1555

WRITES ENABLED(2)

LOAD DATA XX TO ANY ADDRESS(4)

LOAD LAST BYTE TO LAST ADDRESS

ENTER DATA PROTECT STATE

Note:

1. Notes for software program code: 2. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 3. Write Protect state will be activated at end of write even if no other data is loaded. 4. Write Protect state will be deactivated at end of write period even if no other data is loaded. 5. 1 to 64 bytes of data are loaded.

9
0270IPEEPR08/03

Software Data Protection Disable Algorithm(1)

LOAD DATA AA TO ADDRESS 1555

LOAD DATA 55 TO ADDRESS 0AAA

LOAD DATA 80 TO ADDRESS 1555

LOAD DATA AA TO ADDRESS 1555

LOAD DATA 55 TO ADDRESS 0AAA

LOAD DATA 20 TO ADDRESS 1555

EXIT DATA PROTECT STATE(3)

LOAD DATA XX TO ANY ADDRESS(4)

LOAD LAST BYTE TO LAST ADDRESS

Note:

1. Notes for software program code: 2. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 3. Write Protect state will be activated at end of write even if no other data is loaded. 4. Write Protect state will be deactivated at end of write period even if no other data is loaded. 5. 1 to 64 bytes of data are loaded.

10

AT28C64B
0270IPEEPR08/03

AT28C64B
Software Protected Write Cycle Waveforms(1)(2)
OE

CE tWP WE tAS tAH A0 -A5 tDH

tWPH

tBLC

A6 - A12 tDS DATA tWC

Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low.

11
0270IPEEPR08/03

Data Polling Characteristics(1)

Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(1)

Min 0 0

Typ

Max

Units ns ns ns

Write Recovery Time

ns

1. These parameters are characterized and not 100% tested. See AC Read Characteristics on page 5.

Data Polling Waveforms

tOEH tDH tOE

tWR

12

AT28C64B
0270IPEEPR08/03

AT28C64B
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics on page 5.
(2)

Min 10 10

Typ

Max

Units ns ns ns

150 0

ns ns

Toggle Bit Waveforms(1)(2)(3)

tOEH

tOEHP

tDH

tOE tWR

Notes:

1. 2. 3.

Toggling either OE or CE or both OE and CE will operate toggle bit. Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.

13
0270IPEEPR08/03

14

AT28C64B
0270IPEEPR08/03

AT28C64B
Ordering Information(1)
tACC (ns) ICC (mA) Active Standby Ordering Code AT28C64B-15JC AT28C64B-15PC AT28C64B-15SC AT28C64B-15TC AT28C64B-15JI AT28C64B-15PI AT28C64B-15SI AT28C64B-15TI AT28C64B-20JC AT28C64B-20PC AT28C64B-20SC AT28C64B-20TC AT28C64B-20JI AT28C64B-20PI AT28C64B-20SI AT28C64B-20TI AT28C64B-25JC AT28C64B-25PC AT28C64B-25SC AT28C64B-25TC AT28C64B-25JI AT28C64B-25PI AT28C64B-25SI AT28C64B-25TI Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Operation Range Commercial (0C to 70C)

150

40

0.1

Industrial (-40C to 85C)

Commercial (0C to 70C)

200

40

0.1

Industrial (-40C to 85C)

Commercial (0C to 70C)

250

40

0.1

Industrial (-40C to 85C)

Note:

1. See Valid Part Numbers on page 15.

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.
Device Numbers AT28C64B AT28C64B AT28C64B AT28C64B Speed 15 20 25 Package and Temperature Combinations JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI W

Die Products
Reference Section: Parallel EEPROM Die Products

15
0270IPEEPR08/03

Package Type 32J 28P6 28S 28T W 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP) Die

16

AT28C64B
0270IPEEPR08/03

AT28C64B
Packaging Information
32J PLCC

1.14(0.045) X 45

PIN NO. 1 IDENTIFIER

1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)

E1 B

B1

E2

e D1 D A A2 A1

0.51(0.020)MAX 45 MAX (3X)

COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL

D2

MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330

NOM 1.270 TYP

MAX 3.556 2.413 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533

NOTE

A A1 A2 D D1 D2

Note 2

Notes:

1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.

E E1 E2 B B1 e

Note 2

10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B

17
0270IPEEPR08/03

28P6 PDIP

PIN 1

E1

SEATING PLANE

L B1 e E B

A1

C eB

0 ~ 15

REF
SYMBOL A A1 D E E1 B

COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.381 36.703 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM 2.540 TYP MAX 4.826 37.338 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

B1 L C eB e

09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P6 REV. B

18

AT28C64B
0270IPEEPR08/03

AT28C64B
28S SOIC

Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters.

0.51(0.020) 0.33(0.013)

7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394)

PIN 1

1.27(0.50) BSC
TOP VIEW

18.10(0.7125) 17.70(0.6969)

2.65(0.1043) 2.35(0.0926)

0.30(0.0118) 0.10(0.0040)
SIDE VIEWS

0 ~ 8

0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016)

8/4/03

2325 Orchard Parkway San Jose, CA 95131

TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013

DRAWING NO. 28S

REV. B

19
0270IPEEPR08/03

Atmel Corporation
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0270IPEEPR08/03 xM

This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.