Atmel Ata6612p-Plpw

General Features
• Single-package Fully-integrated AVR® 8-bit Microcontroller with LIN Transceiver,

5V Regulator and Watchdog
• Very Low Current Consumption in Sleep Mode
• 8 Kbytes/16 Kbytes Flash Memory for Application Program (ATA6612/ATA6613)
• Supply Voltage Up to 40V
• Operating Voltage: 5V to 27V
• Temperature Range: Tcase –40°C to +125°C
• QFN48, 7 mm × 7 mm Package
Microcontroller
1. Description with LIN
ATA6612/ATA6613 is a System-in-Package (SiP) product, which is particularly suited
for complete LIN-bus slave-node applications. It supports highly integrated solutions Transceiver,
for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC)
ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window
5V Regulator
watchdog. The second chip is an automotive microcontroller from Atmel®’s series of
AVR 8-bit microcontroller with advanced RISC architecture.
and Watchdog
The ATA6612 consists of the LIN-SBC ATA6624 and the ATmega88 with 8 Kbytes
flash. The ATA6613 consists of the LIN-SBC ATA6624 and the ATmega168 with
16 Kbytes flash. All pins of the LIN System Basis Chip as well as all pins of the AVR
ATA6612
microcontroller are bonded out to provide customers the same flexibility for their appli- ATA6613
cations as they have when using discrete parts.
In section 2 you will find the pin configuration for the complete SiP. In sections 3 to 5
the LIN SBC is described, and in sections 6 to 7 the AVR is described in detail.
Figure 1-1. Application Diagram

LIN Bus
ATA6612/ATA6613
MCU LIN-SBC
ATmega88 ATA6624
or
ATmega168
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2. Pin Configuration
Figure 2-1. Pinning QFN48, 7 mm × 7 mm
MCUVDD2
GND2
PD7
PD6
PD5
PB4
PB3
PB2
PB1
PB0
PB7
PB6
48 47 46 45 44 43 42 41 40 39 38 37
PB5 1 36 MCUVDD1
MCUAVDD 2 35 GND1
ADC6 3 34 PD4
AREF 4 33 PD3
GND4 5 32 LIN
ADC7 6 31 GND
PC0 7 30 WAKE
PC1 8 29 NTRIG
PC2 9 28 EN
PC3 10 27 VS
PC4 11 26 VCC
PC5 12 25 PVCC
13 14 15 16 17 18 19 20 21 22 23 24
WD_OSC
NRES
TXD
MODE
RXD
KL_15
INH
PD1
PD2
PC6
TM
PD0
Table 2-1. Pin Description

Pin Symbol Function
1 PB5 Port B 5 I/O line (SCK / PCINT5)
2 MCUAVDD Microcontroller ADC-unit supply voltage
3 ADC6 ADC input channel 6
4 AREF Analog reference voltage input
5 GND4 Ground
6 ADC7 ADC input channel 7
7 PC0 Port C 0 I/O line (ADC0/PCINT8)
11 PC4 Port C 4 I/O line (ADC4/SDA/PCINT12)
12 PC5 Port C 5 I/O line (ADC5/SCL/PCINT13)
13 PC6 Port C 6 I/O line (RESET/PCINT14)
14 PD0 Port D 0 I/O line (RXD/PCINT16)
15 PD1 Port D 1 I/O line (TXD/PCINT17)
16 PD2 Port D 2 I/O line (INT0/PCINT18)
(1)
17 RXD Receive data output
18(1) INH High side switch output for controlling an external voltage regulator
19(1) TXD Transmit data input / active low output after a local wake up request
Note: 1. This identifies the pins of the LIN SBC ATA6624
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Table 2-1. Pin Description (Continued)

Pin Symbol Function
(1)
20 NRES Watchdog and undervoltage reset output (open drain)
(1)
21 WD_OSC External resistor for adjustable watchdog timing
22(1) TM Tie to Ground – for factory use only
(1)
23 MODE Connect to GND for normal watchdog operation or connect to VCC for debug mode
(1)
24 KL_15 Ignition detection (edge sensitive)
(1)
25 PVCC Voltage regulator sense input
26(1) VCC Voltage regulator output
(1)
27 VS Battery connection
(1)
28 EN LIN-transceiver enable input
(1)
29 NTRIG Watchdog trigger input (negative edge)
30(1) WAKE System-basis-chip external wake-up input
31(1) GND Analog system GND
(1)
32 LIN LIN-bus input/output
33 PD3 Port D 3 I/O line (INT1 OC2B/PCINT19)
34 PD4 Port D 4 I/O line (T0/XCK/PCINT20)
35 GND1 Ground
36 MCUVDD1 Microcontroller supply voltage
37 GND2 Ground
38 MCUVDD2 Microcontroller supply voltage
39 PB6 Port B 6 I/O line (TOSC1/XTAL1/PCINT6)
40 PB7 Port B 7 I/O line (TOSC2/XTAL2/PCINT7)
41 PD5 Port D 5 I/O line (T1/OC0B/PCINT21)
42 PD6 Port D 6 I/O line (AIN0/OC0A PCINT22)
43 PD7 Port D 7 I/O line (AIN1/PCINT23)
44 PB0 Port B 0 I/O line (ICP1/CLKO/PCINT0)
45 PB1 Port B 1 I/O line (OC1A/PCINT1)
46 PB2 Port B 2 I/O line (OC1B/SS/PCINT2)
47 PB3 Port B 3 I/O line (MOSI/OC2A/PCINT3)
48 PB4 Port B 4 I/O line (MISO/PCINT4)
Backside Heat slug is connected to GND
Note: 1. This identifies the pins of the LIN SBC ATA6624
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Table 2-2. Maximum Ratings of the SiP
Parameters Symbol Min. Typ. Max. Unit
HBM ESD
ANSI/ESD-STM5.1
±2 KV
JESD22-A114
AEC-Q100 (002)
CDM ESD STM 5.3.1 ±750 V
Storage temperature Ts –55 +150 °C
(1)
Operating temperature Tcase –40 +125 °C
Thermal resistance junction to heat slug Rthjc 5 K/W
Thermal resistance junctiion to ambient,
Rthja 25 K/W
according to JEDEC
Thermal shutdown of VCC regulator 150 165 170 °C
Thermal shutdown of LIN output 150 165 170 °C
Thermal shutdown hysteresis 10 °C
Note: 1. Tcase means the temperature of the heat slug (backside). It is mandatory that this backside temperature is ≤ 125°C in the
application.
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3. LIN System-basis-chip Block
3.1 Features
• Master and Slave Operation Possible
• Supply Voltage up to 40V
• Operating voltage VS = 5V to 27V
• Typically 10 µA Supply Current During Sleep Mode
• Typically 57 µA Supply Current in Silent Mode
• Linear Low-drop Voltage Regulator:
• Normal, Fail-safe, and Silent Mode
• VCC = 5.0V ±2%
• In Sleep Mode VCC is Switched Off
• VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical Combined at Open
Drain Output NRES
• Negative Trigger Input for Watchdog
• Boosting the Voltage Regulator Possible with an External NPN Transistor
• LIN Physical Layer According to LIN 2.0 Specification and SAEJ2602-2
• Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin
• INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up Resistor
• TXD Time-out Timer
• Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery
• Adjustable Watchdog Time via External Resistor
• Advanced EMC and ESD Performance
• ESD HBM 8 kV at Pins LIN and VS According to STM5.1
3.2 Description
The LIN-SBC is a fully integrated LIN transceiver, which complies with the LIN 2.0 and
SAEJ2602-2 specifications. It has a low-drop voltage regulator for 5V/50 mA output and a win-
dow watchdog.
The LIN-SBC are designed to handle the low-speed data communication in vehicles, e.g., in
convenience electronics. Improved slope control at the LIN-driver ensures secure data commu-
nication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low current consumption.
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Figure 3-1. Block Diagram
27
VS
Normal and
Fail-safe
18 Mode
INH Normal and
PVCC Receiver Fail-safe
Mode
17
RXD
32
RF Filter LIN
30
WAKE
24
Edge Wake-up
KL_15
Detection Bus Timer
PVCC Short Circuit and
Overtemperature
Slew Rate Control Protection
19 TXD
TXD Time-out
Timer
Control Unit 26
Normal/Silent/ VCC
Fail-safe Mode 25
28 Debounce /50 mA/2% PVCC
EN Time Mode Select
Undervoltage 20
Reset NRES
OUT Adjustable 21
Internal Testing
Watchdog Watchdog WD_OSC
Unit
31 Oscillator
GND
PVCC
23 22 29
MODE TM NTRIG
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3.3 Functional Description
3.3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
3.3.2 Supply Pin (VS)

The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to dis-
able data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After
switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e.,
output capability).
The supply current is typically 10 µA in Sleep Mode and 57 µA in Silent Mode.
3.3.3 Ground Pin (GND)

The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground
shift up to 11.5% of VS. The mandatory system ground is pin 5.
3.3.4 Voltage Regulator Output Pin (VCC)

The internal voltage regulator is capable of driving loads with up to 50 mA. It is able to supply the
microcontroller and other ICs on the PCB and is protected against overloads by means of cur-
rent limitation and overtemperature shut-down. Furthermore, the output voltage is monitored
and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun.
To boost up the maximum load current, an external NPN transistor may be used, with its base
connected to the VCC pin and its emitter connected to PVCC.
3.3.5 Voltage Regulator Sense Pin (PVCC)

The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when
only using the internal output transistor), this pin is connected to the VCC pin. If an external
boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e.,
its emitter terminal.
3.3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown and an internal pull-up
resistor compliant with the LIN 2.0 specification are implemented. The allowed voltage range is
between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the
event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the
LIN protocol specification. The fall time from recessive to dominant bus state and the rise time
from dominant to recessive bus state are slope controlled.
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3.3.7 Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN
output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or uncon-
nected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in
recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8 mA.
and is latched to low if the last wake-up event was from pin WAKE or KL_15.
3.3.8 TXD Dominant Time-out Function

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in dominant state. If TXD is forced to low for longer than tDOM > 6 ms, the
LIN-bus driver is switched to recessive state. Nevertheless, when switching to Sleep Mode, the
actual level at the TXD pin is relevant.
To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
3.3.9 Output Pin (RXD)

The Output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state)
is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD.
The output has an internal pull-up structure with typically 5 kΩ to VCC. The AC characteristics
can be defined with an external load capacitor of 20 pF.
The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V).
3.3.10 Enable Input Pin (EN)

The Enable Input pin controls the operation mode of the interface. If EN is high, the interface is
in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The
VCC voltage regulator operates with output capability.
If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data trans-
mission is then possible, and the current consumption is reduced to IVS typ. 57 µA. The VCC
regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmis-
sion is possible, and the voltage regulator is switched off.
3.3.11 Wake Input Pin (WAKE)

The Wake Input pin is a high-voltage input used to wake up the device from Sleep Mode or
Silent Mode. It is usually connected to an external switch in the application to generate a local
wake-up. A pull-up current source, typically 10 µA, is implemented.
If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin.
3.3.12 Mode Input Pin (MODE)

Connect the MODE pin directly or via an external resistor to GND for normal watchdog opera-
tion. To debug the software of the connected microcontroller, connect MODE pin and the
watchdog is switched off.
3.3.13 TM Input Pin

The TM pin is used for final production measurements at Atmel. In normal application, it has to
be always connected to GND.
8 ATA6612/ATA6613
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3.3.14 KL_15 Pin

The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It
is an edge sensitive pin (low-to-high transition). It is usually connected to ignition to generate a
local wake-up in the application when the ignition is switched on. Although KL_15 pin is high
voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin
directly to GND if you do not need it. A debounce timer with a typical Tdb Kl_15 of 160 µs is
implemented.
The input voltage threshold can be adjusted by varying the external resistor due to the input cur-
rent IKL_15. To protect this pin against voltage transients, a serial resistor of 50 kΩ and a ceramic
capacitor of 100 nF are recommended. With this RC combination you can increase the wake-up
time TwKL_15 and, therefore, the sensitivity against transients on the ignition Kl.30.
You can also increase the wake-up time using external capacitors with higher values.
3.3.15 INH Output Pin

The INH Output pin is used to switch an external voltage regulator on during Normal or Fail-safe
Mode. The INH pin is switched off in Sleep or Silent Mode. It is possible to switch off the external
1 kΩ master resistor via the INH pin for master node applications. The INH pin is switched off
during VCC undervoltage reset.
3.3.16 Reset Output Pin (NRES)

The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a
watchdog failure.
3.3.17 WD_OSC Output Pin

The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor
with values between 34 kΩ and 120 kΩ to adjust the watchdog oscillator time.
3.3.18 NTRIG Input Pin

The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is imple-
mented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a
minimum time ttrigmin to generate a watchdog trigger.
3.3.19 Wake-up Events from Sleep or Silent Mode

• LIN-bus
• WAKE pin
• EN pin
• KL_15
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3.3.20 Modes of Operation
Figure 3-2. Modes of Operation
Unpowered Mode a: VS > 5V

VBatt = 0V b: VS < 4V
c: Bus wake-up event
d: Wake up from WAKE or KL_15 pin
b a e: NRES switches to low
Fail-safe Mode b
b VCC: With undervoltage monitoring b

Communication: OFF
Watchdog: ON c+d+e
e
EN = 1 EN = 1
c+d
Go to silent command
EN = 0 Silent Mode
TXD = 1 VCC: With undervoltage
Local wake-up event monitoring
Normal Mode EN = 1
Communication: OFF
VCC: With undervoltage Watchdog: OFF
monitoring
Go to sleep command
Communication: ON EN = 0 Sleep Mode
Watchdog: ON
TXD = 0 VCC: switched off
Communication: OFF
Watchdog: OFF
3.3.20.1 Normal Mode

This is the normal transmitting and receiving mode. The voltage regulator is in Normal Mode and
can source 50 mA. The undervoltage detection is activated. The watchdog needs a trigger sig-
nal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes state to
Fail-safe Mode.
3.3.20.2 Silent Mode

A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to
be logic high during the Mode Select window (see Figure 3-3 on page 11). The transmission
path is disabled in Silent Mode. The overall supply current from VBatt is a combination of the IVSsi
57 µA plus the VCC regulator output current IVCC.
The regulator with a 2% tolerance can source up to 50 mA. The internal slave termination
between the LIN pin and the VS pin is disabled in Silent Mode to minimize the power dissipation
in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically
10 µA) between the LIN pin and the VS pin is present. Silent Mode can be activated indepen-
dently from the actual level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition
occurs, the NRES is switched to low, and the IC changes its state to Fail-safe Mode.
With EN high, you can switch directly from Silent mode to Normal mode.
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN
receiver.
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Figure 3-3. Switch to Silent Mode
Normal Mode Silent Mode
EN
Mode select window

TXD
td = 3.2 µs
NRES
VCC
Delay time silent mode

td_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (tbus) and the following rising edge at the LIN pin (see Figure 3-4 on page 12) result in a
remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The internal
LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low
level at the RXD pin to interrupt the microcontroller (see Figure 3-4 on page 12). EN high can be
used to switch directly to Normal Mode.
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Figure 3-4. LIN Wake-up from Silent Mode
Bus wake-up filtering time
tbus Fail-safe mode Normal mode
LIN bus
Node in silent mode
RXD High Low High
TXD
Watchdog Watchdog off Start watchdog lead time td
VCC
voltage Silent mode Fail-safe mode Normal mode
regulator
EN High
EN
NRES Undervoltage detection active
3.3.20.3 Sleep Mode

A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to
be logic low during the Mode Select window (Figure 3-5 on page 13). The transmission path is
disabled in Sleep Mode. The supply current IVSsleep from VBatt is typically 10 µA.
The VCC regulator is switched off. NRES and RXD are low. The internal slave termination
between the LIN pin and VS pin is disabled to minimize the power dissipation in the event that
the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between the
LIN pin and the VS pin is present. Sleep Mode can be activated independently from the current
level on the LIN, WAKE, or KL_15 pin.
receiver.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (tbus) and a rising edge at pin LIN respectively result in a remote wake-up request. The
device switches from Sleep Mode to Fail-safe Mode.
12 ATA6612/ATA6613
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ATA6612/ATA6613
The VCC regulator is activated, and the internal LIN slave termination resistor is switched on.
The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcon-
troller (see Figure 3-6 on page 14).
EN high can be used to switch directly from Sleep/Silent to Fail-safe Mode. If EN is still high after
VCC ramp up and undervoltage reset time, the IC switches to the Normal Mode.
Figure 3-5. Switch to Sleep Mode

Normal Mode Sleep Mode
EN
Mode select window

TXD
td = 3.2 µs
NRES
VCC
Delay time sleep mode

td_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
3.3.20.4 Fail-safe Mode

The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator
is switched on (VCC = 50 mA) (see Figure 3-7 on page 17). The NRES output switches to low
for tres = 4 ms and gives a reset to the microcontroller. LIN communication is switched off. The IC
stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power
down of VBatt (VS < 4V) during Silent or Sleep Mode switches the IC into Fail-safe Mode after
power up. A low at NRES switches into Fail-safe Mode directly. During Fail-safe Mode the TXD
pin is an output and signals the last wake-up source.
3.3.20.5 Unpowered Mode

If you connect battery voltage to the application circuit, the voltage at the VS pin increases
according to the block capacitor (see Figure 3-7 on page 17). After VS is higher than the VS
undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode.
The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the
VCC capacitor and the load.
The NRES is low for the reset time delay treset . During this time, treset, no mode change is
possible.
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Figure 3-6. LIN Wake-up from Sleep Mode
Bus wake-up filtering time
tbus Fail-safe Mode Normal Mode
LIN bus
RXD Low or floating Low
TXD
VCC On state
voltage Off state
regulator
Regulator wake-up time
EN High
EN
Reset
time
NRES Floating
Microcontroller
start-up time delay
Watchdog Watchdog off Start watchdog lead time td
Table 3-1. Table of Modes

Mode of
Operation Transceiver VCC Watchdog WD_OSC INH RXD LIN
Fail-safe Off - On 1.23V On High Recessive
TXD
Normal On - On 1.23V On High
deppending
Silent Off - Off 0V Off High Recessive
Sleep Off 0V Off 0V Off 0V Recessive
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3.3.21 Wake-up Scenarios from Silent to Sleep Mode
3.3.21.1 Remote Wake-up via Dominant Bus State

receiver.
A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain
time period (tBUS) and a rising edge at pin LIN result in a remote wake-up request. The device
switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains
activated, the INH pin is switched to high, and the internal slave termination resistor is switched
on. The remote wake-up request is indicated by a low level at the RXD pin to generate an inter-
rupt for the microcontroller. A low level at the LIN pin in the Normal Mode starts the bus wake-up
filtering time, and if the IC is switched to Silent or Sleep Mode, it will receive a wake-up after a
positive edge at the LIN pin.
3.3.21.2 Local Wake-up via Pin Wake

A falling edge at the WAKE pin followed by a low level maintained for a certain time period
(tWAKE) results in a local wake-up request. The device switches to Fail-safe Mode. The internal
slave termination resistor is switched on. The local wake-up request is indicated by a low level at
the RXD pin to generate an interrupt in the microcontroller and a strong pull down at TXD. When
the Wake pin is low, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the
wake-up signal has to be switched to high > 10 µs before the negative edge at WAKE starts a
new local wake-up request.
3.3.21.3 Local Wake-up via Pin KL_15

A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15)
results in a local wake-up request. The device switches into the Fail-safe Mode. The internal
slave termination resistor is switched on. The extra long wake-up time ensures that no transients
at KL_15 create a wake up. The local wake-up request is indicated by a low level at the RXD pin
to generate an interrupt for the microcontroller and a strong pull down at TXD. During high-level
voltage at pin KL_15, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the
wake-up signal has to be switched to low > 250 µs before the positive edge at KL_15 starts a
new local wake-up request. With external RC combination, the time is even longer.
3.3.21.4 Wake-up Source Recognition

The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a
remote wake-up request (dominant LIN bus state). The wake-up source can be read on the TXD
pin in Fail-safe Mode. A high level indicates a remote wake-up request (weak pull up at the TXD
pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The
wake-up request flag (signalled on the RXD pin), as well as the wake-up source flag (signalled
on the TXD pin), is immediately reset if the microcontroller sets the EN pin to high (see Figure
3-3 on page 11 and Figure 3-4 on page 12) and the IC is in Normal Mode. The last wake-up
source flag is stored and signalled in Fail-safe Mode at the TXD pin.
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3.3.22 Fail-safe Features
• During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_LIM. Due to
the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched
off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD
stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator
works independently.
• During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If
the short-circuit disappears, the IC starts with a remote wake-up.
• The reverse current is very low < 15 µA at the LIN pin during loss of VBatt or GND. This is
optimal behavior for bus systems where some slave nodes are supplied from battery or
ignition.
• During a short circuit at VCC, the output limits the output current to IVCCn. Because of
undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC
switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC
output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of the Fail-safe Mode, the VCC voltage will switch on again although EN is
switched off from the microcontroller. The microcontroller can start with its normal operation.
• EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is
disconnected.
• RXD pin is set floating if VBatt is disconnected.
• TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is
disconnected.
• If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after
tdom > 20 ms.
• If the WD_OSC pin has a short-circuit to GND or the resistor is disconnected, the watchdog
runs with an internal oscillator and guarantees a reset after the second NTRIG signal at the
latest.
3.3.23 Voltage Regulator

The voltage regulator needs an external capacitor for compensation and for smoothing the dis-
turbances from the microcontroller. It is recommended to use an electrolythic capacitor with
C > 10 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be var-
ied by the customer, depending on the application.
The main power dissipation of the IC is created from the VCC output current IVCC , which is
needed for the application.
16 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 3-7. VCC Voltage Regulator: Ramp Up and Undervoltage Detection
VS
12V
TVCC TReset Tres_f t

NRES
For programming purposes of the microcontroller it is potentially neccessary to supply the VCC
output via an external power supply while the VS Pin of the system basis chip is disconnected.
This behavior is no problem for the system basis chip.
3.3.24 Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)
input within a time window of T w d . The trigger signal must exceed a minimum time
ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output
NRES. After a watchdog reset the IC starts with the lead time. The timing basis of the watchdog
is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor
Rwd_osc (34 kΩ to 120 kΩ).
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES
disappears. It is defined as lead time td. After wake up from Sleep or Silent Mode, the lead time
td starts with the negative edge of the RXD output.
17
9111E–AUTO–07/08
3.3.24.1 Typical Timing Sequence with RWD_OSC = 51 kΩ
The trigger signal T wd is adjustable between 20 ms and 64 ms using the external resistor
RWD_OSC.
For example, with an external resistor of RWD_OSC = 51 kΩ ±1%, the typical parameters of the
watchdog are as follows:
tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ; tosc in µs)
tOSC = 19.6 µs due to 51 kΩ
td = 7895 × 19.6 µs = 155 ms
t1 = 1053 × 19.6 µs = 20.6 ms
t2 = 1105 × 19.6 µs = 21.6 ms
tnres = constant = 4 ms
After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output
NRES stays low for the time treset (typically 4 ms), then it switches to high, and the watchdog
waits for the trigger sequence from the microcontroller. The lead time, td, follows the reset and is
td = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trig-
ger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal
occurs during the time td, a watchdog reset with tNRES = 4 ms will reset the microcontroller after
td = 155 ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal
from the microcontroller is anticipated within the time frame of t2 = 21.6 ms. To avoid false trig-
gering from glitches, the trigger pulse must be longer than tTRIG,min > 200 ns. This slope serves to
restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES
output will be drawn to ground. A triggering signal during the closed window t1 immediately
switches NRES to low.
Figure 3-8. Timing Sequence with RWD_OSC = 51 kΩ

VCC
Undervoltage Reset Watchdog Reset

treset = 4 ms tnres = 4 ms
NRES
td = 155 ms t1 t2
t1 = 20.6 ms t2 = 21 ms
twd
NTRIG
ttrig > 200 ns
18 ATA6612/ATA6613
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3.3.24.2 Worst Case Calculation with RWO_OSC = 51 kΩ

The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%.
The worst case calculation for the watchdog period twd is calculated as follows.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum
t2.
t1,min = 0.8 × t1 = 16.5 ms, t1,max = 1.2 × t1 = 24.8 ms
t2,min = 0.8 × t2 = 17.3 ms, t2,max = 1.2 × t2 = 26 ms
twdmax = t1min + t2min = 16.5 ms + 17.3 ms = 33.8 ms
twdmin = t1max = 24.8 ms
twd = 29.3 ms ±4.5 ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs
correctly.
Table 3-2. Typical Watchdog Timings

Oscillator Lead Closed Trigger Period from
RWD_OSC Period Time Window Open Window Microcontroller Reset Time
kΩ tosc/µs td/ms t1/ms t2/ms twd/ms tnres/ms
34 13.3 105 14.0 14.7 19.9 4
51 19.61 154.8 20.64 21.67 29.32 4
91 33.54 264.80 35.32 37.06 50.14 4
120 42.84 338.22 45.11 47.34 64.05 4
19
9111E–AUTO–07/08
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Min. Typ. Max. Unit
Supply voltage VS VS –0.3 +40 V
Pulse time ≤ 500 ms
Ta = 25°C VS +40 V
Output current IVCC ≤ 50 mA
Pulse time ≤ 2 min
Ta = 25°C VS 27 V
Output current IVCC ≤ 50 mA
WAKE (with 33 kΩ serial resistor)
KL_15 (with 50 kΩ/100 nF)
DC voltage –1 +40 V
Transient voltage due to ISO7637 –150 +100 V
(coupling 1 nF)
INH
- DC voltage –0.3 +40 V
LIN
- DC voltage –27 +40 V
Logic pins (RxD, TxD, EN, NRES, NTRIG,
V
WD_OSC, MODE, TM) –0.3 +5.5
Output current NRES INRES +2 mA
PVCC DC voltage –0.3 +5.5 V
VCC DC voltage –0.3 +6.5 V
According to IBEE LIN EMC
Test Spec. 1.0 following IEC 61000-4-2
- Pin VS, LIN to GND ±6 KV
- Pin WAKE (33 kΩ serial resistor and ±6 KV
10 nF to GND)
ESD HBM following STM5.1 with 1.5 kΩ
150 pF ±8 KV
- Pin VS, LIN, WAKE to GND
Junction temperature Tj –40 +150 °C
Storage temperature Ts –55 +150 °C
Thermal shutdown of VCC regulator 150 165 170 °C
Thermal shutdown of LIN output 150 165 170 °C
Thermal shutdown hysteresis 10 °C
20 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
5. Electrical Characteristics
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 VS Pin
Nominal DC voltage
1.1 VS VS 5 27 V A
range
Sleep Mode
VLIN > VS – 0.5V VS IVSsleep 3 10 14 µA A
Supply current in Sleep VS < 14V (Tj = 25°C)
1.2
Mode Sleep Mode
VLIN > VSt – 0.5V IVSsleep 5 11 16 µA A
VS < 14V (Tj = 125°C)
Bus recessive
VS < 14V (Tj = 25°C) IVSsi 47 57 67 µA A
Supply current in Silent Without load at VCC
1.3
Mode Bus recessive
VS < 14V (Tj = 125°C) IVSsi 56 66 76 µA A
Without load at VCC
Bus recessive
Supply current in Normal
1.4 VS < 14V VS IVSrec 0.3 0.8 mA A
Mode
Without load at VCC
Bus dominant
Supply current in Normal
1.5 VS < 14V VS IVSdom 50 53 mA A
Mode
VCC load current 50 mA
Bus recessive
Supply current in
1.6 VS < 14V VS IVSfail 0.35 0.53 mA A
Fail-safe Mode
Without load at VCC
VS undervoltage
1.7 VS VSth 4.0 4.5 5 V A
threshold
VS undervoltage
1.8 VS VSth_hys 0.2 V A
threshold hysteresis
2 RXD Output Pin
Normal Mode
2.1 Low-level input current VLIN = 0V RXD IRXD 1.3 2.5 8 mA A
VRXD = 0.4V
2.2 Low-level output voltage IRXD = 1 mA RXD VRXDL 0.4 V A
Internal 5 kΩ resistor to
2.3 RXD RRXD 3 5 7 kΩ A
VCC
3 TXD Input/Output Pin
3.1 Low-level voltage input TXD VTXDL –0.3 +0.8 V A
VCC +
3.2 High-level voltage input TXD VTXDH 2 V A
0.3V
3.3 Pull-up resistor VTXD = 0V TXD RTXD 125 250 400 kΩ A
High-level leakage
3.4 VTXD = VCC TXD ITXD –3 +3 µA A
current
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
21
9111E–AUTO–07/08
5. Electrical Characteristics (Continued)
Fail-safe Mode
Low-level input current at VLIN = VS
3.5 TXD ITXDwake 2 2.5 8 mA A
local wake-up request VWAKE = 0V
VTXD = 0.4V
4 EN Input Pin
4.1 Low-level voltage input EN VENL –0.3 +0.8 V A
VCC +
4.2 High-level voltage input EN VENH 2 V A
0.3V
4.3 Pull-down resistor VEN = VCC EN REN 50 125 200 kΩ A
4.4 Low-level input current VEN = 0V EN IEN –3 +3 µA A
5 NTRIG Watchdog Input Pin
5.1 Low-level voltage input VNTRIGL –0.3 +0.8 V A
VCC +
5.2 High-level voltage input VNTRIGH 2 V A
0.3V
5.3 Pull-up resistor VNTRIG = 0V RNTRIG 125 250 400 kΩ A
High-level leakage
5.4 VNTRIG = VCC INTRIG –3 +3 µA A
current
6 Mode Input Pin
6.1 Low-level voltage input VMODEL –0.3 +0.8 V A
VCC +
6.2 High-level voltage input VMODEH 2 V A
0.3V
High-level leakage VMODE = VCC or
6.3 IMODE –3 +3 µA A
current VMODE = 0V
7 INH Output Pin
7.1 High-level voltage IINH = –15 mA VINHH VS – 0.8 VS V A
Switch-on resistance
7.2 RINH 30 50 Ω A
between VS and INH
High-level leakage Sleep Mode
7.3 IINHL –3 +3 µA A
current VINH = 27V, VS = 27V
LIN Bus Driver: Bus Load Conditions:
8 Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF
10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps
Driver recessive output
8.1 Load1/Load2 LIN VBUSrec 0.9 × VS VS V A
voltage
VVS = 7V
8.2 Driver dominant voltage LIN V_LoSUP 1.2 V A
Rload = 500 Ω
VVS = 18V
8.3 Driver dominant voltage LIN V_HiSUP 2 V A
Rload = 500 Ω
VVS = 7.0V
8.4 Driver dominant voltage LIN V_LoSUP_1k 0.6 V A
Rload = 1000 Ω
VVS = 18V
8.5 Driver dominant voltage LIN V_HiSUP_1k 0.8 V A
Rload = 1000 Ω
The serial diode is
8.6 Pull-up resistor to VS LIN RLIN 20 30 60 kΩ A
mandatory
22 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613

LIN current limitation
8.7 LIN IBUS_LIM 40 120 200 mA A
VBUS = VBatt_max
Input leakage current at Input leakage current
the receiver including Driver off
8.8 LIN IBUS_PAS_dom –1 –0.35 mA A
pull-up resistor as VBUS = 0V
specified VBatt = 12V
Driver off
Leakage current LIN 8V < VBatt < 18V
8.9 LIN IBUS_PAS_rec 15 20 µA A
recessive 8V < VBUS < 18V
VBUS ≥ VBatt
Leakage current when
control unit disconnected
from ground. GNDDevice = VS
8.10 Loss of local ground VBatt = 12V LIN IBUS_NO_gnd –10 +0.5 +10 µA A
must not affect 0V < VBUS < 18V
communication in the
residual network.
Node has to sustain the
current that can flow VBatt disconnected
8.11 under this condition. Bus VSUP_Device = GND LIN IBUS 0.1 2 µA A
must remain operational 0V < VBUS < 18V
under this condition.
9 LIN Bus Receiver
Center of receiver VBUS_CNT = 0.475 × 0.5 × 0.525 ×
9.1 LIN VBUS_CNT V A
threshold (Vth_dom + Vth_rec)/2 VS VS VS
9.2 Receiver dominant state VEN = 5V LIN VBUSdom 0.4 × VS V A
9.3 Receiver recessive state VEN = 5V LIN VBUSrec 0.6 × VS V A
Receiver input 0.028 × 0.175 ×
9.4 Vhys = Vth_rec – Vth_dom LIN VBUShys 0.1 × VS V A
hysteresis VS VS
Pre_Wake detection LIN VS +
9.5 LIN VLINH VS – 1V V A
High-level input voltage 0.3V
Pre_Wake detection LIN VS –
9.6 Activates the LIN receiver LIN VLINL –27 V A
Low-level input voltage 3.3V
10 Internal Timers
Dominant time for
10.1 VLIN = 0V tbus 30 90 150 µs A
wake-up via LIN bus
Time delay for mode
change from Fail-safe
10.2 VEN = 5V tnorm 5 15 20 µs A
into Normal Mode via
EN pin
Time delay for mode
change from Normal
10.3 V = 0V tsleep 2 7 12 µs A
Mode to Sleep Mode via EN
EN pin
TXD dominant time-out
10.4 V = 0V tdom 6 13 20 ms A
timer (ATA6626 disabled) TXD
23
9111E–AUTO–07/08
Time delay for mode
change from Silent
10.5 V = 5V ts_n 5 15 40 µs A
Mode into Normal Mode EN
via EN
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
10.6 Duty cycle 1 VS = 7.0V to 18V D1 0.396 A
tBit = 50 µs
D1 = tbus_rec(min)/(2 × tBit)
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
tBit = 50 µs
D2 = tbus_rec(max)/(2 × tBit)
THRec(max) = 0.778 × VS
THDom(max) = 0.616 × VS
tBit = 96 µs
D3 = tbus_rec(min)/(2 × tBit)
THRec(min) = 0.389 × VS
THDom(min) = 0.251 × VS
tBit = 96 µs
D4 = tbus_rec(max)/(2 × tBit)
VS = 7.0V to 18V Slope
Slope time falling and tSLOPE_fall
10.10 time dominant and 3.5 22.5 µs A
rising edge at LIN tSLOPE_rise
recessive edges
Receiver Electrical AC Parameters of the LIN Physical Layer
11
LIN Receiver, RXD Load Conditions (CRXD): 20 pF
Propagation delay of
VS = 7.0V to 18V
11.1 receiver (Figure 5-1 on trx_pd 6 µs A
trx_pd = max(trx_pdr, trx_pdf)
page 27)
Symmetry of receiver
VS = 7.0V to 18V
11.2 propagation delay rising trx_sym –2 +2 µs A
t =t –t
edge minus falling edge rx_sym rx_pdr rx_pdf
12 NRES Open Drain Output Pin
VS ≥ 5.5V
12.1 Low-level output voltage Inres = 1 mA VNRESL 0.2 V A
Inres = 250 µA 0.14 V
10 kΩ to VCC
12.2 Low-level output low VNRESLL 0.2 V A
VCC = 0V
VVS ≥ 5.5V
12.3 Undervoltage reset time Treset 2 4 6 ms A
CNRES = 20 pF
Reset debounce time for VVS ≥ 5.5V
12.4 Tres_f 1.5 10 µs A
falling edge CNRES = 20 pF
24 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613

13 Watchdog Oscillator
Voltage at WD_OSC in IWD_OSC = –200 µA
13.1 VWD_OSC 1.13 1.23 1.33 V A
Normal Mode VVS ≥ 4V
Positive values of
13.2 ROSC 34 120 kΩ A
resistor
13.3 Oscillator period ROSC = 34 kΩ tOSC 10.65 13.3 15.97 µs A
14 Watchdog Timing Relative to tOSC
Watchdog lead time after
14.1 td 7895 cycles A
Reset
Watchdog closed
14.2 t1 1053 cycles A
window
14.3 Watchdog open window t2 1105 cycles A
Watchdog reset time
14.4 tnres 3.2 4 4.8 ms A
NRES
15 KL_15 Pin
High-level input voltage Positive edge initializes a VS +
15.1 VKL_15H 4 V A
RV = 50 kΩ wake-up 0.3V
Low-level input voltage
15.2 VKL_15L –1 +2 V A
RV = 50 kΩ
VS < 27V
15.3 KL_15 pull-down current IKL_15 50 60 µA A
VKL_15 = 27V
15.4 Internal debounce time Without external capacitor TdbKL_15 80 160 250 µs A
KL_15 wake-up time
15.5 R = 50 kΩ, C = 100 nF TwKL_15 0.4 2 4.5 ms C
(RV = 50 kΩ, C = 100 nF) V
16 WAKE Pin
VS +
16.1 High-level input voltage VWAKEH VS – 1V V A
0.3V
VS –
16.2 Low-level input voltage Initializes a wake-up signal VWAKEL –1 V A
3.3V
VS < 27V
16.3 WAKE pull-up current IWAKE –30 –10 µA A
VWAKE = 0V
High-level leakage VS = 27V
16.4 IWAKEL –5 +5 µA A
current VWAKE = 27V
Time of low pulse for
16.5 VWAKE = 0V IWAKEL 30 70 150 µs A
wake-up via WAKE pin
25
9111E–AUTO–07/08
18 VCC Voltage Regulator
5.5V < VS < 18V
18.1 Output voltage VCC VCCnor 4.9 5.1 V A
(0 mA to 50 mA)
Output voltage VCC at
18.2 4V < VS < 5.5V VCClow VS – VD 5.1 V A
low VS
VS > 4V
18.3 Regulator drop voltage VD1 250 mV A
IVCC = –20 mA
VS > 4V
18.4 Regulator drop voltage VD2 400 600 mV A
IVCC = –50 mA
VS > 3.3V
18.5 Regulator drop voltage VD3 200 mV A
IVCC = –15 mA
18.6 Line regulation 5.5V < VS < 18V VCCline 1 % A
5 mA < IVCC < 50 mA
18.7 Load regulation VCCload 0.5 2 % A
100 kHz
18.8 Output current limitation VS > 5.5V IVCCs –200 –130 mA A
18.9 Load capacity 1Ω < ESR < 5Ω VthunN 1.8 10 µF D
VCC undervoltage Referred to VCC
18.10 VthunN 4.2 4.8 V A
threshold VS > 5.5V
Hysteresis of Referred to VCC
18.11 Vhysthun 250 mV A
undervoltage threshold VS > 5.5V
Ramp-up time VS > 5.5V CVCC = 2.2 µF
18.12 tVCC 130 300 µs A
to VCC = 5V Iload = –5 mA at VCC
26 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 5-1. Definition of Bus Timing Parameters

tBit tBit tBit
TXD
(Input to transmitting node)
tBus_dom(max) tBus_rec(min)
Thresholds of
THRec(max)
receiving node1
VS THDom(max)
(Transceiver supply
of transmitting node) LIN Bus Signal
Thresholds of
THRec(min) receiving node2
THDom(min)
tBus_dom(min) tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1) trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2) trx_pdf(2)
27
9111E–AUTO–07/08
6. Microcontroller Block
6.1 Features
• High Performance, Low Power AVR 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Register
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 8/16 Kbytes of In-System Self-programmable Flash (ATA6612/ATA6613)
Endurance: 75,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1 Kbyte Internal SRAM
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
• I/O
– 23 Programmable I/O Lines
• Operating Voltage
– 2.7V to 5.5V
• Speed Grade
– 0 to 8 MHz at 2.7V to 5.5V, 0 to 16 MHz at 4.5V to 5.5V
• Low Power Consumption
– Active Mode:
• 4 MHz, 3.0V: 1.8 mA
– Power-down Mode:
• 5 µA at 3.0V
28 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
6.2 Overview
The ATA6612/ATA6613 uses a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATA6612/ATA6613 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
6.2.1 Block Diagram
Figure 6-1. Block Diagram

GND VCC
Watchdog debugWIRE
Timer
Power Supervision
POR / BOD and
Reset
Watchdog Program
Oscillator Logic
Flash SRAM
Oscillator Circuits /
Clock Generation
AVR CPU
EEPROM
AVCC
AREF
GND
2
8 bit T/C 0 16 bit T/C 1 A/D Converter
DATABUS
Analog Internal 6
8 bit T/C 2 Compensation Bandgap
USART 0 SPI TWI
Port D (8) Port B (8) Port C (7)
RESET
XTAL[1..2]
PD[0..7] PB[0..7] PC[0..6] ADC[6..7]
29
9111E–AUTO–07/08
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATA6612/ATA6613 provides the following features: 8K/16K bytes of In-System Program-
mable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM,
23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Coun-
ters with compare modes, internal and external interrupts, a serial programmable USART, a
byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in
TQFP and QFN packages), a programmable Watchdog Timer with internal Oscillator, and five
software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to con-
tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O mod-
ules except asynchronous timer and ADC, to minimize switching noise during ADC conversions.
In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleep-
ing. This allows very fast start-up combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATA6612/ATA6613 uses a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATA6612/ATA6613 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-
lator, and Evaluation kits.
6.2.2 Automotive Quality Grade

The ATA6612 and ATA6613 have been developed and manufactured according to the most
stringent requirements of the international standard ISO-TS-16949 grade 1. This data sheet con-
tains limit values extracted from the results of extensive characterization (Temperature and
Voltage). The quality and reliability of the ATA6612 and ATA6613 have been verified during reg-
ular product qualification as per AEC-Q100.
30 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
6.2.3 Comparison Between ATA6612/ATA6613

The ATA6612 and ATA6613 differ only in memory sizes, boot loader support, and interrupt vec-
tor sizes. Table 6-1 summarizes the different memory and interrupt vector sizes for the two
devices.
Table 6-1. Memory Size Summary

Device Flash EEPROM RAM Interrupt Vector Size
ATA6612 8 Kbytes 512 Bytes 1 Kbyte 1 instruction word/vector
ATA6613 16 Kbytes 512 Bytes 1 Kbyte 2 instruction words/vector
ATA6612 and ATA6613 support a real Read-While-Write Self-Programming mechanism. There

is a separate Boot Loader Section, and the SPM instruction can only execute from there.
6.2.4 Pin Descriptions
6.2.4.1 VCC
Digital supply voltage.
6.2.4.2 GND
Ground.
6.2.4.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscil-
lator amplifier.
Depending on the clock selection fuse settings, PB7 can be used as input to the inverting oscil-
lator amplifier.
If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1
input for the asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
97 and “System Clock and Clock Options” on page 51.
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6.2.4.4 Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC5..0 output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
6.2.4.5 PC6/RESET
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 6-3 on page 47. Shorter pulses are not guaranteed
to generate a Reset.
The various special features of Port C are elaborated in “Alternate Functions of Port C” on page
101.
6.2.4.6 Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
The various special features of Port D are elaborated in “Alternate Functions of Port D” on page
104.
6.2.4.7 AVCC
AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. I should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC.
6.2.4.8 AREF
AREF is the analog reference pin for the A/D converter.
6.2.4.9 ADC7:6 (TQFP and QFN Package Only)

In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These
pins are powered from the analog supply and serve as 10-bit ADC channels.
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6.3 About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header file
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
6.4 AVR CPU Core
6.4.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
6.4.2 Architectural Overview
Figure 6-2. Block Diagram of the AVR Architecture

Data Bus 8-bit
Flash Program Status

program counter and control
memory
Interrupt
32 × 8 unit
Instruction general
register purpose
registers SPI
unit
Instruction
decoder Watchdog
timer
Indirect addressing
Direct addressing
ALU
Control lines Analog
comparator
I/O Module 1
DATA I/O Module 2

SRAM
I/O Module n
EEPROM
I/O lines
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In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATA6612/ATA6613 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
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6.4.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
6.4.4 Status Register

The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial
0 0 0 0 0 0 0 0
Value
• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers. If the Global Interrupt
Enable Register is cleared, none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred,
and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the instruc-
tion set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied into T
by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File
by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the “Instruction Set Description” for detailed information.
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• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruc-
tion Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
6.4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 6-3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6-3. AVR CPU General Purpose Working Registers
7 0 Address
R0 0x00
R1 0x01
R2 0x02
...
R13 0x0D
R14 0x0E
General R15 0x0F
Purpose
R16 0x10
Working
Registers R17 0x11
...
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
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Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 6-3 on page 36, each register is also assigned a data memory address,
mapping them directly into the first 32 locations of the user Data Space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in
access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in
the file.
6.4.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 6-4.
Figure 6-4. The X-, Y-, and Z-registers
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
6.4.6 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x0100, preferably RAMEND. The Stack Pointer is decremented by one when data
is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the
return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is
incremented by one when data is popped from the Stack with the POP instruction, and it is incre-
mented by two when data is popped from the Stack with return from subroutine RET or return
from interrupt RETI.
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The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
6.4.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6-5 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-5. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 6-6 on page 39 shows the internal timing concept for the Register File. In a single clock
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
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Figure 6-6. Single Cycle ALU Operation

T1 T2 T3 T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
6.4.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See section “Memory Programming”
on page 300 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 79. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 79 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse (see “Boot Loader Support – Read-While-Write Self-Programming, ATA6612
and ATA6613” on page 284).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
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Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
6.4.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clock cycles the program vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
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6.5 AVR ATA6612/ATA6613 Memories

This section describes the different memories in the ATA6612/ATA6613. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In addition,
the ATA6612/ATA6613 features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
6.5.1 In-System Reprogrammable Flash Program Memory

The ATA6612/ATA6613 contains 8/16 Kbytes On-chip In-System Reprogrammable Flash mem-
ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two sec-
tions, Boot Loader Section and Application Program Section in ATA6612 and ATA6613. See
SELFPRGEN description in section “Store Program Memory Control and Status Register –
SPMCSR” on page 289 for more details.
The Flash memory has an endurance of at least 75,000 write/erase cycles. The
ATA6612/ATA6613 Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K
program memory locations. The operation of Boot Program section and associated Boot Lock
bits for software protection are described in detail in “Boot Loader Support – Read-While-Write
Self-Programming, ATA6612 and ATA6613” on page 284. “Memory Programming” on page 300
contains a detailed description on Flash Programming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 38.
Figure 6-7. Program Memory Map, ATA6612/ATA6613

Program Memory
0x0000
Application Flash Section
0x7FF
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Figure 6-8. Program Memory Map, ATA6612/ATA6613
Program Memory
0x0000
Boot Flash Section

0x0FFF/0x1FFF
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6.5.2 SRAM Data Memory

Figure 6-9 shows how the ATA6612/ATA6613 SRAM Memory is organized.
The ATA6612/ATA6613 is a complex microcontroller with more peripheral units than can be
supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For
the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 768/1280/1280 data memory locations address both the Register File, the I/O mem-
ory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the
Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O
memory, and the next 512/1024/1024 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 512/1024/1024 bytes of internal data SRAM in the ATA6612/ATA6613 are all accessible
through all these addressing modes. The Register File is described in “General Purpose Regis-
ter File” on page 36.
Figure 6-9. Data Memory Map

Data Memory
32 Registers 0x0000 - 0x001F

64 I/O Registers 0x0020 - 0x005F
160 Ext I/O Reg. 0x0060 - 0x00FF
0x0100
Internal SRAM
(512/1024/1024 x 8)
0x02FF/0x04FF/0x04FF
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6.5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 6-10.
Figure 6-10. On-chip Data SRAM Access Cycles

T1 T2 T3
clkCPU
Address Compute Address Address valid
Data
Write
WR
Data
Read
RD
Memory Access Instruction Next Instruction
6.5.3 EEPROM Data Memory

The ATA6612/ATA6613 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
The section “Memory Programming” on page 300 contains a detailed description on EEPROM
Programming in SPI or Parallel Programming mode.
6.5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 6-3 on page 47. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See “Preventing EEPROM Corruption” on page 49 for details on how to avoid problems in
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
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6.5.3.2 The EEPROM Address Register – EEARH and EEARL

Bit 15 14 13 12 11 10 9 8
– – – – – – – EEAR8 EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 X
X X X X X X X X
• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in
the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0
and 255/511/511. The initial value of EEAR is undefined. A proper value must be written
before the EEPROM may be accessed.
6.5.3.3 The EEPROM Data Register – EEDR

Bit 7 6 5 4 3 2 1 0
MSB LSB EEDR
Initial Value 0 0 0 0 0 0 0 0
• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
6.5.3.4 The EEPROM Control Register – EECR

Bit 7 6 5 4 3 2 1 0
– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 X X 0 0 X 0

These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase
the old value and program the new value) or to split the Erase and Write operations in two
different operations.
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The Programming times for the different modes are shown in Table 6-2. While EEPE is set,
any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Table 6-2. EEPROM Mode Bits

Programming
EEPM1 EEPM0 Time Operation
0 0 3.4 ms Erase and Write in one operation (Atomic Operation)
0 1 1.8 ms Erase Only
1 0 1.8 ms Write Only
1 1 – Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writ-
ing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEPE is cleared.
• Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at
the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See
the description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Write Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE,
otherwise no EEPROM write takes place. The following procedure should be followed when
writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SELFPRGEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The soft-
ware must check that the Flash programming is completed before initiating a new EEPROM
write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to pro-
gram the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See
“Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and ATA6613” on
page 284 for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM
is interrupting another EEPROM access, the EEAR or EEDR Register will be modified,
causing the interrupted EEPROM access to fail. It is recommended to have the Global Inter-
rupt Flag cleared during all the steps to avoid these problems.
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When the write access time has elapsed, the EEPE bit is cleared by hardware. The user
software can poll this bit and wait for a zero before writing the next byte. When EEPE has
been set, the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to a logic one to
trigger the EEPROM read. The EEPROM read access takes one instruction, and the
requested data is available immediately. When the EEPROM is read, the CPU is halted for
four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 6-3 lists the typical
programming time for EEPROM access from the CPU.
Table 6-3. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time
EEPROM write
26,368 3.3 ms
(from CPU)
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob-
ally) so that no interrupts will occur during execution of these functions. The examples also
assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
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EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
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EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
6.5.3.5 Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low VCC reset Protection circuit can
be used. If a reset occurs while a write operation is in progress, the write operation will be com-
pleted provided that the power supply voltage is sufficient.
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6.5.4 I/O Memory
The I/O space definition of the ATA6612/ATA6613 is shown in “Register Summary” on page
344.
All ATA6612/ATA6613 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses. The ATA6612/ATA6613 is a
complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared
by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions
will only operate on the specified bit, and can therefore be used on registers containing such
Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and
peripherals control registers are explained in later sections.
6.5.4.1 General Purpose I/O Registers

The ATA6612/ATA6613 contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and
Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
6.5.4.2 General Purpose I/O Register 2 – GPIOR2

Bit 7 6 5 4 3 2 1 0
MSB LSB GPIOR2

Bit 7 6 5 4 3 2 1 0
MSB LSB GPIOR1

Bit 7 6 5 4 3 2 1 0
MSB LSB GPIOR0
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6.6 System Clock and Clock Options
6.6.1 Clock Systems and their Distribution

Figure 6-11 presents the principal clock systems in the AVR and their distribution. All of the
clocks need not be active at a given time. In order to reduce power consumption, the clocks to
modules not being used can be halted by using different sleep modes, as described in “Power
Management and Sleep Modes” on page 62. The clock systems are detailed below.
Figure 6-11. Clock Distribution

Asynchronous General I/O Flash and
ADC CPU Core RAM
Timer/Counter Modules EEPROM
clkADC
clkI/O AVR Clock clkCPU

Control Unit
clkASY clkFLASH
System Clock Reset Logic Watchdog Timer

Prescaler
Source clock Watchdog clock
Clock Watchdog
Multiplexer Oscillator
Timer/Counter Crystal Low-frequency Calibrated RC

External Clock
Oscillator Oscillator Crystal Oscillator Oscillator
6.6.1.1 CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
6.6.1.2 I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that start condition detection in the USI module is carried out asynchro-
nously when clkI/O is halted, TWI address recognition in all sleep modes.
6.6.1.3 Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
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6.6.1.4 Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
6.6.1.5 ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
6.6.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-4. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0
Low Power Crystal Oscillator 1111 - 1000
Full Swing Crystal Oscillator 0111 - 0110
Low Frequency Crystal Oscillator 0101 - 0100
Internal 128 kHz RC Oscillator 0011
Calibrated Internal RC Oscillator 0010
External Clock 0000
Reserved 0001
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
6.6.2.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that
all users can make their desired clock source setting using any available programming interface.
6.6.2.2 Clock Startup Sequence

Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. The section “System Control and Reset”
on page 68 describes the start conditions for the internal reset. The delay (tTOUT) is timed from
the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx
fuse bits. The selectable delays are shown in Table 6-5 on page 53. The frequency of the
Watchdog Oscillator is voltage dependent as shown in “Register Summary” on page 344.
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Table 6-5. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
0 ms 0 ms 0
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The
delay will not monitor the actual voltage and it will be required to select a delay longer than the
VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be
used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the time-out delay
can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is
not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute. The recommended oscillator start-up time is dependent on the clock type, and
varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-save or Power-down mode, VCC is
assumed to be at a sufficient level and only the start-up time is included.
6.6.3 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip Oscillator, as shown in Figure 6-12. Either a quartz crystal or a
ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out-
put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and
may be more susceptible to noise in noisy environments. In these cases, refer to the “Full Swing
Crystal Oscillator” on page 55.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 6-6 on page 54. For ceramic resonators, the capacitor val-
ues given by the manufacturer should be used.
Figure 6-12. Crystal Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
The Low Power Oscillator can operate in three different modes, each optimized for a specific fre-
quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-6
on page 54.
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Table 6-6. Low Power Crystal Oscillator Operating Modes(3)
Recommended Range for Capacitors C1
Frequency Range(1) (MHz) CKSEL3..1 and C2 (pF)
0.4 - 0.9 100(2) –
0.9 - 3.0 101 12 - 22
3.0 - 8.0 110 12 - 22
8.0 - 16.0 111 12 - 22
Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8
Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured
that the resulting divided clock meets the frequency specification of the device.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
6-7.
Table 6-7. Start-up Times for the Low Power Crystal Oscillator Clock Selection
Start-up Time from Additional Delay
Oscillator Source/ Power-down and from Reset
Power Conditions Power-save (VCC = 5.0V) CKSEL0 SUT1..0
Ceramic resonator, fast
258 CK 14CK + 4.1 ms(1) 0 00
rising power
Ceramic resonator, slowly
258 CK 14CK + 65 ms(1) 0 01
rising power
Ceramic resonator, BOD
1K CK 14CK(2) 0 10
enabled
1K CK 14CK + 4.1 ms(2) 0 11
rising power
1K CK 14CK + 65 ms(2) 1 00
rising power
Crystal Oscillator, BOD
16K CK 14CK 1 01
enabled
Crystal Oscillator, fast
16K CK 14CK + 4.1 ms 1 10
rising power
Crystal Oscillator, slowly
16K CK 14CK + 65 ms 1 11
rising power
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
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6.6.4 Full Swing Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip Oscillator, as shown in Figure 6-12 on page 53. Either a quartz
crystal or a ceramic resonator may be used.
This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is
useful for driving other clock inputs and in noisy environments. The current consumption is
higher than the “Low Power Crystal Oscillator” on page 53. Note that the Full Swing Crystal
Oscillator will only operate for VCC = 2.7 - 5.5V.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 6-9 on page 56. For ceramic resonators, the capacitor val-
ues given by the manufacturer should be used.
The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-8.
Table 6-8. Full Swing Crystal Oscillator Operating Modes(2)

0.4 - 20 011 12 - 22
Figure 6-13. Crystal Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
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Table 6-9. Start-up Times for the Full Swing Crystal Oscillator Clock Selection
Oscillator Source/ Power-down and from Reset
258 CK 14CK + 4.1 ms(1) 0 00
rising power
258 CK 14CK + 65 ms(1) 0 01
rising power
Ceramic resonator, BOD
1K CK 14CK(2) 0 10
enabled
1K CK 14CK + 4.1 ms(2) 0 11
rising power
1K CK 14CK + 65 ms(2) 1 00
rising power
Crystal Oscillator, BOD
16K CK 14CK 1 01
enabled
Crystal Oscillator, fast
16K CK 14CK + 4.1 ms 1 10
rising power
Crystal Oscillator, slowly
16K CK 14CK + 65 ms 1 11
rising power
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
6.6.5 Low Frequency Crystal Oscillator

The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Fre-
quency Crystal Oscillator. The crystal should be connected as shown in Figure 6-12 on page 53.
When this Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0
as shown in Table 6-10.
Table 6-10. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Power-down and from Reset
(1)
BOD enabled 1K CK 14CK 0 00
(1)
Fast rising power 1K CK 14CK + 4.1 ms 0 01
Slowly rising power 1K CK 14CK + 65 ms(1) 0 10
Reserved 0 11
BOD enabled 32K CK 14CK 1 00
Fast rising power 32K CK 14CK + 4.1 ms 1 01
Slowly rising power 32K CK 14CK + 65 ms 1 10
Reserved 1 11
Note: 1. These options should only be used if frequency stability at start-up is not important for the
application.
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6.6.6 Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nom-
inal value at 5V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See
“System Clock Prescaler” on page 60 for more details. This clock may be selected as the system
clock by programming the CKSEL Fuses as shown in Table 6-11. If selected, it will operate with
no external components. During reset, hardware loads the calibration byte into the OSCCAL
Register and thereby automatically calibrates the RC Oscillator. At 5V and 25° C, this calibration
gives a frequency of 8 MHz ± 1%. The tolerance of the internal RC oscillator remains better than
±10% within the whole automotive temperature and voltage ranges (4.5V to 5.5V, –40°C to
+125°C). The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within
±1% accuracy, by changing the OSCCAL register. When this Oscillator is used as the chip
clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset
Time-out. For more information on the pre-programmed calibration value (see “Calibration Byte”
on page 304).
Table 6-11. Internal Calibrated RC Oscillator Operating Modes(1)(3)

Frequency Range(2) (MHz) CKSEL3..0
7.3 - 8.1 0010
Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.
Fuse can be programmed in order to divide the internal frequency by 8.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-12.
Table 6-12. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Time from Additional Delay from
Power Conditions Power-down and Power-save Reset (VCC = 5.0V) SUT1..0
(1)
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1 ms 01
(2)
Slowly rising power 6 CK 14CK + 65 ms 10
Reserved 11
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1 ms to ensure programming mode can be entered.
2. The device is shipped with this option selected.
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6.6.6.1 Oscillator Calibration Register – OSCCAL
Bit 7 6 5 4 3 2 1 0
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Initial Value Device Specific Calibration Value
• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. The factory-calibrated value is
automatically written to this register during chip reset, giving an oscillator frequency of
8.0 MHz at 25°C. The application software can write this register to change the oscillator fre-
quency. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within
±1% accuracy. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to
more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives
the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two
frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a
higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency
in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in
the frequency range 7.3 - 8.1 MHz.
6.6.7 128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25° C. This clock may be select as the system clock by
programming the CKSEL Fuses to “11” as shown in Table 6-13.
Table 6-13. 128 kHz Internal Oscillator Operating Modes

Nominal Frequency CKSEL3..0
128 kHz 0011
Note: 1. The frequency is preliminary value. Actual value is TBD.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-14 on page 59.
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Table 6-14. Start-up Times for the 128 kHz Internal Oscillator
Power Conditions Power-down and Power-save Reset SUT1..0
(1)
Fast rising power 6 CK 14CK + 4 ms 01
Reserved 11
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1 ms to ensure programming mode can be entered.
6.6.8 External Clock

The device can utilize a external clock source as shown in Figure 6-14. To run the device on an
external clock, the CKSEL Fuses must be programmed as shown in Table 6-15.
Table 6-15. Full Swing Crystal Oscillator Operating Modes(2)

0 - 100 0000 12 - 22
Figure 6-14. External Clock Drive Configuration
NC XTAL2
EXTERNAL
CLOCK XTAL1
SIGNAL
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-16.
Table 6-16. Start-up Times for the External Clock Selection

Power Conditions Power-down and Power-save Reset (VCC = 5.0V) SUT1..0
Fast rising power 6 CK 14CK + 4.1 ms 01
Reserved 11
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When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
60 for details.
6.6.9 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
6.6.10 Timer/Counter Oscillator

The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-
nal clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with
XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when an
internal RC Oscillator is selected as system clock source. See Figure 6-12 on page 53 for crystal
connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to
logic one. See “Asynchronous operation of the Timer/Counter” on page 180 for further descrip-
tion on selecting external clock as input instead of a 32 kHz crystal.
6.6.11 System Clock Prescaler

The ATA6612/ATA6613 has a system clock prescaler, and the system clock can be divided by
setting the “Clock Prescale Register – CLKPR” on page 617. This feature can be used to
decrease the system clock frequency and the power consumption when the requirement for pro-
cessing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are
divided by a factor as shown in Table 6-20 on page 70.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
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To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
6.6.11.1 Clock Prescale Register – CLKPR

Bit 7 6 5 4 3 2 1 0
CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are writ-
ten. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out
period, nor clear the CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The division
factors are given in Table 6-17 on page 62.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-
grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are
reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the
selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. Note that any value can be written to the CLKPS bits
regardless of the CKDIV8 Fuse setting. The Application software must ensure that a suffi-
cient division factor is chosen if the selected clock source has a higher frequency than the
maximum frequency of the device at the present operating conditions. The device is shipped
with the CKDIV8 Fuse programmed.
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Table 6-17. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0 0 0 0 1
0 0 0 1 2
0 0 1 0 4
0 0 1 1 8
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
6.7 Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See Table 6-18 on page 63 for a summary. If an enabled
interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted
for four cycles in addition to the start-up time, executes the interrupt routine, and resumes exe-
cution from the instruction following SLEEP. The contents of the Register File and SRAM are
unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU
wakes up and executes from the Reset Vector.
Figure 6-11 on page 51 presents the different clock systems in the ATA6612/ATA6613, and their
distribution. The figure is helpful in selecting an appropriate sleep mode.
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6.7.1 Sleep Mode Control Register – SMCR

The Sleep Mode Control Register contains control bits for power management.
Bit 7 6 5 4 3 2 1 0
– – – – SM2 SM1 SM0 SE SMCR
Read/Write R R R R R/W R/W R/W R/W
• Bits 7..4 Res: Reserved Bits

These bits are unused bits in the ATA6612/ATA6613, and will always read as zero.
• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 6-18.
Table 6-18. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 ADC Noise Reduction
0 1 0 Power-down
0 1 1 Power-save
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Standby(1)
1 1 1 Reserved
Note: 1. Standby mode is only recommended for use with external crystals or resonators.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the
programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just
before the execution of the SLEEP instruction and to clear it immediately after waking up.
6.7.2 Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
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6.7.3 ADC Noise Reduction Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the
2-wire Serial Interface address watch, Timer/Counter2, and the Watchdog to continue operating
(if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other
clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a
Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0
or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
6.7.4 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts,
the 2-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
Only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a
2-wire Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin
change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks,
allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 108
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in “Clock Sources” on page 52.
6.7.5 Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception.
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from
either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding
Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in
SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save
mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is
stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is
stopped during sleep. Note that even if the synchronous clock is running in Power-save, this
clock is only available for Timer/Counter2.
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6.7.6 Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
Table 6-19. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Wake-up Sources
Source Enabled
Timer Oscillator
SPM/EEPROM
INT1, INT0 and
TWI Address
Pin Change
Main Clock
Other I/O
Enabled
clkFLASH
Timer2
Ready
Match
clkCPU
clkADC
clkASY
WDT
ADC
clkIO
Sleep Mode
Idle X X X X X(2) X X X X X X X
ADC Noise
X X X X(2) X(3) X X X X X
Reduction
Power-down X(3) X X
(3)
Power-save X X X X X X
(1) (3)
Standby X X X X
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT1 and INT0, only level interrupt.
6.7.7 Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-
als to reduce power consumption. The current state of the peripheral is frozen and the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. See “Power-down Supply Current” on page 330 for examples. In all other
sleep modes, the clock is already stopped.
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6.7.7.1 Power Reduction Register - PRR
Bit 7 6 5 4 3 2 1 0
PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC PRR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
• Bit 6 - PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode
(AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the
shutdown.
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the
Timer/Counter0 is enabled, operation will continue like before the shutdown.
• Bit 4 - Res: Reserved bit
This bit is reserved in ATA6612/ATA6613 and will always read as zero.
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the
Timer/Counter1 is enabled, operation will continue like before the shutdown.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock
to the module. When waking up the SPI again, the SPI should be re initialized to ensure
proper operation.
• Bit 1 - PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module.
When waking up the USART again, the USART should be re initialized to ensure proper
operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut
down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
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6.7.8 Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an
AVR controlled system. In general, sleep modes should be used as much as possible, and the
sleep mode should be selected so that as few as possible of the device’s functions are operat-
ing. All functions not needed should be disabled. In particular, the following modules may need
special consideration when trying to achieve the lowest possible power consumption.
6.7.8.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 265
for details on ADC operation.
6.7.8.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep
mode. Refer to “Analog Comparator” on page 262 for details on how to configure the Analog
Comparator.
6.7.8.3 Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
nificantly to the total current consumption. Refer to “Brown-out Detection” on page 71 for details
on how to configure the Brown-out Detector.
6.7.8.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 73 for details on the start-up time.
6.7.8.5 Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to “Watchdog Timer” on page 74 for details on how to configure the Watchdog Timer.
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6.7.8.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 94 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to VCC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page 264 and “Digital Input Dis-
able Register 0 – DIDR0” on page 281 for details.
6.7.8.7 On-chip Debug System

If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
6.8 System Control and Reset
6.8.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. For the ATA6613, the instruction placed at the Reset Vector must be a
JMP – Absolute Jump – instruction to the reset handling routine. For the ATA6612, the instruc-
tion placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset
handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not
used, and regular program code can be placed at these locations. This is also the case if the
Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or
vice versa (ATA6612/ATA6613 only). The circuit diagram in Figure 6-15 on page 69 shows the
reset logic. Table 6-20 on page 70 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in “Clock Sources” on page 52.
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6.8.2 Reset Sources

The ATA6612/ATA6613 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minimum pulse length.
• Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog System Reset mode is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out
Reset threshold (VBOT) and the Brown-out Detector is enabled.
Figure 6-15. Reset Logic

DATA BUS
MCU Status
Register (MCUSR)
PORF
BORF
EXTRF
WDRF
VCC
Power-on Reset
Circuit
Brown-out
BODLEVEL [2..0] Reset Circuit
INTERNAL RESET
Pull-up Resistor
Reset Q
Circuit S
R
COUNTER RESET
SPIKE
RESET FILTER Watchdog
Timer
RSTDISBL
Watchdog
Oscillator
Clock CK Delay Counters

Generator TIMEOUT
CKSEL[3:0]
SUT[1:0]
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6.8.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 6-20. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 6-16. MCU Start-up, RESET Tied to VCC

V CCRR
VCC
VPORMAX
VPORMIN
RESET
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 6-17. MCU Start-up, RESET Extended Externally
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
Table 6-20. Power-on Reset Characteristics

Symbol Parameter Condition Min Typ Max Units
Power-on Reset Threshold Voltage (rising) 1.0 1.4 V
VPOT (1)
Power-on Reset Threshold Voltage (falling) 0.9 1.3 V
VPORMAX VCC Max. start voltage to ensure internal Power-on Reset signal 0.4 V
VPORMIN VCC Min. start voltage to ensure internal Power-on Reset signal -0.1 V
VCCRR VCC Rise Rate to ensure Power-on Reset 0.01 V/ms
VRST RESET Pin Threshold Voltage 0.1 VCC 0.9 VCC V
Note: 1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a Reset.
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6.8.4 External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 6-20 on page 70) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the
MCU after the Time-out period – tTOUT – has expired. The External Reset can be disabled by the
RSTDISBL fuse, see Table 6-117 on page 302.
Figure 6-18. External Reset During Operation

VCC
RESET
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
6.8.5 Brown-out Detection

ATA6612/ATA6613 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can
be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ =
VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
Table 6-21. BODLEVEL Fuse Coding(1)

BODLEVEL 2..0 Fuses Min VBOT Typ VBOT Max VBOT Units
111 BOD Disabled
110 1.8
101 2.7 V
100 4.3
011
010
Reserved
001
000
Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where
this is the case, the device is tested down to VCC = VBOT during the production test. This guar-
antees that a Brown-Out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 110 and BODLEVEL = 101 for ATA6612V/ATA6613V, and BODLEVEL = 101
and BODLEVEL = 101 for ATA6612/ATA6613.
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Table 6-22. Brown-out Characteristics
Symbol Parameter Min Typ Max Units
VHYST Brown-out Detector Hysteresis 50 mV
tBOD Min Pulse Width on Brown-out Reset ns
When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure
6-19), the Brown-out Reset is immediately activated. When VCC increases above the trigger
level (VBOT+ in Figure 6-19), the delay counter starts the MCU after the Time-out period tTOUT has
expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for lon-
ger than tBOD given in Table 6-20 on page 70.
Figure 6-19. Brown-out Reset During Operation
VCC VBOT+
VBOT-
RESET
TIME-OUT tTOUT
INTERNAL
RESET
6.8.6 Watchdog System Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
“Watchdog Timer” on page 74 for details on operation of the Watchdog Timer.
Figure 6-20. Watchdog System Reset During Operation

VCC
RESET
1 CK Cycle
WDT
TIME-OUT
RESET tTOUT
TIME-OUT
INTERNAL
RESET
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6.8.7 MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.
Bit 7 6 5 4 3 2 1 0
– – – – WDRF BORF EXTRF PORF MCUSR
Initial Value 0 0 0 0 See Bit Description
• Bit 7..4: Res: Reserved Bits

• Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writ-
ing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the
flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before
another reset occurs, the source of the reset can be found by examining the Reset Flags.
6.8.8 Internal Voltage Reference

ATA6612/ATA6613 features an internal bandgap reference. This reference is used for
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
6.8.8.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in Table 6-23 on page 74. To save power, the reference is not always
turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuses).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
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Table 6-23. Internal Voltage Reference Characteristics(1)
VBG Bandgap reference voltage TBD 1.0 1.1 1.2 V
tBG Bandgap reference start-up time TBD 40 70 µs
IBG Bandgap reference current consumption TBD 10 TBD µA
Note: 1. Values are guidelines only. Actual values are TBD.
6.8.9 Watchdog Timer

ATA6612/ATA6613 has an Enhanced Watchdog Timer (WDT). The main features are:
• Clocked from separate On-chip Oscillator
• 3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16 ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 6-21. Watchdog Timer
WATCHOG
128kHz PRESCALER
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WATCHDOG WDP2
RESET
WDP3
WDE
MCU RESET
WDIF
INTERRUPT
WDIE
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset
- instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
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In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera-
tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and
changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
desired, but with the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watch-
dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during the execution of these functions.
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Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note: 1. The example code assumes that the part specific header file is included.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition,
the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to han-
dle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the
application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE
control bit in the initialization routine, even if the Watchdog is not in use.
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The following code example shows one assembly and one C function for changing the time-out
value of the Watchdog Timer.

WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed equence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change
in the WDP bits can result in a time-out when switching to a shorter time-out period.
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6.8.9.1 Watchdog Timer Control Register - WDTCSR
Bit 7 6 5 4 3 2 1 0
WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
Initial Value 0 0 0 0 X 0 0 0
• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Inter-
rupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in
Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog
Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out
in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear
WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode).
This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in
Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should how-
ever not be done within the interrupt service routine itself, as this might compromise the
safety-function of the Watchdog System Reset mode. If the interrupt is not executed before
the next time-out, a System Reset will be applied.
Table 6-24. Watchdog Timer Configuration

WDTON WDE WDIE Mode Action on Time-out
0 0 0 Stopped None
0 0 1 Interrupt Mode Interrupt
0 1 0 System Reset Mode Reset
Interrupt and System Reset Interrupt, then go to System
0 1 1
Mode Reset Mode
1 x x System Reset Mode Reset
• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE
bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF
is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets dur-
ing conditions causing failure, and a safe start-up after the failure.
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• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
running. The different prescaling values and their corresponding time-out periods are shown
in Table 6-25.
Table 6-25. Watchdog Timer Prescale Select

Number of WDT Oscillator Typical Time-out at
WDP3 WDP2 WDP1 WDP0 Cycles VCC = 5.0V
0 0 0 0 2K (2048) cycles 16 ms
0 0 0 1 4K (4096) cycles 32 ms
0 0 1 0 8K (8192) cycles 64 ms
0 0 1 1 16K (16384) cycles 0.125 s
0 1 0 0 32K (32768) cycles 0.25 s
0 1 0 1 64K (65536) cycles 0.5 s
0 1 1 0 128K (131072) cycles 1.0 s
0 1 1 1 256K (262144) cycles 2.0 s
1 0 0 0 512K (524288) cycles 4.0 s
1 0 0 1 1024K (1048576) cycles 8.0 s
1 0 1 0
1 0 1 1
1 1 0 0
Reserved
1 1 0 1
1 1 1 0
1 1 1 1
6.9 Interrupts
This section describes the specifics of the interrupt handling as performed in
ATA6612/ATA6613. For a general explanation of the AVR interrupt handling, refer to “Reset and
Interrupt Handling” on page 39.
The interrupt vectors in ATA6612 and ATA6613 are generally the same, with the following
differences:
• Each Interrupt Vector occupies two instruction words in ATA6613, and one instruction word in
ATA6612.
• In ATA6612 and ATA6613, the Reset Vector is affected by the BOOTRST fuse, and the
Interrupt Vector start address is affected by the IVSEL bit in MCUCR.
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6.9.1 Interrupt Vectors in ATA6612
Table 6-26. Reset and Interrupt Vectors in ATA6612

Program
Vector No. Address(2) Source Interrupt Definition
(1)
1 0x000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
2 0x001 INT0 External Interrupt Request 0
4 0x003 PCINT0 Pin Change Interrupt Request 0
7 0x006 WDT Watchdog Time-out Interrupt
8 0x007 TIMER2 COMPA Timer/Counter2 Compare Match A
9 0x008 TIMER2 COMPB Timer/Counter2 Compare Match B
10 0x009 TIMER2 OVF Timer/Counter2 Overflow
11 0x00A TIMER1 CAPT Timer/Counter1 Capture Event
12 0x00B TIMER1 COMPA Timer/Counter1 Compare Match A
13 0x00C TIMER1 COMPB Timer/Coutner1 Compare Match B
14 0x00D TIMER1 OVF Timer/Counter1 Overflow
15 0x00E TIMER0 COMPA Timer/Counter0 Compare Match A
16 0x00F TIMER0 COMPB Timer/Counter0 Compare Match B
18 0x011 SPI, STC SPI Serial Transfer Complete
19 0x012 USART, RX USART Rx Complete
20 0x013 USART, UDRE USART, Data Register Empty
21 0x014 USART, TX USART, Tx Complete
22 0x015 ADC ADC Conversion Complete
23 0x016 EE READY EEPROM Ready
24 0x017 ANALOG COMP Analog Comparator
25 0x018 TWI 2-wire Serial Interface
26 0x019 SPM READY Store Program Memory Ready
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
reset (see “Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and
ATA6613” on page 284).
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Interrupt Vector will then be the address in this table
added to the start address of the Boot Flash Section.
Table 6-27 on page 81 shows reset and Interrupt Vectors placement for the various combina-
tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This
is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in
the Boot section or vice versa.
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Table 6-27. Reset and Interrupt Vectors Placement in ATA6612(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x001
1 1 0x000 Boot Reset Address + 0x001
0 0 Boot Reset Address 0x001
0 1 Boot Reset Address Boot Reset Address + 0x001
Note: 1. The Boot Reset Address is shown in Table 6-107 on page 298. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATA6612 is:
Address Labels Code Comments
0x000 rjmp RESET ; Reset Handler
0x001 rjmp EXT_INT0 ; IRQ0 Handler
0x003 rjmp PCINT0 ; PCINT0 Handler
0x006 rjmp WDT ; Watchdog Timer Handler
0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler
0X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler
0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler
0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler
0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler
0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler
0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler
0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler
0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler
0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler
0x011 rjmp SPI_STC ; SPI Transfer Complete Handler
0x012 rjmp USART_RXC ; USART, RX Complete Handler
0x013 rjmp USART_UDRE ; USART, UDR Empty Handler
0x014 rjmp USART_TXC ; USART, TX Complete Handler
0x015 rjmp ADC ; ADC Conversion Complete Handler
0x016 rjmp EE_RDY ; EEPROM Ready Handler
0x017 rjmp ANA_COMP ; Analog Comparator Handler
0x018 rjmp TWI ; 2-wire Serial Interface Handler
0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
0x01ARESET: ldi r16, high(RAMEND); Main program start
0x01B out SPH,r16 ; Set Stack Pointer to top of RAM
0x01C ldi r16, low(RAMEND)
0x01D out SPL,r16
0x01E sei ; Enable interrupts
0x01F <instr> xxx
... ... ... ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in ATA6612 is:
0x000 RESET: ldi r16,high(RAMEND); Main program start
0x001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x002 ldi r16,low(RAMEND)
0x003 out SPL,r16
0x004 sei ; Enable interrupts
0x005 <instr> xxx
;
.org 0xC01
0xC01 rjmp EXT_INT0 ; IRQ0 Handler
... ... ... ;
0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6612 is:
.org 0x001
... ... ... ;
0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0xC00
0xC00 RESET: ldi r16,high(RAMEND); Main program start
0xC01 out SPH,r16 ; Set Stack Pointer to top of RAM
0xC02 ldi r16,low(RAMEND)
0xC03 out SPL,r16
0xC04 sei ; Enable interrupts
0xC05 <instr> xxx
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATA6612 is:

;
.org 0xC00
0xC00 rjmp RESET ; Reset handler
... ... ... ;
0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
0xC1A RESET: ldi r16,high(RAMEND); Main program start
0xC1B out SPH,r16 ; Set Stack Pointer to top of RAM
0xC1C ldi r16,low(RAMEND)
0xC1D out SPL,r16
0xC1E sei ; Enable interrupts
0xC1F <instr> xxx
6.9.2 Interrupt Vectors in ATA6613
Table 6-28. Reset and Interrupt Vectors in ATA6613

Program
1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
6 0x000A PCINT2 Pin Change Interrupt Request 2
7 0x000C WDT Watchdog Time-out Interrupt
8 0x000E TIMER2 COMPA Timer/Counter2 Compare Match A
9 0x0010 TIMER2 COMPB Timer/Counter2 Compare Match B
11 0x0014 TIMER1 CAPT Timer/Counter1 Capture Event
12 0x0016 TIMER1 COMPA Timer/Counter1 Compare Match A
13 0x0018 TIMER1 COMPB Timer/Coutner1 Compare Match B
14 0x001A TIMER1 OVF Timer/Counter1 Overflow
15 0x001C TIMER0 COMPA Timer/Counter0 Compare Match A
16 0x001E TIMER0 COMPB Timer/Counter0 Compare Match B
18 0x0022 SPI, STC SPI Serial Transfer Complete
19 0x0024 USART, RX USART Rx Complete
20 0x0026 USART, UDRE USART, Data Register Empty
21 0x0028 USART, TX USART, Tx Complete
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Table 6-28. Reset and Interrupt Vectors in ATA6613 (Continued)
Program
22 0x002A ADC ADC Conversion Complete
23 0x002C EE READY EEPROM Ready
24 0x002E ANALOG COMP Analog Comparator
25 0x0030 TWI 2-wire Serial Interface
26 0x0032 SPM READY Store Program Memory Ready
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
reset (see “Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and
ATA6613” on page 284).
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Interrupt Vector will then be the address in this table
added to the start address of the Boot Flash Section.
Table 6-29 shows reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used, and regular program code can be placed at these locations. This is also
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
Table 6-29. Reset and Interrupt Vectors Placement in ATA6613(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x001
1 1 0x000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x001
0 1 Boot Reset Address Boot Reset Address + 0x0002
Note: 1. The Boot Reset Address is shown in Table 6-107 on page 298. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
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The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATA6613 is:
0x0000 jmp RESET ; Reset Handler
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0006 jmp PCINT0 ; PCINT0 Handler
0x0008 jmp PCINT1 ; PCINT1 Handler
0x000A jmp PCINT2 ; PCINT2 Handler
0x000C jmp WDT ; Watchdog Timer Handler
0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler
0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler
0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler
0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler
0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler
0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler
0x001A jmp TIM1_OVF ; Timer1 Overflow Handler
0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler
0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler
0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler
0x0022 jmp SPI_STC ; SPI Transfer Complete Handler
0x0024 jmp USART_RXC ; USART, RX Complete Handler
0x0026 jmp USART_UDRE ; USART, UDR Empty Handler
0x0028 jmp USART_TXC ; USART, TX Complete Handler
0x002A jmp ADC ; ADC Conversion Complete Handler
0x002C jmp EE_RDY ; EEPROM Ready Handler
0x002E jmp ANA_COMP ; Analog Comparator Handler
0x0030 jmp TWI ; 2-wire Serial Interface Handler
0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x0033RESET: ldi r16, high(RAMEND); Main program start
0x0035 ldi r16, low(RAMEND)
0x0036 out SPL,r16
0x0038 <instr> xxx
... ... ... ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in ATA6613 is:
0x0000 RESET: ldi r16,high(RAMEND); Main program start
0x0002 ldi r16,low(RAMEND)
0x0003 out SPL,r16
0x0005 <instr> xxx
;
.org 0xC02
0x1C02 jmp EXT_INT0 ; IRQ0 Handler
... ... ... ;
0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6613 is:
.org 0x0002
... ... ... ;
0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0x1C00
0x1C00 RESET: ldi r16,high(RAMEND); Main program start
0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1C02 ldi r16,low(RAMEND)
0x1C03 out SPL,r16
0x1C04 sei ; Enable interrupts
0x1C05 <instr> xxx
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATA6613 is:
;
.org 0x1C00
0x1C00 jmp RESET ; Reset handler
... ... ... ;
0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x1C33 RESET: ldi r16,high(RAMEND); Main program start
0x1C34 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1C35 ldi r16,low(RAMEND)
0x1C36 out SPL,r16
0x1C37 sei ; Enable interrupts
0x1C38 <instr> xxx
6.9.2.1 Moving Interrupts Between Application and Boot Space, ATA6612 and ATA6613
The MCU Control Register controls the placement of the Interrupt Vector table.
6.9.2.2 MCU Control Register – MCUCR

Bit 7 6 5 4 3 2 1 0
– – – PUD – – IVSEL IVCE MCUCR
Read/Write R R R R/W R R R/W R/W
• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning
of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash
Section is determined by the BOOTSZ Fuses. Refer to section “Boot Loader Support –
Read-While-Write Self-Programming, ATA6612 and ATA6613” on page 284 for details. To
avoid unintentional changes of Interrupt Vector tables, a special write procedure must be fol-
lowed to change the IVSEL bit:
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are dis-
abled in the cycle IVCE is set, and they remain disabled until after the instruction following
the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit
in the Status Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to section “Boot Loader Support –
Read-While-Write Self-Programming, ATA6612 and ATA6613” on page 284 for details on Boot
Lock bits.
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• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared
by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will
disable interrupts, as explained in the IVSEL description above. See Code Example below.
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ldi r16, (1<<IVSEL)
out MCUCR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of Interrupt Vectors */
MCUCR = (1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = (1<<IVSEL);
}
6.10 I/O-Ports
6.10.1 Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 6-22 on page 89. Refer to
“Electrical Characteristics” on page 320 for a complete list of parameters.
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Figure 6-22. I/O Pin Equivalent Schematic
Rpu
Pxn Logic
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
ters and bit locations are listed in “Register Description for I/O Ports” on page 107.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
90. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 95. Refer to the individual module sections for a full description of the alter-
nate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
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6.10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 6-23 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 6-23. General Digital I/O(1)
PUD
Q D
DDxn
QCLR
WDx
RESET
RDx
1
Pxn Q D
DATA BUS
PORTxn 0
QCLR
RESET
WPx
WRx
SLEEP RRx
SYNCHRONIZER
RPx
D Q D Q
PINxn
L Q Q
clk I/O
WDx: WRITE DDRx

PUD: PULLUP DISABLE RDx: READ DDRx
SLEEP: SLEEP CONTROL WRx: WRITE PORTx
clkI/O: I/O CLOCK RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
WPx: WRITE PINx REGISTER
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
6.10.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O Ports” on page 107, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
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6.10.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
6.10.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 6-30 summarizes the control signals for the pin value.
Table 6-30. Port Pin Configurations

PUD
DDxn PORTxn (in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
6.10.2.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 6-23 on page 90, the PINxn Register bit and the preced-
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure 6-24 on
page 92 shows a timing diagram of the synchronization when reading an externally applied pin
value. The maximum and minimum propagation delays are denoted t pd,max and t pd,min
respectively.
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Figure 6-24. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIONS XXX XXX in r17, PINx
SYNC LATCH
PINxn
r17 0x00 0xFF

tpd, max
tpd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 6-25. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 6-25. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16 0xFF
INSTRUCTIONS out PORTx, r16 nop in r17, PINx
SYNC LATCH
PINxn
r17 0x00 0xFF

tpd
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.

...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
Note: 1. For the assembly program, two temporary registers are used to minimize the time from
pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and
3 as low and redefining bits 0 and 1 as strong high drivers.
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6.10.2.5 Digital Input Enable and Sleep Modes
As shown in Figure 6-23 on page 90, the digital input signal can be clamped to ground at the
input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power
consumption if some input signals are left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 95.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
6.10.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, float-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is
accidentally configured as an output.
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6.10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 6-26
shows how the port pin control signals from the simplified Figure 6-23 on page 90 can be over-
ridden by alternate functions. The overriding signals may not be present in all port pins, but the
figure serves as a generic description applicable to all port pins in the AVR microcontroller
family.
Figure 6-26. Alternate Port Functions(1)
PUOExn
PUOVxn
1
0
PUD
DDOExn
DDOVxn
1
0 Q D
DDxn
Q CLR
WDx
PVOExn RESET
RDx
PVOVxn
DATA BUS
1 1
Pxn
0 Q D 0
PORTxn
PTOExn
Q CLR
DIEOExn
WPx
DIEOVxn RESET
1 WRx
RRx
0 SLEEP
SYNCHRONIZER
RPx
D SETQ D Q
PINxn
L CLR Q
CLR Q
clk I/O
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUD: PULLUP DISABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE WDx: WRITE DDRx
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE RDx: READ DDRx
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE RRx: READ PORTx REGISTER
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE WRx: WRITE PORTx
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE RPx: READ PORTx PIN
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE WPx: WRITE PINx
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE clkI/O: I/O CLOCK
SLEEP: SLEEP CONTROL DIxn: DIGITAL INPUT PIN n ON PORTx
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
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Table 6-31 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 6-26 on page 95 are not shown in the succeeding tables. The overriding signals are
generated internally in the modules having the alternate function.
Table 6-31. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description
If this signal is set, the pull-up enable is controlled by the PUOV
Pull-up Override
PUOE signal. If this signal is cleared, the pull-up is enabled when
Enable
{DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is
Pull-up Override
PUOV set/cleared, regardless of the setting of the DDxn, PORTxn,
Value
and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the
Data Direction
DDOE DDOV signal. If this signal is cleared, the Output driver is
Override Enable
enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
Data Direction
DDOV DDOV is set/cleared, regardless of the setting of the DDxn
Override Value
Register bit.
If this signal is set and the Output Driver is enabled, the port
Port Value value is controlled by the PVOV signal. If PVOE is cleared, and
PVOE
Override Enable the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
Port Value If PVOE is set, the port value is set to PVOV, regardless of the
PVOV
Override Value setting of the PORTxn Register bit.
Port Toggle
PTOE If PTOE is set, the PORTxn Register bit is inverted.
Override Enable
Digital Input If this bit is set, the Digital Input Enable is controlled by the
DIEOE Enable Override DIEOV signal. If this signal is cleared, the Digital Input Enable
Enable is determined by MCU state (Normal mode, sleep mode).
Digital Input If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV Enable Override DIEOV is set/cleared, regardless of the MCU state (Normal
Value mode, sleep mode).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but
DI Digital Input before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
This is the Analog Input/output to/from alternate functions. The
Analog
AIO signal is connected directly to the pad, and can be used
Input/Output
bi-directionally.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
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6.10.3.1 MCU Control Register – MCUCR

Bit 7 6 5 4 3 2 1 0
– – – PUD – – IVSEL IVCE MCUCR
Read/Write R R R R/W R R R/W R/W
• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
“Configuring the Pin” on page 90 for more details about this feature.
6.10.3.2 Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 6-32.
Table 6-32. Port B Pins Alternate Functions

Port Pin Alternate Functions
XTAL2 (Chip Clock Oscillator pin 2)
PB7 TOSC2 (Timer Oscillator pin 2)
PCINT7 (Pin Change Interrupt 7)
XTAL1 (Chip Clock Oscillator pin 1 or External clock input)
PB6 TOSC1 (Timer Oscillator pin 1)
SCK (SPI Bus Master clock Input)
PB5
MISO (SPI Bus Master Input/Slave Output)
PB4
MOSI (SPI Bus Master Output/Slave Input)
PB3 OC2A (Timer/Counter2 Output Compare Match A Output)
SS (SPI Bus Master Slave select)
PB2 OC1B (Timer/Counter1 Output Compare Match B Output)
OC1A (Timer/Counter1 Output Compare Match A Output)
PB1
ICP1 (Timer/Counter1 Input Capture Input)
PB0 CLKO (Divided System Clock Output)
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The alternate pin configuration is as follows:
• XTAL2/TOSC2/PCINT7 – Port B, Bit 7
XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency
crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as
chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR.
When the AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable asyn-
chronous clocking of Timer/Counter2 using the Crystal Oscillator, pin PB7 is disconnected
from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a
crystal Oscillator is connected to this pin, and the pin cannot be used as an I/O pin.
PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt
source.
If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.
• XTAL1/TOSC1/PCINT6 – Port B, Bit 6
XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated
RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as
chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR.
When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2,
pin PB6 is disconnected from the port, and becomes the input of the inverting Oscillator
amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be
used as an I/O pin.
source.
If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.
• SCK/PCINT5 – Port B, Bit 5
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled
as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the
SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the
pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.
source.
• MISO/PCINT4 – Port B, Bit 4
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled
as a Master, this pin is configured as an input regardless of the setting of DDB4. When the
SPI is enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin
is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.
source.
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• MOSI/OC2/PCINT3 – Port B, Bit 3

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled
as a Slave, this pin is configured as an input regardless of the setting of DDB3. When the
SPI is enabled as a Master, the data direction of this pin is controlled by DDB3. When the
pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit.
OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the
Timer/Counter2 Compare Match. The PB3 pin has to be configured as an output (DDB3 set
(one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer
function.
source.
• SS/OC1B/PCINT2 – Port B, Bit 2
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin is
driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled
by DDB2. When the pin is forced by the SPI to be an input, the pull-up can still be controlled
by the PORTB2 bit.
OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the
Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2
set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode
timer function.
source.
• OC1A/PCINT1 – Port B, Bit 1
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the
Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1
set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode
timer function.
source.
• ICP1/CLKO/PCINT0 – Port B, Bit 0
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB0 and DDB0 settings. It will also be output during reset.
source.
Table 6-33 on page 100 and Table 6-34 on page 100 relate the alternate functions of Port B
to the overriding signals shown in Figure 6-26 on page 95. SPI MSTR INPUT and SPI
SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUT-
PUT and SPI SLAVE INPUT.
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Table 6-33. Overriding Signals for Alternate Functions in PB7..PB4
Signal PB7/XTAL2/ PB6/XTAL1/ PB5/SCK/ PB4/MISO/
Name TOSC2/PCINT7(1) TOSC1/PCINT6(1) PCINT5 PCINT4
INTRC • EXTCK+
PUOE INTRC + AS2 SPE • MSTR SPE • MSTR
AS2
PUOV 0 0 PORTB5 • PUD PORTB4 • PUD
INTRC • EXTCK+
DDOE INTRC + AS2 SPE • MSTR SPE • MSTR
AS2
DDOV 0 0 0 0
PVOE 0 0 SPE • MSTR SPE • MSTR
SPI SLAVE
PVOV 0 0 SCK OUTPUT
OUTPUT
INTRC • EXTCK +
INTRC + AS2 +
DIEOE AS2 + PCINT7 • PCINT5 • PCIE0 PCINT4 • PCIE0
PCINT6 • PCIE0
PCIE0
(INTRC + EXTCK) •
DIEOV INTRC • AS2 1 1
AS2
PCINT5 INPUT PCINT4 INPUT
DI PCINT7 INPUT PCINT6 INPUT
SCK INPUT SPI MSTR INPUT
Oscillator/Clock
AIO Oscillator Output – –
Input
Notes: 1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),
EXTCK means that external clock is selected (by the CKSEL fuses).
Table 6-34. Overriding Signals for Alternate Functions in PB3..PB0

Signal PB3/MOSI/ PB2/SS/ PB1/OC1A/ PB0/ICP1/
Name OC2/PCINT3 OC1B/PCINT2 PCINT1 PCINT0
PUOE SPE • MSTR SPE • MSTR 0 0
PUOV PORTB3 • PUD PORTB2 • PUD 0 0
DDOE SPE • MSTR SPE • MSTR 0 0
DDOV 0 0 0 0
SPE • MSTR +
PVOE OC1B ENABLE OC1A ENABLE 0
OC2A ENABLE
SPI MSTR OUTPUT
PVOV OC1B OC1A 0
+ OC2A
DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0
DIEOV 1 1 1 1
PCINT3 INPUT PCINT2 INPUT PCINT0 INPUT
DI PCINT1 INPUT
SPI SLAVE INPUT SPI SS ICP1 INPUT
AIO – – – –
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6.10.3.3 Alternate Functions of Port C

The Port C pins with alternate functions are shown in Table 6-35.
Table 6-35. Port C Pins Alternate Functions

Port Pin Alternate Function
RESET (Reset pin)
PC6
ADC5 (ADC Input Channel 5)
PC5 SCL (2-wire Serial Bus Clock Line)
PC4 SDA (2-wire Serial Bus Data Input/Output Line)
PC3
PC2
PC1
PC0

• RESET/PCINT14 – Port C, Bit 6
RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a nor-
mal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its
reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected
to the pin, and the pin can not be used as an I/O pin.
If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.
PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt
source.
• SCL/ADC5/PCINT13 – Port C, Bit 5
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the
2-wire Serial Interface, pin PC5 is disconnected from the port and becomes the Serial Clock
I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-
press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain
driver with slew-rate limitation.
PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital
power.
source.
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• SDA/ADC4/PCINT12 – Port C, Bit 4
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the
2-wire Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data
I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-
press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain
driver with slew-rate limitation.
PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital
power.
source.
• ADC3/PCINT11 – Port C, Bit 3
PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog
power.
source.
power.
source.
power.
source.
power.
source.
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Table 6-36 and Table 6-37 relate the alternate functions of Port C to the overriding signals
shown in Figure 6-26 on page 95.
Table 6-36. Overriding Signals for Alternate Functions in PC6..PC4(1)

Signal
Name PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 PC4/SDA/ADC4/PCINT12
PUOE RSTDISBL TWEN TWEN
PUOV 1 PORTC5 • PUD PORTC4 • PUD
DDOE RSTDISBL TWEN TWEN
DDOV 0 SCL_OUT SDA_OUT
PVOE 0 TWEN TWEN
PVOV 0 0 0
RSTDISBL + PCINT14 •
DIEOE PCINT13 • PCIE1 + ADC5D PCINT12 • PCIE1 + ADC4D
PCIE1
DIEOV RSTDISBL PCINT13 • PCIE1 PCINT12 • PCIE1
DI PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT
AIO RESET INPUT ADC5 INPUT / SCL INPUT ADC4 INPUT / SDA INPUT
Note: 1. When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4
and PC5. This is not shown in the figure. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
Table 6-37. Overriding Signals for Alternate Functions in PC3..PC0

Signal PC3/ADC3/ PC2/ADC2/ PC1/ADC1/ PC0/ADC0/
Name PCINT11 PCINT10 PCINT9 PCINT8
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
PCINT11 • PCIE1 + PCINT10 • PCIE1 + PCINT9 • PCIE1 + PCINT8 • PCIE1 +
DIEOE
ADC3D ADC2D ADC1D ADC0D
DIEOV PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1
DI PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT PCINT8 INPUT
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
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6.10.3.4 Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 6-38.
Table 6-38. Port D Pins Alternate Functions

Port Pin Alternate Function
AIN1 (Analog Comparator Negative Input)
PD7
AIN0 (Analog Comparator Positive Input)
PD6 OC0A (Timer/Counter0 Output Compare Match A Output)
T1 (Timer/Counter 1 External Counter Input)
PD5 OC0B (Timer/Counter0 Output Compare Match B Output)
XCK (USART External Clock Input/Output)
PD4 T0 (Timer/Counter 0 External Counter Input)
INT1 (External Interrupt 1 Input)
PD3 OC2B (Timer/Counter2 Output Compare Match B Output)
INT0 (External Interrupt 0 Input)
PD2
TXD (USART Output Pin)
PD1
RXD (USART Input Pin)
PD0

• AIN1/OC2B/PCINT23 – Port D, Bit 7
AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the
Analog Comparator.
PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt
source.
• AIN0/OC0A/PCINT22 – Port D, Bit 6
AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the
Analog Comparator.
OC0A, Output Compare Match output: The PD6 pin can serve as an external output for the
Timer/Counter0 Compare Match A. The PD6 pin has to be configured as an output (DDD6
set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode
timer function.
source.
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• T1/OC0B/PCINT21 – Port D, Bit 5

T1, Timer/Counter1 counter source.
OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the
Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an output (DDD5
timer function.
source.
• XCK/T0/PCINT20 – Port D, Bit 4
XCK, USART external clock.
T0, Timer/Counter0 counter source.
source.
• INT1/OC2B/PCINT19 – Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.
OC2B, Output Compare Match output: The PD3 pin can serve as an external output for the
Timer/Counter0 Compare Match B. The PD3 pin has to be configured as an output (DDD3
timer function.
source.
• INT0/PCINT18 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.
source.
• TXD/PCINT17 – Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is
enabled, this pin is configured as an output regardless of the value of DDD1.
source.
• RXD/PCINT16 – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled
this pin is configured as an input regardless of the value of DDD0. When the USART forces
this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
source.
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Table 6-39 and Table 6-40 relate the alternate functions of Port D to the overriding signals
shown in Figure 6-26 on page 95.
Table 6-39. Overriding Signals for Alternate Functions PD7..PD4

Signal PD7/AIN1 PD6/AIN0/ PD5/T1/OC0B/ PD4/XCK/
Name /PCINT23 OC0A/PCINT22 PCINT21 T0/PCINT20
PUOE 0 0 0 0
PUO 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 OC0A ENABLE OC0B ENABLE UMSEL
PVOV 0 OC0A OC0B XCK OUTPUT
DIEOE PCINT23 • PCIE2 PCINT22 • PCIE2 PCINT21 • PCIE2 PCINT20 • PCIE2
DIEOV 1 1 1 1
PCINT20 INPUT
PCINT21 INPUT
DI PCINT23 INPUT PCINT22 INPUT XCK INPUT
T1 INPUT
T0 INPUT
AIO AIN1 INPUT AIN0 INPUT – –
Table 6-40. Overriding Signals for Alternate Functions in PD3..PD0

Signal PD3/OC2B/INT1/ PD2/INT0/ PD1/TXD/ PD0/RXD/
Name PCINT19 PCINT18 PCINT17 PCINT16
PUOE 0 0 TXEN RXEN
PUO 0 0 0 PORTD0 • PUD
DDOE 0 0 TXEN RXEN
DDOV 0 0 1 0
PVOE OC2B ENABLE 0 TXEN 0
PVOV OC2B 0 TXD 0
INT1 ENABLE + INT0 ENABLE +
DIEOE PCINT17 • PCIE2 PCINT16 • PCIE2
PCINT19 • PCIE2 PCINT18 • PCIE1
DIEOV 1 1 1 1
PCINT19 INPUT PCINT18 INPUT PCINT16 INPUT
DI PCINT17 INPUT
INT1 INPUT INT0 INPUT RXD
AIO – – – –
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6.10.4 Register Description for I/O Ports
6.10.4.1 The Port B Data Register – PORTB

Bit 7 6 5 4 3 2 1 0
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB
6.10.4.2 The Port B Data Direction Register – DDRB

Bit 7 6 5 4 3 2 1 0
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB
6.10.4.3 The Port B Input Pins Address – PINB

Bit 7 6 5 4 3 2 1 0
PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
6.10.4.4 The Port C Data Register – PORTC

Bit 7 6 5 4 3 2 1 0
– PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R R/W R/W R/W R/W R/W R/W R/W
6.10.4.5 The Port C Data Direction Register – DDRC

Bit 7 6 5 4 3 2 1 0
– DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
6.10.4.6 The Port C Input Pins Address – PINC

Bit 7 6 5 4 3 2 1 0
– PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Initial Value 0 N/A N/A N/A N/A N/A N/A N/A
6.10.4.7 The Port D Data Register – PORTD

Bit 7 6 5 4 3 2 1 0
PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD
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6.10.4.8 The Port D Data Direction Register – DDRD
Bit 7 6 5 4 3 2 1 0
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
6.10.4.9 The Port D Input Pins Address – PIND

Bit 7 6 5 4 3 2 1 0
PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
6.11 External Interrupts

The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins
are configured as outputs. This feature provides a way of generating a software interrupt. The
pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change
interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0
will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-
ters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Register A – EICRA.
When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-
rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge
interrupts on INT0 or INT1 requires the presence of an I/O clock, described in “Clock Systems
and their Distribution” on page 51. Low level interrupt on INT0 and INT1 is detected asynchro-
nously. This implies that this interrupt can be used for waking the part also from sleep modes
other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in “System Clock and Clock Options” on page 51.
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6.11.1 External Interrupt Control Register A – EICRA

The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 7 6 5 4 3 2 1 0
– – – – ISC11 ISC10 ISC01 ISC00 EICRA
• Bit 7..4 – Res: Reserved Bits

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the cor-
responding interrupt mask are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in Table 6-41. The value on the INT1 pin is sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt.
Table 6-41. Interrupt 1 Sense Control

ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any logical change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the cor-
responding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 6-42. The value on the INT0 pin is sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt.
Table 6-42. Interrupt 0 Sense Control

ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
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6.11.2 External Interrupt Mask Register – EIMSK
Bit 7 6 5 4 3 2 1 0
– – – – – – INT1 INT0 EIMSK
Read/Write R R R R R R R/W R/W

• Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in
the External Interrupt Control Register A (EICRA) define whether the external interrupt is
activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will
cause an interrupt request even if INT1 is configured as an output. The corresponding inter-
rupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in
the External Interrupt Control Register A (EICRA) define whether the external interrupt is
activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will
cause an interrupt request even if INT0 is configured as an output. The corresponding inter-
rupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
6.11.3 External Interrupt Flag Register – EIFR

Bit 7 6 5 4 3 2 1 0
– – – – – – INTF1 INTF0 EIFR

• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes
set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to
cuted. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
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6.11.4 Pin Change Interrupt Control Register - PCICR
Bit 7 6 5 4 3 2 1 0
– – – – – PCIE2 PCIE1 PCIE0 PCICR
Read/Write R R R R R R/W R/W R/W
• Bit 7..3 - Res: Reserved Bits

• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the
PCI2 Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.
6.11.5 Pin Change Interrupt Flag Register - PCIFR
Bit 7 6 5 4 3 2 1 0
– – – – – PCIF2 PCIF1 PCIF0 PCIFR
• Bit 7..3 - Res: Reserved Bits

• Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes
set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
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6.11.6 Pin Change Mask Register 2 – PCMSK2

Bit 7 6 5 4 3 2 1 0
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2
• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16

Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.

Bit 7 6 5 4 3 2 1 0
– PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
• Bit 7 – Res: Reserved Bit

This bit is an unused bit in the ATA6612/ATA6613, and will always read as zero.
Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.

Bit 7 6 5 4 3 2 1 0
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled
on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corre-
sponding I/O pin is disabled.
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6.12 8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation. The main features are:
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• Clear Timer on Compare Match (Auto Reload)
• Glitch Free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
6.12.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 6-27. The device-spe-
cific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
page 125.
The PRTIM0 bit in “Power Reduction Register - PRR” on page 66 must be written to zero to
enable Timer/Counter0 module.
Figure 6-27. 8-bit Timer/Counter Block Diagram

Count TOVn
Clear (Int.Req.)
Control Logic
Direction clkTN
TOSC1
T/C
Oscillator
Prescaler TOSC2
TOP BOTTOM
clkI/O
Timer/Counter
TCNTn
= = 0
OCnA
(Int.Req.)
Waveform
= OCnA
Generation
OCRnA
Fixed OCnB
TOP (Int.Req.)
DATA BUS
Value
Waveform
= OCnB
Generation
OCRnB
TCCRnA TCCRnB
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6.12.1.1 Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 6-43 are also used extensively throughout the document.
Table 6-43. General Counter Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is dependent
on the mode of operation.
6.12.1.2 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Using the Output Compare Unit” on page 143 for details. The compare match
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Out-
put Compare interrupt request.
6.12.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler (see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 131).
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6.12.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
6-28 shows a block diagram of the counter and its surroundings.
Figure 6-28. Counter Unit Block Diagram

TOVn
DATA BUS (Int.Req.)
Clock Select
count Edge
Tn
clear clkTn Detector
TCNTn Control Logic
direction
(From Prescaler)
bottom top
Signal description (internal signals):

count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation (see “Modes of
Operation” on page 118).
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
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6.12.4 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max
and bottom signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation (see “Modes of Operation” on page 118).
Figure 6-29 shows a block diagram of the Output Compare unit.
Figure 6-29. Output Compare Unit, Block Diagram

DATA BUS
OCRnx TCNTn
= (8-bit Comparator)
OCFnx (Int.Req.)
top
bottom
Waveform Generator OCnx
FOCn
WGMn1:0 COMnX1:0
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR0x directly.
6.12.4.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0x) bit. Forcing compare match will not set the
OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare
match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or
toggled).
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6.12.4.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-
ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
6.12.4.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-
pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when
changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
6.12.5 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses
the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match.
Also, the COM0x1:0 bits control the OC0x pin output source. Figure 6-30 shows a simplified
schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR
and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x
state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur,
the OC0x Register is reset to “0”.
Figure 6-30. Compare Match Output Unit, Schematic
COMnx1
COMnx0 Waveform
D Q
FOCnx Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clkI/O
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The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation (see “8-bit Timer/Counter Register Description” on page 125).
6.12.5.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to Table 6-44 on page 125. For fast PWM mode, refer to Table 6-45 on
page 125, and for phase correct PWM refer to Table 6-46 on page 126.
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output
mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare
match (see “Compare Match Output Unit” on page 117).
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 123.

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
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6.12.6.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 6-31. The counter value (TCNT0)
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
Figure 6-31. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set
TCNTn
OCn
(COMnx1:0 = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
f clk_I/O
f OCnx = ------------------------------------------------------
-
2 ⋅ N ⋅ ( 1 + OCRnx )
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
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6.12.6.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In
non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare
match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode,
the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 6-32. The TCNT0 value is in the timing diagram shown as a his-
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare
matches between OCR0x and TCNT0.
Figure 6-32. Fast PWM Mode, Timing Diagram
OCRnx Interrupt
Flag Set
OCRnx Update and

TOVn Interrupt Flag Set
TCNTn
OCn (COMnx1:0 = 2)
OCn (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows
the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available
for the OC0B pin (see Table 6-48 on page 126). The actual OC0x value will only be visible on
the port pin if the data direction for the port pin is set as output. The PWM waveform is gener-
ated by setting (or clearing) the OC0x Register at the compare match between OCR0x and
TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
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The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = --------------------
-
N ⋅ 256
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform
generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-
put Compare unit is enabled in the fast PWM mode.
6.12.6.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In
match between TCNT0 and OCR0x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to
the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor con-
trol applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 6-33 on page 122. The TCNT0 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM out-
puts. The small horizontal line marks on the TCNT0 slopes represent compare matches
between OCR0x and TCNT0.
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Figure 6-33. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt
Flag Set
OCRnx Update
TOVn Interrupt
Flag Set
TCNTn
OCn (COMnx1:0 = 2)
OCn (COMnx1:0 = 3)
Period 1 2 3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (see Table 6-49 on page 127). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and
TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare
match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = --------------------
-
N ⋅ 510
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
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At the very start of period 2 in Figure 6-33 on page 122 OCnx has a transition from high to low
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCRnx changes its value from MAX, like in Figure 6-33 on page 122. When the OCR0A
value is MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCnx value at MAX must correspond to
the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
misses the Compare Match and hence the OCnx change that would have happened on the
way up.
6.12.7 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 6-34 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 6-34. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTN
(clkI/O/1)
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
Figure 6-35 shows the same timing data, but with the prescaler enabled.
Figure 6-35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTN
(clkI/O/8)
TOVn
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Figure 6-36 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 6-36. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCRnx OCRnx Value
OCFnx
Figure 6-37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM
mode where OCR0A is TOP.
Figure 6-37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-
caler (fclk_I/O/8)
clkI/O
clkTN
(clkI/O/8)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC)
OCRnx TOP
OCFnx
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6.12.8 8-bit Timer/Counter Register Description
6.12.8.1 Timer/Counter Control Register A – TCCR0A

Bit 7 6 5 4 3 2 1 0
COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 6-44 shows the COM0A1:0 bit functionality when the WGM02:0
bits are set to a normal or CTC mode (non-PWM).
Table 6-44. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on Compare Match
1 0 Clear OC0A on Compare Match
1 1 Set OC0A on Compare Match
Table 6-45 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 6-45. Compare Output Mode, Fast PWM Mode(1)

WGM02 = 0: Normal Port Operation, OC0A Disconnected.
0 1
WGM02 = 1: Toggle OC0A on Compare Match.
1 0 Clear OC0A on Compare Match, set OC0A at TOP
1 1 Set OC0A on Compare Match, clear OC0A at TOP
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 120
for more details.
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Table 6-46 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Table 6-46. Compare Output Mode, Phase Correct PWM Mode(1)

0 1
Clear OC0A on Compare Match when up-counting. Set OC0A on
1 0
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
1 1
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 149 for more details.
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the
COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O
ing to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 6-47 shows the COM0B1:0 bit functionality when the WGM02:0

COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on Compare Match
1 0 Clear OC0B on Compare Match
1 1 Set OC0B on Compare Match
Table 6-48 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
0 1 Reserved
1 0 Clear OC0B on Compare Match, set OC0B at TOP
1 1 Set OC0B on Compare Match, clear OC0B at TOP
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
for more details.
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Table 6-49 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.

0 1 Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
1 0
Set OC0B on Compare Match when up-counting. Clear OC0B on
1 1
• Bits 3, 2 – Res: Reserved Bits
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation to be used (see Table 6-50). Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC)
mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation”
on page 118).
Table 6-50. Waveform Generation Mode Bit Description

Timer/Counter
Mode of Update of TOV Flag
Mode WGM02 WGM01 WGM00 Operation TOP OCRx at Set on(1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
PWM, Phase
1 0 0 1 0xFF TOP BOTTOM
Correct
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –
PWM, Phase
5 1 0 1 OCRA TOP BOTTOM
Correct
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Notes: 1. MAX = 0xFF

2. BOTTOM = 0x00
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6.12.8.2 Timer/Counter Control Register B – TCCR0B
Bit 7 6 5 4 3 2 1 0
FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R R R/W R/W
• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A
bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A
output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is imple-
mented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines
the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B
bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B
output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is imple-
mented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “Timer/Counter Control Register A – TCCR0A” on page 125.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
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Table 6-51. Clock Select Bit Description

CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clkI/O/(No prescaling)
0 1 0 clkI/O/8 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
6.12.8.3 Timer/Counter Register – TCNT0

Bit 7 6 5 4 3 2 1 0
TCNT0[7:0] TCNT0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
6.12.8.4 Output Compare Register A – OCR0A

Bit 7 6 5 4 3 2 1 0
OCR0A[7:0] OCR0A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
6.12.8.5 Output Compare Register B – OCR0B

Bit 7 6 5 4 3 2 1 0
OCR0B[7:0] OCR0B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
generate a waveform output on the OC0B pin.
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6.12.8.6 Timer/Counter Interrupt Mask Register – TIMSK0
Bit 7 6 5 4 3 2 1 0
– – – – – OCIE0B OCIE0A TOIE0 TIMSK0

• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is exe-
cuted if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0
Interrupt Flag Register – TIFR0.
6.12.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR0

Bit 7 6 5 4 3 2 1 0
– – – – – OCF0B OCF0A TOV0 TIFR0

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the
data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B
Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is
executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a
logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match
Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is
executed.
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• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is
executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 6-50 on page
127 and “Waveform Generation Mode Bit Description” on page 127.
6.13 Timer/Counter0 and Timer/Counter1 Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
6.13.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or
fCLK_I/O/1024.
6.13.2 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
6.13.3 External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 6-38
on page 132 shows a functional equivalent block diagram of the T1/T0 synchronization and
edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
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Figure 6-38. T1/T0 Pin Sampling
Tn D Q D Q D Q Tn_sync
(To Clock
Select Logic)
LE
clkI/O
Synchronization Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 6-39. Prescaler for Timer/Counter0 and Timer/Counter1(1)

clkI/O 10-BIT T/C PRESCALER
Clear
CK/64
CK/1024
CK/256
CK/8
PSRSYNC
T0
Synchronization
T1
Synchronization 0 0
CS10 CS00
CS11 CS01
CS12 CS02
TIMER/COUNTER1 CLOCK SOURCE TIMER/COUNTER0 CLOCK SOURCE

clkT1 clkT0
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 6-38.
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6.13.4 General Timer/Counter Control Register – GTCCR

Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R R R R R R/W R/W
• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode,
the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the cor-
responding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of one
of them advancing during configuration. When the TSM bit is written to zero, the PSRASY
and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting
simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is
normally cleared immediately by hardware, except if the TSM bit is set. Note that
Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler
will affect both timers.
6.14 16-bit Timer/Counter1 with PWM

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• External Event Counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
6.14.1 Overview
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 6-40 on page 134. The
device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register
Description” on page 155.
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Figure 6-40. 16-bit Timer/Counter Block Diagram(1)
Count TOVn
Clear (Int.Req.)
Control Logic
Direction clkTn Clock Select
Edge
Tn
Detector
TOP BOTTOM
(From Prescaler)
Timer/Counter
TCNTn
= =0
OCnA
(Int.Req.)
Waveform
= OCnA
Generation
OCRnA
Fixed OCnB
TOP (Int.Req.)
Values
Waveform
OCnB
DATA BUS
= Generation
OCRnB (From Analog

Comparator Ouput)
ICFn (Int.Req.)
Edge Noise
ICRn
Detector Canceler
ICPn
TCCRnA TCCRnB
Note: 1. Refer to Table 6-32 on page 97 and Table 6-38 on page 104 for Timer/Counter1 pin
placement and description.
6.14.1.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-
ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the
16-bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 135. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all
visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with
the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1).
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The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun-
ter value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OC1A/B), see “Out-
put Compare Units” on page 142. The compare match event will also set the Compare Match
Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (see
“Analog Comparator” on page 262). The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using
OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used
as an alternative, freeing the OCR1A to be used as PWM output.
The following definitions are used extensively throughout the section:
Table 6-52. General Counter Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,
TOP
or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is depen-
dent of the mode of operation.
6.14.2 Accessing 16-bit Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via
the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers within each 16-bit
timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a
16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of
a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-
rary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B
16-bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit
access.
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Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-
ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents.
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
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TIM16_ReadTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNT1 Register contents.
Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

TIM16_WriteTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
The assembly code example requires that the r17:r16 register pair contains the value to be writ-
ten to TCNT1.
6.14.2.1 Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,
then the high byte only needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
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The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits
located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and
prescaler (see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 131).
6.14.4 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 6-41 shows a block diagram of the counter and its surroundings.

DATA BUS (8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Count Edge
Tn
TCNTnH (8-bit) TCNTnL (8-bit) Clear clkTn Detector
Control Logic
Direction
TCNTn (16-bit Counter)
(From Prescaler)
TOP BOTTOM

Count Increment or decrement TCNT1 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT1 (set all bits to zero).
clkT1 Timer/Counter clock.
TOP Signalize that TCNT1 has reached maximum value.
BOTTOM Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT1H value when the TCNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source,
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
count operations.
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The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC1x. For more details about advanced counting
sequences and waveform generation (see “Modes of Operation” on page 145).
6.14.5 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-
nal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 6-42. The elements of
the block diagram that are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
Figure 6-42. Input Capture Unit Block Diagram

DATA BUS (8-bit)
TEMP (8-bit)
ICRnH (8-bit) ICRnL (8-bit) TCNTnH (8-bit) TCNTnL (8-bit)
WRITE ICRn (16-bit Register) TCNTn (16-bit Counter)
ACO* ACIC* ICNC ICES
Analog
Comparator Noise Edge
ICFn (Int.Req.)
Canceler Detector
ICPn
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively
on the Analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at
the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),
the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically
cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software
by writing a logical one to its I/O bit location.
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Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied
into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will
access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location
before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 135.
6.14.5.1 Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the T1 pin (see Figure 6-38 on page 132). The edge detector is
also identical. However, when the noise canceler is enabled, additional logic is inserted before
the edge detector, which increases the delay by four system clock cycles. Note that the input of
the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a
Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
6.14.5.2 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
6.14.5.3 Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 Flag is not required (if an interrupt handler is used).
6.14.6 Output Compare Units

The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-
pare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (see “Modes of Operation” on page 145).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 6-43 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.

DATA BUS (8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit)
OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter)
OCRnxH (8-bit) OCRnxL (8-bit)
OCRnx (16-bit Register)
OCFnx (Int.Req.)
TOP
BOTTOM
WGMn3:0 COMnx1:0
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The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-
put glitch-free.
abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Reg-
ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 135.

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or
toggled).

All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

cycle, there are risks involved when changing TCNT1 when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect wave-
form generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.
pare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when
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Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 6-44 shows a simplified
schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the
OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset
occur, the OC1x Register is reset to “0”.
COMnx1
COMnx0 Waveform
D Q
FOCnx Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clkI/O
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 6-53 on page 155, Table 6-54 on page 155
and Table 6-55 on page 156 for details.
The COM1x1:0 bits have no effect on the Input Capture unit.
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The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.
non-PWM modes refer to Table 6-53 on page 155. For fast PWM mode refer to Table 6-54 on
page 155, and for phase correct and phase and frequency correct PWM refer to Table 6-55 on
page 156.
FOC1x strobe bits.

the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
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In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =
12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the opera-
tion of counting external events.
increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)
is cleared.
OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(COMnA1:0 = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-
ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buff-
ering feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the compare match. The counter will then have to count to its max-
imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-
quency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is
defined by the following equation:
f clk_I/O
f OCnA = -------------------------------------------------------
-
2 ⋅ N ⋅ ( 1 + OCRnA )
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
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The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on
the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting Compare
Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper-
ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high fre-
quency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capaci-
tors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max-
imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
log ( TOP + 1 )
R FPWM = -----------------------------------
log ( 2 )
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =
14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 6-46. The figure
shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will
be set when a compare match occurs.
OCRnx/TOP Update and

TOVn Interrupt Flag Set and
(Interrupt on TOP)
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7 8
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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition
the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A
or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-
dler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP
value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICR1 value written is lower than the current value of TCNT1. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location
to be written anytime. When the OCR1A I/O location is written the value written will be put into
the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done
at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
can be generated by setting the COM1x1:0 to three (see Table on page 155). The actual OC1x
value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at
the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
f clk_I/O
f OCnxPWM = -------------------------------------
N ⋅ ( 1 + TOP )
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits).
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ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is
similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com-
pare unit is enabled in the fast PWM mode.

The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then
from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-
tion in bits can be calculated by using the following equation:
log ( TOP + 1 )
R PCPWM = -----------------------------------
log ( 2 )
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 6-47 on page
150. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP.
The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The
OC1x Interrupt Flag will be set when a compare match occurs.
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OCRnx/TOP Update and
(Interrupt on TOP)

(Interrupt on Bottom)
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When
either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord-
ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x Registers are written. As the third period shown in Figure 6-47 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg-
ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM1x1:0 to three. The actual OC1x value will
only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x).
The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare
match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the
OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements.
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The PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
f clk_I/O
f OCnxPCPWM = ---------------------------------
2 ⋅ N ⋅ TOP
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
6.14.8.5 Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x Register is updated by the OCR1x Buffer Register (see Figure 6-47
on page 150 and Figure 6-48 on page 152).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
log ( TOP + 1 -)
R PFCPWM = ----------------------------------
log ( 2 )
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 6-48 on page 152. The figure shows phase and fre-
quency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in
the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will
be set when a compare match occurs.
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Figure 6-48. Phase and Frequency Correct PWM Mode, Timing Diagram
(Interrupt on TOP)
OCRnx/TOP Updateand
(Interrupt on Bottom)
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1
is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.
The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
As Figure 6-48 shows the output generated is, in contrast to the phase correct mode, symmetri-
cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table on
page 156). The actual OC1x value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-
ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPFCPWM = ---------------------------------
2 ⋅ N ⋅ TOP
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The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.

The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering). Figure 6-49 shows a timing diagram for the setting of OCF1x.
Figure 6-49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
clkI/O
clkTn
(clkI/O/1)
OCRnx OCRnx Value
OCFnx
Figure 6-50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
OCRnx OCRnx Value
OCFnx
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Figure 6-51 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOV1 Flag at BOTTOM.
clkI/O
clkTn
(clkI/O/1)
TCNTn
(CTC and FPWM)
TCNTn
TOP - 1 TOP TOP - 1 TOP - 2
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1
TCNTn
TOP - 1 TOP TOP - 1 TOP - 2
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)
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6.14.10.1 Timer/Counter1 Control Register A – TCCR1A

Bit 7 6 5 4 3 2 1 0
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of
the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is
dependent of the WGM13:0 bits setting. Table 6-53 shows the COM1x1:0 bit functionality
when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 6-53. Compare Output Mode, non-PWM

COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
1 0
low level).
Set OC1A/OC1B on Compare Match (Set output to high
1 1
level).
Table 6-54 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
PWM mode.
Table 6-54. Compare Output Mode, Fast PWM(1)

WGM13:0 = 14 or 15: Toggle OC1A on Compare Match,
OC1B disconnected (normal port operation). For all
0 1
other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match, set
1 0
OC1A/OC1B at TOP
Set OC1A/OC1B on Compare Match, clear
1 1
OC1A/OC1B at TOP
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 147 for more details.
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Table 6-55 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Table 6-55. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
WGM13:0 = 8, 9, 10 or 11: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation). For
0 1
all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match when
1 0 up-counting. Set OC1A/OC1B on Compare Match when
downcounting.
Set OC1A/OC1B on Compare Match when up-counting.
1 1 Clear OC1A/OC1B on Compare Match when
downcounting.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
“Phase Correct PWM Mode” on page 149 for more details.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and what
type of waveform generation to be used (see Table 6-56 on page 157). Modes of operation
supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see “Modes
of Operation” on page 145).
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Table 6-56. Waveform Generation Mode Bit Description(1)

WGM12 WGM11 WGM10 Timer/Counter Mode of Update of TOV1 Flag
Mode WGM13 (CTC1) (PWM11) (PWM10) Operation TOP OCR1x at Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
4 0 1 0 0 CTC OCR1A Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
PWM, Phase and Frequency
8 1 0 0 0 ICR1 BOTTOM BOTTOM
Correct
PWM, Phase and Frequency
9 1 0 0 1 OCR1A BOTTOM BOTTOM
Correct
10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM
12 1 1 0 0 CTC ICR1 Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICR1 TOP TOP
15 1 1 1 1 Fast PWM OCR1A TOP TOP
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
6.14.10.2 Timer/Counter1 Control Register B – TCCR1B

Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler
is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires
four successive equal valued samples of the ICP1 pin for changing its output. The Input
Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into
the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and
this can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input
Capture function is disabled.
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• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit
must be written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
Figure 6-49 on page 153 and Figure 6-50 on page 153.

0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkI/O/1 (No prescaling)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.
counting.
6.14.10.3 Timer/Counter1 Control Register C – TCCR1C

Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B – – – – – – TCCR1C
Read/Write R/W R/W R R R R R R
• Bit 7 – FOC1A: Force Output Compare for Channel A

• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to zero
when TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation
unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
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6.14.10.4 Timer/Counter1 – TCNT1H and TCNT1L

Bit 7 6 5 4 3 2 1 0
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers see “Accessing 16-bit
Registers” on page 135.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
6.14.10.5 Output Compare Register 1 A – OCR1AH and OCR1AL

Bit 7 6 5 4 3 2 1 0
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
6.14.10.6 Output Compare Register 1 B – OCR1BH and OCR1BL

Bit 7 6 5 4 3 2 1 0
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
The Output Compare Registers contain a 16-bit value that is continuously compared with the
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers (see “Accessing 16-bit Registers” on page 135).
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6.14.10.7 Input Capture Register 1 – ICR1H and ICR1L
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers (see “Accessing 16-bit Registers” on page 135).
6.14.10.8 Timer/Counter1 Interrupt Mask Register – TIMSK1

Bit 7 6 5 4 3 2 1 0
– – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W R R R/W R/W R/W
• Bit 7, 6 – Res: Reserved Bits

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Inter-
rupt Vector (see “Interrupts” on page 79) is executed when the ICF1 Flag, located in TIFR1,
is set.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corre-
sponding Interrupt Vector (see “Interrupts” on page 79) is executed when the OCF1B Flag,
located in TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corre-
sponding Interrupt Vector (see “Interrupts” on page 79) is executed when the OCF1A Flag,
located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt
Vector (see “Watchdog Timer” on page 74) is executed when the TOV1 Flag, located in
TIFR1, is set.
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6.14.10.9 Timer/Counter1 Interrupt Flag Register – TIFR1

Bit 7 6 5 4 3 2 1 0
– – ICF1 – – OCF1B OCF1A TOV1 TIFR1
Read/Write R R R/W R R R/W R/W R/W

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Reg-
ister (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when
the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alterna-
tively, ICF1 can be cleared by writing a logic one to its bit location.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC
modes, the TOV1 Flag is set when the timer overflows. Refer to Table 6-56 on page 157 for
the TOV1 Flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is exe-
cuted. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
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6.15 8-bit Timer/Counter2 with PWM and Asynchronous Operation
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
• Single Channel Counter
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
6.15.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 6-53. The device-spe-
cific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
page 174.
Figure 6-53. 8-bit Timer/Counter Block Diagram

Count TOVn
Clear (Int.Req.)
Control Logic
Direction clkTN
TOSC1
T/C
Oscillator
Prescaler TOSC2
TOP BOTTOM
clkI/O
Timer/Counter
TCNTn
= = 0
OCnA
(Int.Req.)
Waveform
= OCnA
Generation
OCRnA
Fixed OCnB
TOP (Int.Req.)
DATA BUS
Value
Waveform
= OCnB
Generation
OCRnB
TCCRnA TCCRnB
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6.15.1.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-
isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag
Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-
tive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and
OC2B). See “Output Compare Unit” on page 165 for details. The compare match event will also
set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare
interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2
counter value and so on.
The definitions below are also used extensively throughout the section.
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is dependent
on the mode of operation.

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation (see “Asyn-
chronous Status Register – ASSR” on page 181). For details on clock sources and prescaler,
see “Timer/Counter Prescaler” on page 183.
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6.15.3 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
6-54 shows a block diagram of the counter and its surrounding environment.

TOVn
DATA BUS (Int.Req.)
TOSC1
count
clkTn T/C
clear Oscillator
TCNTn Control Logic Prescaler
direction
TOSC2
bottom top clkI/O

count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT2 in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source,
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter
Control Register B (TCCR2B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.
For more details about advanced counting sequences and waveform generation (see “Modes of
Operation” on page 168).
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6.15.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a
match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)
bits. The max and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (see “Modes of Operation” on page
168).
Figure 6-55 shows a block diagram of the Output Compare unit.

DATA BUS
OCRnx TCNTn
OCFnx (Int.Req.)
top
bottom
FOCn
WGMn1:0 COMnX1:0
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
abled the CPU will access the OCR2x directly.

In non-PWM waveform generation modes, the match output of the comparator can be forced by
match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or
toggled).
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All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-
ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.

cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when

Also, the COM2x1:0 bits control the OC2x pin output source. Figure 6-56 on page 167 shows a
simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control
Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring
to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.
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COMnx1
COMnx0 Waveform
D Q
FOCnx Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clkI/O
ble on the pin. The port override function is independent of the Waveform Generation mode.

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.
non-PWM modes refer to Table 6-61 on page 175. For fast PWM mode, refer to Table 6-62 on
page 175, and for phase correct PWM refer to Table 6-63 on page 176.
FOC2x strobe bits.
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the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will

In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
increases until a compare match occurs between TCNT2 and OCR2A, and then counter
(TCNT2) is cleared.

OCnx Interrupt Flag Set
TCNTn
OCn
(COMnx1:0 = 1)
(Toggle)
Period 1 2 3 4
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An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR2A is lower than the current
value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
the pin is set to output. The waveform generated will have a maximum frequency of fOC2A =
fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following
equation:
f clk_I/O
f OCnx = ------------------------------------------------------
-
2 ⋅ N ⋅ ( 1 + OCRnx )
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In
match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode,
the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 6-58 on page 170. The TCNT2 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes
represent compare matches between OCR2x and TCNT2.
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OCRnx Interrupt
Flag Set
OCRnx Update and

TCNTn
OCn (COMnx1:0 = 2)
OCn (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when MGM2:0 = 7 (see Table 6-59 on page 174). The actual OC2x value will only
be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-
form is generated by setting (or clearing) the OC2x Register at the compare match between
OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the
counter is cleared (changes from TOP to BOTTOM).
f clk_I/O
f OCnxPWM = --------------------
-
N ⋅ 256
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0
bits.)
ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform
generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This fea-
ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
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The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In
match between TCNT2 and OCR2x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to
the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor con-
trol applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 6-59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x
and TCNT2.
OCnx Interrupt
Flag Set
OCRnx Update
TOVn Interrupt
Flag Set
TCNTn
OCn (COMnx1:0 = 2)
OCn (COMnx1:0 = 3)
Period 1 2 3
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM
output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 6-60 on page 175). The actual OC2x
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
f clk_I/O
f OCnxPCPWM = --------------------
-
N ⋅ 510
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 6-59 on page 171 OCnx has a transition from high to low
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, like in Figure 6-59 on page 171. When the OCR2A
value is MAX the OCn pin value is the same as the result of a down-counting compare match.
To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result
of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2)
is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set. Figure 6-60 contains timing data for basic Timer/Counter operation. The figure shows the
count sequence close to the MAX value in all modes other than phase correct PWM mode.
clkI/O
clkTN
(clkI/O/1)
TOVn
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clkI/O
clkTN
(clkI/O/8)
TOVn
Figure 6-62 shows the setting of OCF2A in all modes except CTC mode.
Figure 6-62. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
OCRnx OCRnx Value
OCFnx
Figure 6-63 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Figure 6-63. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
clkI/O
clkTN
(clkI/O/8)
TCNTn
(CTC)
OCRnx TOP
OCFnx
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6.15.8.1 Timer/Counter Control Register A – TCCR2A

Bit 7 6 5 4 3 2 1 0
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the
COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O
ing to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 6-58 shows the COM2A1:0 bit functionality when the WGM22:0

0 1 Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match
1 1 Set OC2A on Compare Match
Table 6-59 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.

0 1
1 0 Clear OC2A on Compare Match, set OC2A at TOP
1 1 Set OC2A on Compare Match, clear OC2A at TOP
for more details.
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Table 6-60 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.

0 1
Clear OC2A on Compare Match when up-counting. Set OC2A on
1 0
Set OC2A on Compare Match when up-counting. Clear OC2A on
1 1
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the
COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O
ing to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. Table 6-61 shows the COM2B1:0 bit functionality when the WGM22:0

0 1 Toggle OC2B on Compare Match
1 0 Clear OC2B on Compare Match
1 1 Set OC2B on Compare Match
Table 6-62 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
mode.

0 1 Reserved
1 0 Clear OC2B on Compare Match, set OC2B at TOP
1 1 Set OC2B on Compare Match, clear OC2B at TOP
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Table 6-63 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.

0 1 Reserved
Clear OC2B on Compare Match when up-counting. Set OC2B on
1 0
Set OC2B on Compare Match when up-counting. Clear OC2B on
1 1
• Bits 3, 2 – Res: Reserved Bits
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 6-64. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 168).
Table 6-64. Waveform Generation Mode Bit Description

Timer/Counter Update of TOV Flag
Mode WGM2 WGM1 WGM0 Mode of Operation TOP OCRx at Set on(1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
PWM, Phase
1 0 0 1 0xFF TOP BOTTOM
Correct
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –
PWM, Phase
5 1 0 1 OCRA TOP BOTTOM
Correct
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Notes: 1. MAX= 0xFF

2. BOTTOM= 0x00
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6.15.8.2 Timer/Counter Control Register B – TCCR2B

Bit 7 6 5 4 3 2 1 0
FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B
Read/Write W W R R R R R/W R/W
• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A
bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A
output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is imple-
mented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B
bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B
output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is imple-
mented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bit 3 – WGM22: Waveform Generation Mode
See the description in “Timer/Counter Control Register A – TCCR2A” on page 174.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter (see
Table 6-65 on page 178).
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0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkT2S/(No prescaling)
0 1 0 clkT2S/8 (From prescaler)
counting.
6.15.8.3 Timer/Counter Register – TCNT2

Bit 7 6 5 4 3 2 1 0
TCNT2[7:0] TCNT2
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
6.15.8.4 Output Compare Register A – OCR2A

Bit 7 6 5 4 3 2 1 0
OCR2A[7:0] OCR2A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
generate a waveform output on the OC2A pin.
6.15.8.5 Output Compare Register B – OCR2B

Bit 7 6 5 4 3 2 1 0
OCR2B[7:0] OCR2B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
generate a waveform output on the OC2B pin.
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6.15.8.6 Timer/Counter2 Interrupt Mask Register – TIMSK2

Bit 7 6 5 4 3 2 1 0
– – – – – OCIE2B OCIE2A TOIE2 TIMSK2
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable

When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2
Interrupt Flag Register – TIFR2.
6.15.8.7 Timer/Counter2 Interrupt Flag Register – TIFR2

Bit 7 6 5 4 3 2 1 0
– – – – – OCF2B OCF2A TOV2 TIFR2
• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and
the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare
match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and
the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare
match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
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• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2
is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2
Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt
is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction
at 0x00.
6.15.9 Asynchronous operation of the Timer/Counter
6.15.9.1 Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
b. Select clock source by setting AS2 as appropriate.
c. Write new values to TCNT2, OCR2x, and TCCR2x.
d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and
TCR2xUB.
e. Clear the Timer/Counter2 Interrupt Flags.
f. Enable interrupts, if needed.
• The CPU main clock frequency must be more than four times the Oscillator frequency.
• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a
temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the five mentioned registers have their individual temporary register,
which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To
detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented.
• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,
OCR2x, or TCCR2x, the user must wait until the written register has been updated if
Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode
before the changes are effective. This is particularly important if any of the Output Compare2
interrupt is used to wake up the device, since the Output Compare function is disabled during
writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode
before the corresponding OCR2xUB bit returns to zero, the device will never receive a
compare match interrupt, and the MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction
mode, precautions must be taken if the user wants to re-enter one of these modes: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and
re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the
device will fail to wake up. If the user is in doubt whether the time before re-entering
Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used
to ensure that one TOSC1 cycle has elapsed:
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a. Write a value to TCCR2x, TCNT2, or OCR2x.

b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2
is always running, except in Power-down and Standby modes. After a Power-up Reset or
wake-up from Power-down or Standby mode, the user should be aware of the fact that this
Oscillator might take as long as one second to stabilize. The user is advised to wait for at
least one second before using Timer/Counter2 after power-up or wake-up from Power-down
or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after
a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no
matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O
clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from
Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the Interrupt Flag. The
Output Compare pin is changed on the timer clock and is not synchronized to the processor
clock.
6.15.9.2 Asynchronous Status Register – ASSR

Bit 7 6 5 4 3 2 1 0
– EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR
Read/Write R R/W R/W R R R R R
• Bit 6 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock input
buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin
instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous opera-
tion is selected. Note that the crystal Oscillator will only run when this bit is zero.
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• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When
AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the
Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2,
OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new
value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new
value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new
value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes
set. When TCCR2A has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated
with a new value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes
set. When TCCR2B has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated
with a new value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag
is set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are differ-
ent. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B,
TCCR2A and TCCR2B the value in the temporary storage register is read.
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6.15.10 Timer/Counter Prescaler
Figure 6-64. Prescaler for Timer/Counter2
clkI/O clkT2S
10-BIT T/C PRESCALER
Clear
TOSC1
clkT2S/32
clkT2S/64
clkT2S/128
clkT2S/256
clkT2S/1024
clkT2S/8
AS2
PSRASY 0
CS20
CS21
CS22
TIMER/COUNTER2 CLOCK SOURCE

clkT2
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main
system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Apply-
ing an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clk T2S /8, clk T2S /32, clk T2S /64,
clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
6.15.10.1 General Timer/Counter Control Register – GTCCR

Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R R R R R R/W R/W
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchro-
nous mode, the bit will remain one until the prescaler has been reset. The bit will not be
cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM:
Timer/Counter Synchronization Mode” on page 133 for a description of the Timer/Counter
Synchronization mode.
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6.16 Serial Peripheral Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATA6612/ATA6613 and peripheral devices or between several AVR devices. The
ATA6612/ATA6613 SPI includes the following features:
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
The USART can also be used in Master SPI mode (see “USART in SPI Mode” on page 220).
The PRSPI bit in “Power Reduction Register - PRR” on page 66 must be written to zero to
enable SPI module.
Figure 6-65. SPI Block Diagram(1)

S
MISO
M
XTAL M MOSI
MSB LSB
PIN CONTROL LOGIC

8 BIT SHIFT REGISTER S
READ DATA BUFFER

DIVIDER
/2/4/8/16/32/64/128
CLOCK
SPI CLOCK (MASTER)
SELECT CLOCK S SCK
LOGIC M
SPI2X
SPR0
SPR1
SS
DORD
MSTR
SPE
MSTR
SPI CONTROL SPE
DORD
MSTR
CPHA
CPOL
SPR1
SPR0
WCOL
SPI2X
SPIE
SPIF
SPE
SPI STATUS REGISTER SPI CONTROL REGISTER
8 8
SPI INTERRUPT INTERNAL

REQUEST DATA BUS
Note: 1. Refer to Table 6-32 on page 97 for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 6-66. The sys-
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective shift Registers, and the Master generates
the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-
ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 6-66. SPI Master-slave Interconnection

MSB MASTER LSB MISO MISO MSB SLAVE LSB
8 BIT SHIFT REGISTER 8 BIT SHIFT REGISTER
MOSI MOSI
SHIFT
ENABLE
SPI SCK SCK

CLOCK GENERATOR
SS SS
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
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In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table 6-66. For more details on automatic port overrides, refer to “Alternate Port
Functions” on page 95.
Table 6-66. SPI Pin Overrides(1)

Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Input
MISO Input User Defined
SCK User Defined Input
SS User Defined Input
Note: 1. See “Alternate Functions of Port B” on page 97 for a detailed description of how to define the
direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI
with DDB5 and DDR_SPI with DDRB.
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SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out SPDR,r16
Wait_Transmit:
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)

{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
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The following code examples show how to initialize the SPI as a Slave and how to perform a
simple reception.
SPI_SlaveInit:
; Set MISO output, all others input
ldi r17,(1<<DD_MISO)
out DDR_SPI,r17
; Enable SPI
ldi r17,(1<<SPE)
out SPCR,r17
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
; Read received data and return
in r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return Data Register */
return SPDR;
}
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6.16.1 SS Pin Functionality
6.16.1.1 Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin
is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
6.16.1.2 Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG
is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
mode.
6.16.1.3 SPI Control Register – SPCR

Bit 7 6 5 4 3 2 1 0
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and
the if the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any
SPI operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
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• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is
low when idle. Refer to Figure 6-67 and Figure 6-68 for an example. The CPOL functionality
is summarized below:
Table 6-67. CPOL Functionality

CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising
• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 6-67 and Figure 6-68 for an example.
The CPOL functionality is summarized below:
Table 6-68. CPHA Functionality

CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0
have no effect on the Slave. The relationship between SCK and the Oscillator Clock fre-
quency fosc is shown in the following table:
Table 6-69. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency
0 0 0 fosc/4
0 0 1 fosc/16
0 1 0 fosc/64
0 1 1 fosc/128
1 0 0 fosc/2
1 0 1 fosc/8
1 1 0 fosc/32
1 1 1 fosc/64
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6.16.1.4 SPI Status Register – SPSR

Bit 7 6 5 4 3 2 1 0
SPIF WCOL – – – – – SPI2X SPSR
Read/Write R R R R R R R R/W
• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the
SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared
by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register
(SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see Table 6-69 on page 190). This means that the minimum SCK
period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only
guaranteed to work at fosc/4 or lower.
The SPI interface on the ATA6612/ATA6613 is also used for program memory and
EEPROM downloading or uploading. See “Serial Downloading” on page 315 for serial pro-
gramming and verification.
6.16.1.5 SPI Data Register – SPDR

Bit 7 6 5 4 3 2 1 0
MSB LSB SPDR
Initial Value X X X X X X X X Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
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6.16.2 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
6-67 and Figure 6-68. Data bits are shifted out and latched in on opposite edges of the SCK sig-
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 6-67 and Table 6-68, as done below.
Table 6-70. CPOL Functionality

Leading Edge Trailing eDge SPI Mode
CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0
CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1
CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2
CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3
Figure 6-67. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB
Figure 6-68. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB
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6.17 USART0
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
The USART can also be used in Master SPI mode (see “USART in SPI Mode” on page 220. The
Power Reduction USART bit, PRUSART0, in “Power Reduction Register - PRR” on page 66
must be disabled by writing a logical zero to it.
6.17.1 Overview
A simplified block diagram of the USART Transmitter is shown in Figure 6-69 on page 194. CPU
accessible I/O Registers and I/O pins are shown in bold.
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Figure 6-69. USART Block Diagram(1)
Clock Generator
UBRRn [H:L]
OSC
BAUD RATE GENERATOR
SYNC LOGIC PIN

XCKn
CONTROL
Transmitter
TX
UDRn(Transmit)
CONTROL
PARITY
GENERATOR
DATA BUS
PIN
TRANSMIT SHIFT REGISTER TxDn
CONTROL
Receiver
CLOCK RX
RECOVERY CONTROL
DATA PIN
RECEIVE SHIFT REGISTER RxDn
RECOVERY CONTROL
PARITY
UDRn(Receive) CHECKER
UCSRnA UCSRnB UCSRnC
Note: 1. Refer to Table 6-38 on page 104 for USART0 pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
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6.17.2 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 6-70 shows a block diagram of the clock generation logic.
Figure 6-70. Clock Generation Logic, Block Diagram

UBRRn
U2Xn
foscn
Prescaling UBRRn+1
/2 /4 /2
Down-Counter 0
1
0
OSC txclk
1
DDR_XCKn
Sync Edge
xcki Register Detector 0
XCKn UMSELn
xcko 1
Pin
DDR_XCKn UCPOLn 1
rxclk
0
Signal description:
txclk Transmitter clock (Internal Signal).
rxclk Receiver base clock (Internal Signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave
operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc XTAL pin frequency (System Clock).
6.17.2.1 Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to Figure 6-70.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The Transmitter divides the
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
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Table 6-71 contains equations for calculating the baud rate (in bits per second) and for calculat-
ing the UBRRn value for each mode of operation using an internally generated clock source.
Table 6-71. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud Equation for Calculating UBRRn
Operating Mode Rate(1) Value
f OSC
UBRRn = -----------------------
-–1
16BAUD
f OSC
Asynchronous Normal mode BAUD = -----------------------------------------
-
(U2Xn = 0) 16 ( UBRRn + 1 )
f OSC
UBRRn = -------------------
-–1
8BAUD
Asynchronous Double f OSC

Speed mode (U2Xn = 1) BAUD = --------------------------------------
-
8 ( UBRRn + 1 )
f OSC
UBRRn = -------------------
-–1
2BAUD
f OSC
Synchronous Master mode BAUD = --------------------------------------
-
2 ( UBRRn + 1 )
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 6-79 on
page 218 (see “Examples of UBRRn Settings for Commonly Used Oscillator Frequencies” on
page 218).
6.17.2.2 Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
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6.17.2.3 External Clock

External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 6-70 on page 195 for details.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
f OSC
f XCK < -----------
4
Note that fosc depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
6.17.2.4 Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 6-71. Synchronous Mode XCKn Timing
UCPOL = 1 XCK
RxD / TxD
Sample
UCPOL = 0 XCK
RxD / TxD
Sample
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As Figure 6-71 shows, when UCPOLn is zero the data will be changed at
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
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6.17.3 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 6-72 illustrates the possible combinations of the frame formats. Bits inside brackets are
optional.
Figure 6-72. Frame Formats
FRAME
(IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE)
St Start bit, always low.

(n) Data bits (0 to 8).
P Parity bit. Can be odd or even.
Sp Stop bit, always high.
IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line
must be high.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores
the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the
first stop bit is zero.
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6.17.3.1 Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
P even = d n – 1 ⊕ …⊕ d 3 ⊕ d2 ⊕ d1 ⊕ d0 ⊕ 0
P odd = d n – 1 ⊕ …⊕ d 3 ⊕ d2 ⊕ d1 ⊕ d0 ⊕ 1
Peven Parity bit using even parity

Podd Parity bit using odd parity
dn Data bit n of the character
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
6.17.4 USART Initialization

The USART has to be initialized before any communication can take place. The initialization pro-
cess normally consists of setting the baud rate, setting frame format and enabling the
Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no
ongoing transmissions during the period the registers are changed. The TXCn Flag can be used
to check that the Transmitter has completed all transfers, and the RXC Flag can be used to
check that there are no unread data in the receive buffer. Note that the TXCn Flag must be
cleared before each transmission (before UDRn is written) if it is used for this purpose.
The following simple USART initialization code examples show one assembly and one C func-
tion that are equal in functionality. The examples assume asynchronous operation using polling
(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16
Registers.
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USART_Init:
; Set baud rate
out UBRRnH, r17
out UBRRnL, r16
; Enable receiver and transmitter
ldi r16, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r16
; Set frame format: 8data, 2stop bit
ldi r16, (1<<USBSn)|(3<<UCSZn0)
out UCSRnC,r16
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
/* Set baud rate */
UBRRnH = (unsigned char)(baud>>8);
UBRRnL = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set frame format: 8data, 2stop bit */
UCSRnC = (1<<USBSn)|(3<<UCSZn0);
}
More advanced initialization routines can be made that include frame format as parameters, dis-
able interrupts and so on. However, many applications use a fixed setting of the baud and
control registers, and for these types of applications the initialization code can be placed directly
in the main routine, or be combined with initialization code for other I/O modules.
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6.17.5 Data Transmission – The USART Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB
Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid-
den by the USART and given the function as the Transmitter’s serial output. The baud rate,
mode of operation and frame format must be set up once before doing any transmissions. If syn-
chronous operation is used, the clock on the XCKn pin will be overridden and used as
transmission clock.
6.17.5.1 Sending Frames with 5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The
CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the
transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new
frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or
immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is
loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,
U2Xn bit or by XCKn depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the
Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-
nificant bits written to the UDRn are ignored. The USART has to be initialized before the function
can be used. For the assembly code, the data to be sent is assumed to be stored in Register
R16.
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out UDRn,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) )
;
/* Put data into buffer, sends the data */
UDRn = data;
}
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,
the interrupt routine writes the data into the buffer.
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6.17.5.2 Sending Frames with 9 Data Bit
If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in
UCSRnB before the low byte of the character is written to UDRn. The following code examples
show a transmit function that handles 9-bit characters. For the assembly code, the data to be
sent is assumed to be stored in registers R17:R16.
Assembly Code Example(1)(2)
USART_Transmit:
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Copy 9th bit from r17 to TXB8
cbi UCSRnB,TXB8
sbrc r17,0
sbi UCSRnB,TXB8
; Put LSB data (r16) into buffer, sends the data
out UDRn,r16
ret
C Code Example(1)(2)
void USART_Transmit( unsigned int data )
{
while ( !( UCSRnA & (1<<UDREn))) )
;
/* Copy 9th bit to TXB8 */
UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRnB |= (1<<TXB8);
UDRn = data;
}
Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-
tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used
after initialization.
2. The example code assumes that the part specific header file is included.
The ninth bit can be used for indicating an address frame when using multi processor communi-
cation mode or for other protocol handling as for example synchronization.
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6.17.5.3 Transmitter Flags and Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register Empty
(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Register. For compat-
ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the
USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
transmission is used, the Data Register Empty interrupt routine must either write new data to
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART
Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt
is executed.
6.17.5.4 Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
6.17.5.5 Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed, i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxDn pin.
6.17.6 Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn
pin is overridden by the USART and given the function as the Receiver’s serial input. The baud
rate, mode of operation and frame format must be set up once before any serial reception can
be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer
clock.
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6.17.6.1 Receiving Frames with 5 to 8 Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register
until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.
When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift
Register, the contents of the Shift Register will be moved into the receive buffer. The receive
buffer can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the
Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant
bits of the data read from the UDRn will be masked to zero. The USART has to be initialized
before the function can be used.

USART_Receive:
; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get and return received data from buffer */
return UDRn;
}
The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,
before reading the buffer and returning the value.
6.17.6.2 Receiving Frames with 9 Data Bits

If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in
UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and
UPEn Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the
UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n,
FEn, DORn and UPEn bits, which all are stored in the FIFO, will change.
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The following code example shows a simple USART receive function that handles both nine bit
characters and the status bits.
USART_Receive:
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get status and 9th bit, then data from buffer
in r18, UCSRnA
in r17, UCSRnB
in r16, UDRn
; If error, return -1
andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
breq USART_ReceiveNoError
ldi r17, HIGH(-1)
ldi r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr r17
andi r17, 0x01
ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRnA;
resh = UCSRnB;
resl = UDRn;
/* If error, return -1 */
if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
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The receive function example reads all the I/O Registers into the Register File before any com-
putation is done. This gives an optimal receive buffer utilization since the buffer location read will
be free to accept new data as early as possible.
6.17.6.3 Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf-
fer. This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),
the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive
Complete interrupt will be executed as long as the RXCn Flag is set (provided that global inter-
rupts are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-
rupt will occur once the interrupt routine terminates.
6.17.6.4 Receiver Error Flags

The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and
Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is
that they are located in the receive buffer together with the frame for which they indicate the
error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the
receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.
Another equality for the Error Flags is that they can not be altered by software doing a write to
the flag location. However, all flags must be set to zero when the UCSRnA is written for upward
compatibility of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),
and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn
Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,
except for the first, stop bits. For compatibility with future devices, always set this bit to zero
when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A
Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-
ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there
was one or more serial frame lost between the frame last read from UDRn, and the next frame
read from UDRn. For compatibility with future devices, always write this bit to zero when writing
to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see “Parity Bit Calculation” on page 199 and “Parity Checker” on page 207.
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6.17.6.5 Parity Checker

The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par-
ity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software
to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.
6.17.6.6 Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will
no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
6.17.6.7 Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.

USART_Flush:
sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}
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6.17.7 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
6.17.7.1 Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 6-73
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Figure 6-73. Start Bit Sampling
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), to decide if a valid start bit is received. If two or more of these three samples have logical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
6.17.7.2 Asynchronous Data Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode. Figure 6-74 on page 209 shows the sampling of the
data bits and the parity bit. Each of the samples is given a number that is equal to the state of
the recovery unit.
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Figure 6-74. Sampling of Data and Parity Bit
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 6-75 shows the sampling of the stop bit and the earliest possible beginning of the start bit
of the next frame.
Figure 6-75. Stop Bit Sampling and Next Start Bit Sampling
RxD STOP 1 (A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 6-75. For Double Speed mode the first low level must be delayed to
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
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6.17.7.3 Asynchronous Operational Range
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 6-72) base frequency, the Receiver will not be able to synchronize the frames to the start
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
( D + 1 )S ( D + 2 )S
R slow = --------------------------------------------- R fast = -----------------------------------
S – 1 + D × S + SF ( D + 1 )S + S M
D Sum of character size and parity size (D = 5 to 10 bit)

S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
SF First sample number used for majority voting. SF = 8 for normal speed and SF = 4
for Double Speed mode.
SM Middle sample number used for majority voting. SM = 9 for normal speed and
SM = 5 for Double Speed mode.
Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be
accepted in relation to the receiver baud rate.
Table 6-72 and Table 6-73 on page 211 list the maximum receiver baud rate error that can be
tolerated. Note that Normal Speed mode has higher toleration of baud rate variations.
Table 6-72. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2Xn = 0)
D Recommended Max
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Receiver Error (%)
5 93.20 106.67 +6.67/-6.8 ± 3.0
6 94.12 105.79 +5.79/-5.88 ± 2.5
7 94.81 105.11 +5.11/-5.19 ± 2.0
8 95.36 104.58 +4.58/-4.54 ± 2.0
9 95.81 104.14 +4.14/-4.19 ± 1.5
10 96.17 103.78 +3.78/-3.83 ± 1.5
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Table 6-73. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2Xn = 1)
D Recommended Max
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Receiver Error (%)
5 94.12 105.66 +5.66/-5.88 ± 2.5
6 94.92 104.92 +4.92/-5.08 ± 2.0
7 95.52 104,35 +4.35/-4.48 ± 1.5
8 96.00 103.90 +3.90/-4.00 ± 1.5
9 96.39 103.53 +3.53/-3.61 ± 1.5
10 96.70 103.23 +3.23/-3.30 ± 1.0
The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The Receiver’s system clock
(XTAL) will always have some minor instability over the supply voltage range and the tempera-
ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a
resonator the system clock may differ more than 2% depending of the resonators tolerance. The
second source for the error is more controllable. The baud rate generator can not always do an
exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value
that gives an acceptable low error can be used if possible.
6.17.8 Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering
function of incoming frames received by the USART Receiver. Frames that do not contain
address information will be ignored and not put into the receive buffer. This effectively reduces
the number of incoming frames that has to be handled by the CPU, in a system with multiple
MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn
setting, but has to be used differently when it is a part of a system utilizing the Multi-processor
Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-
cates if the frame contains data or address information. If the Receiver is set up for frames with
nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When
the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
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6.17.8.1 Using MPCMn
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The
ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in
UCSRnA is set).
2. The Master MCU sends an address frame, and all slaves receive and read this frame.
In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If
so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and
keeps the MPCMn setting.
4. The addressed MCU will receive all data frames until a new address frame is received.
The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets
the MPCMn bit and waits for a new address frame from master. The process then
repeats from 2.
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes
full-duplex operation difficult since the Transmitter and Receiver uses the same character size
setting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
6.17.9 USART Register Description
6.17.9.1 USART I/O Data Register n– UDRn

Bit 7 6 5 4 3 2 1 0
RXB[7:0] UDRn (Read)
TXB[7:0] UDRn (Write)
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
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The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Mod-
ify-Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions
(SBIC and SBIS), since these also will change the state of the FIFO.
6.17.9.2 USART Control and Status Register n A – UCSRnA

Bit 7 6 5 4 3 2 1 0
RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn UCSRnA
Read/Write R R/W R R R R R/W R/W
• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled,
the receive buffer will be flushed and consequently the RXCn bit will become zero. The
RXCn Flag can be used to generate a Receive Complete interrupt (see description of the
RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out
and there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag
bit is automatically cleared when a transmit complete interrupt is executed, or it can be
cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit Com-
plete interrupt (see description of the TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can
generate a Data Register Empty interrupt (see description of the UDRIEn bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FEn: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received.
I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid
until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data
is one. Always set this bit to zero when writing to UCSRnA.
• Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the
receive buffer is full (two characters), it is a new character waiting in the Receive Shift Reg-
ister, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read.
Always set this bit to zero when writing to UCSRnA.
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• Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and
the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive
buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively
doubling the transfer rate for asynchronous communication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written
to one, all the incoming frames received by the USART Receiver that do not contain address
information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more
detailed information see “Multi-processor Communication Mode” on page 211.
6.17.9.3 USART Control and Status Register n B – UCSRnB

Bit 7 6 5 4 3 2 1 0
RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n UCSRnB
Read/Write R/W R/W R/W R/W R/W R/W R R/W
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt
will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG
is written to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing
TXENn to zero) will not become effective until ongoing and pending transmissions are com-
pleted, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain
data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port.
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• Bit 2 – UCSZn2: Character Size n

The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with
nine data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDRn.
6.17.9.4 USART Control and Status Register n C – UCSRnC

Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
• Bits 7:6 – UMSELn1:0 USART Mode Select

These bits select the mode of operation of the USARTn as shown in Table 6-74.
Table 6-74. UMSELn Bits Settings

UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)(1)
Note: 1. See “USART in SPI Mode” on page 220 for full description of the Master SPI Mode (MSPIM)
operation
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter
will automatically generate and send the parity of the transmitted data bits within each
frame. The Receiver will generate a parity value for the incoming data and compare it to the
UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 6-75. UPMn Bits Settings

UPMn1 UPMn0 Parity Mode
0 0 Disabled
0 1 Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
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Table 6-76. USBS Bit Settings
USBSn Stop Bit(s)
0 1-bit
1 2-bit
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 6-77. UCSZn Bits Settings

UCSZn2 UCSZn1 UCSZn0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 9-bit
• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode
is used. The UCPOLn bit sets the relationship between data output change and data input
sample, and the synchronous clock (XCKn).
Table 6-78. UCPOLn Bit Settings

Transmitted Data Changed (Output of Received Data Sampled (Input on RxDn
UCPOLn TxDn Pin) Pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge
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6.17.9.5 USART Baud Rate Registers – UBRRnL and UBRRnH

Bit 15 14 13 12 11 10 9 8
– – – – UBRRn[11:8] UBRRnH
UBRRn[7:0] UBRRnL
7 6 5 4 3 2 1 0
R R R R R/W R/W R/W R/W
Read/Write
0 0 0 0 0 0 0 0
Initial Value
0 0 0 0 0 0 0 0
• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must
be written to zero when UBRRnH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the
four most significant bits, and the UBRRnL contains the eight least significant bits of the
USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted
if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud
rate prescaler.
6.17.10 Examples of Baud Rate Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRRn settings in Table 6-79 on page 218.
UBRRn values which yield an actual baud rate differing less than 0.5% from the target baud
rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will have less
noise resistance when the error ratings are high, especially for large serial frames (see “Asyn-
chronous Operational Range” on page 210). The error values are calculated using the following
equation:
BaudRate Closest Match
Error[%] = ⎛ -------------------------------------------------------
- – 1⎞ • 100%
⎝ BaudRate ⎠
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Table 6-79. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz
Baud
Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
(bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%
4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%
9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%
14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%
19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%
28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%
38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%
57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%
76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%
115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%
230.4k – – – – – – 0 0.0% – – – –
250k – – – – – – – – – – 0 0.0%
(1)
Max. 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps
Note: 1. UBRRn = 0, Error = 0.0%
Table 6-80. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%
4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%
9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0%
14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%
19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%
28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%
38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%
57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%
76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%
115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%
230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%
250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%
0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%
1M – – – – – – – – – – 0 -7.8%
Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps
1. UBRRn = 0, Error = 0.0%
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Baud
2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%
4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%
9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%
14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%
19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%
28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%
38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%
57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%
76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%
115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%
230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%
250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%
0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%
1M – – 0 0.0% – – – – 0 -7.8% 1 -7.8%
(1)
Max. 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps
1. UBRRn = 0, Error = 0.0%
Baud
2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%
4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%
9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%
14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%
19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%
28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%
38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%
57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%
76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%
115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%
230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%
250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%
0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%
1M 0 0.0% 1 0.0% – – – – – – – –
(1)
Max. 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps
1. UBRRn = 0, Error = 0.0%
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6.18 USART in SPI Mode
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow-
ing features:
• Full Duplex, Three-wire Synchronous Data Transfer
• Master Operation
• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
• LSB First or MSB First Data Transfer (Configurable Data Order)
• Queued Operation (Double Buffered)
• High Resolution Baud Rate Generator
• High Speed Operation (fXCKmax = fCK/2)
• Flexible Interrupt Generation
6.18.1 Overview
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
6.18.2 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations (see Table 6-83 on page 221).
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Table 6-83. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud Equation for Calculating UBRRn
Operating Mode Rate(1) Value
Synchronous Master f OSC f OSC

BAUD = --------------------------------------
- UBRRn = -------------------
-–1
mode 2 ( UBRRn + 1 ) 2BAUD
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095)
6.18.3 SPI Data Modes and Timing

There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 6-76 on page 221. Data bits are shifted out and latched in on opposite edges of
the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and
UCPHAn functionality is summarized in Table 6-84. Note that changing the setting of any of
these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 6-84. UCPOLn and UCPHAn Functionality-

UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)
1 1 3 Setup (Falling) Sample (Rising)
Figure 6-76. UCPHAn and UCPOLn Data Transfer Timing Diagrams

UCPOL=0 UCPOL=1
UCPHA=1
XCK XCK
Data setup (TXD) Data setup (TXD)
Data sample (RXD) Data sample (RXD)
XCK XCK
UCPHA=0
Data setup (TXD) Data setup (TXD)
Data sample (RXD) Data sample (RXD)
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6.18.4 Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM
mode has two valid frame formats:
• 8-bit data with MSB first
• 8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete
frame is transmitted, a new frame can directly follow it, or the communication line can be set to
an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The
Receiver and Transmitter use the same setting. Note that changing the setting of any of these
bits will corrupt all ongoing communication for both the Receiver and Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit com-
plete interrupt will then signal that the 16-bit value has been shifted out.
6.18.4.1 USART MSPIM Initialization

The USART in MSPIM mode has to be initialized before any communication can take place. The
initialization process normally consists of setting the baud rate, setting master mode of operation
(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the
Receiver. Only the transmitter can operate independently. For interrupt driven USART opera-
tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when
doing the initialization.
Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be
zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the
UBRRn must then be written to the desired value after the transmitter is enabled, but before the
first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces-
sary if the initialization is done immediately after a reset since UBRRn is reset to zero.
Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that
there is no ongoing transmissions during the period the registers are changed. The TXCn Flag
can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can
be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag
must be cleared before each transmission (before UDRn is written) if it is used for this purpose.
The following simple USART initialization code examples show one assembly and one C func-
tion that are equal in functionality. The examples assume polling (no interrupts enabled). The
baud rate is given as a function parameter. For the assembly code, the baud rate parameter is
assumed to be stored in the r17:r16 registers.
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USART_Init:
clr r18
out UBRRnH,r18
out UBRRnL,r18
; Setting the XCKn port pin as output, enables master mode.
sbi XCKn_DDR, XCKn
; Set MSPI mode of operation and SPI data mode 0.
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
out UCSRnC,r18
; Enable receiver and transmitter.
ldi r18, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r18
; Set baud rate.
; IMPORTANT: The Baud Rate must be set after the transmitter is enabled!
out UBRRnH, r17
out UBRRnL, r18
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
UBRRn = 0;
/* Setting the XCKn port pin as output, enables master mode. */
XCKn_DDR |= (1<<XCKn);
/* Set MSPI mode of operation and SPI data mode 0. */
UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);
/* Enable receiver and transmitter. */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set baud rate. */
/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled
*/
UBRRn = baud;
}
Note: 1. The example code assumes that the part specific header file is included. For I/O Registers
located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must
be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS"
combined with "SBRS", "SBRC", "SBR", and "CBR".
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6.18.5 Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in
the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation
of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling
the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given
the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer
clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-
ing to the UDRn I/O location. This is the case for both sending and receiving data since the
transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buf-
fer to the shift register when the shift register is ready to send a new frame.
Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must
be read once for each byte transmitted. The input buffer operation is identical to normal USART
mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buf-
fer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDRn
is not read before all transfers are completed, then byte 3 to be received will be lost, and not byte
1.
The following code examples show a simple USART in MSPIM mode transfer function based on
polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The
USART has to be initialized before the function can be used. For the assembly code, the data to
be sent is assumed to be stored in Register R16 and the data received will be available in the
same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. The function then waits for data to be present
in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the
value.
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USART_MSPIM_Transfer:
sbis UCSRnA, UDREn
rjmp USART_MSPIM_Transfer
; Put data (r16) into buffer, sends the data
out UDRn,r16
USART_MSPIM_Wait_RXCn:
sbis UCSRnA, RXCn
rjmp USART_MSPIM_Wait_RXCn
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
while ( !( UCSRnA & (1<<UDREn)) );
UDRn = data;
while ( !(UCSRnA & (1<<RXCn)) );
/* Get and return received data from buffer */
return UDRn;
}
Note: 1. The example code assumes that the part specific header file is included. For I/O Registers
located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must
be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS"
combined with "SBRS", "SBRC", "SBR", and "CBR".
6.18.5.1 Transmitter and Receiver Flags and Interrupts

The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode
are identical in function to the normal USART operation. However, the receiver error status flags
(FE, DOR, and PE) are not in use and is always read as zero.
6.18.5.2 Disabling the Transmitter or Receiver

The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to
the normal USART operation.
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6.18.6 USART MSPIM Register Description
The following section describes the registers used for SPI operation using the USART.
6.18.6.1 USART MSPIM I/O Data Register - UDRn

The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
normal USART operation (see “USART I/O Data Register n– UDRn” on page 212).
6.18.6.2 USART MSPIM Control and Status Register n A - UCSRnA
Bit 7 6 5 4 3 2 1 0
RXCn TXCn UDREn - - - - - UCSRnA
Read/Write R/W R/W R/W R R R R R
• Bit 7 - RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled,
the receive buffer will be flushed and consequently the RXCn bit will become zero. The
RXCn Flag can be used to generate a Receive Complete interrupt (see description of the
RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out
and there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag
bit is automatically cleared when a transmit complete interrupt is executed, or it can be
cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit Com-
plete interrupt (see description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can
generate a Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set
after a reset to indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnA is written.
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6.18.6.3 USART MSPIM Control and Status Register n B - UCSRnB
Bit 7 6 5 4 3 2 1 0
RXCIEn TXCIEn UDRIE RXENn TXENn - - - UCSRnB
Read/Write R/W R/W R/W R/W R/W R R R
• Bit 7 - RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt
will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is
written to one and the UDREn bit in UCSRnA is set.
• Bit 4 - RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will over-
ride normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush
the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and
TXENn=0) has no meaning since it is the transmitter that controls the transfer clock and
since only master mode is supported.
• Bit 3 - TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing
TXENn to zero) will not become effective until ongoing and pending transmissions are com-
pleted, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain
data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port.
devices, these bits must be written to zero when UCSRnB is written.
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6.18.6.4 USART MSPIM Control and Status Register n C - UCSRnC
Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn UCSRnC
Read/Write R/W R/W R R R R/W R/W R/W
• Bit 7:6 - UMSELn1:0: USART Mode Select

These bits select the mode of operation of the USART as shown in Table 6-85. See “USART
Control and Status Register n C – UCSRnC” on page 215 for full description of the normal
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM
is enabled.
Table 6-85. UMSELn Bits Settings

UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)

devices, these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of
the data word is transmitted first. Refer to the section “Frame Formats” on page 198 for
details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing
(last) edge of XCKn. Refer to the section “SPI Data Modes and Timing” on page 221 for
details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the section “SPI Data
Modes and Timing” on page 221 for details.
USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation (see “USART Baud Rate Registers – UBRRnL and UBRRnH” on page 217).
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6.18.7 AVR USART MSPIM versus AVR SPI

The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
• Master mode timing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
• The UCPHAn bit functionality is identical to the SPI CPHA bit.
• The UDORDn bit functionality is identical to the SPI DORD bit.
However, since the USART in MSPIM mode reuses the USART resources, the use of the
USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of
the control register bits, and that only master operation is supported by the USART in MSPIM
mode, the following features differ between the two modules:
• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no
buffer.
• The USART in MSPIM mode receiver includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is
achieved by setting UBRRn accordingly.
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 6-86.
Table 6-86. Comparison of USART in MSPIM Mode and SPI Pins.

USART_MSPIM SPI Comment
TxDn MOSI Master Out only
RxDn MISO Master In only
XCKn SCK (Functionally identical)
(N/A) SS Not supported by USART in MSPIM
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6.19 2-wire Serial Interface
6.19.1 Features
• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up When AVR is in Sleep Mode
6.19.2 2-wire Serial Interface Bus Definition

The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 6-77. TWI Bus Interconnection

VCC
Device 1 Device 2 Device 3 ........ Device n R1 R2
SDA
SCL
6.19.2.1 TWI Terminology

The following definitions are frequently encountered in this section.
Table 6-87. TWI Terminology

Term Description
The device that initiates and terminates a transmission. The Master also generates the
Master
SCL clock.
Slave The device addressed by a Master.
Transmitter The device placing data on the bus.
Receiver The device reading data from the bus.
The PRTWI bit in “Power Reduction Register - PRR” on page 66 must be written to zero to
enable the 2-wire Serial Interface.
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6.19.2.2 Electrical Interconnection

As depicted in Figure 6-77 on page 230, both bus lines are connected to the positive supply volt-
age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or
open-collector. This implements a wired-AND function which is essential to the operation of the
interface. A low level on a TWI bus line is generated when one or more TWI devices output a
zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resis-
tors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in “2-wire Serial Interface Characteristics” on page 324. Two
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
6.19.3 Data Transfer and Frame Format
6.19.3.1 Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 6-78. Data Validity
SDA
SCL
Data Stable Data Stable
Data Change
6.19.3.2 START and STOP Conditions

The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signalled by changing the level of the SDA
line when the SCL line is high.
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Figure 6-79. START, REPEATED START and STOP Conditions
SDA
SCL
START STOP START REPEATED START STOP
6.19.3.3 Address Packet Format

All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one
READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera-
tion is to be performed, otherwise a write operation should be performed. When a Slave
recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL
(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-
ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then
transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An
address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or
SLA+W, respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the
designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK
cycle. A general call is used when a Master wishes to transmit the same message to several
slaves in the system. When the general call address followed by a Write bit is transmitted on the
bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.
The following data packets will then be received by all the slaves that acknowledged the general
call. Note that transmitting the general call address followed by a Read bit is meaningless, as
this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 6-80. Address Packet Format
Addr MSB Addr LSB R/W ACK
SDA
SCL
1 2 7 8 9
START
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6.19.3.4 Data Packet Format

All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 6-81. Data Packet Format
Data MSB Data LSB ACK

Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1 2 7 8 9
STOP, REPEATED
SLA+R/W Data Byte START or Next
Data Byte
6.19.3.5 Combining Address and Data Packets into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 6-82 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
Figure 6-82. Typical Data Transmission
Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK
SDA
SCL
1 2 7 8 9 1 2 7 8 9
START SLA+R/W Data Byte STOP
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6.19.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slaves,
i.e. the data being transferred on the bus must not be corrupted.
• Different masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Figure 6-83. SCL Synchronization Between Multiple Masters

TAlow TAhigh
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TBlow TBhigh
Masters Start Masters Start

Counting Low Period Counting High Period
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Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 6-84. Arbitration Between Two Masters

START Master A Loses
Arbitration, SDAA ≠ SDA
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
Note that arbitration is not allowed between:

• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
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6.19.5 Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 6-85. All registers
drawn in a thick line are accessible through the AVR data bus.
Figure 6-85. Overview of the TWI Module
SCL SDA
Slew-rate Spike Slew-rate Spike

Control Filter Control Filter
Bus Interface Unit Bit Rate Generator
START / STOP
Spike Suppression Prescaler
Control
Address/Data Shift Bit Rate Register

Arbitration detection Ack
Register (TWDR) (TWBR)
Address Match Unit Control Unit
Address Register Status Register Control Register
TWI Unit
(TWAR) (TWSR) (TWCR)
State Machine and

Address Comparator
Status control
6.19.5.1 SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
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6.19.5.2 Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
CPU Clock frequency

SCL frequency = --------------------------------------------------------------------------------------------
16 + 2(TWBR) ⋅ ( PrescalerValue )
• TWBR = Value of the TWI Bit Rate Register.

• PrescalerValue = Value of the prescaler (see Table 6-88 on page 240).
Note: TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the
Master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob-
lem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a Slave (a
Slave does not need to be connected to the bus for the condition to happen).
6.19.5.3 Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
6.19.5.4 Address Match Unit

The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0)
occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-
tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the
only enabled interrupt when entering Power-down.
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6.19.5.5 Control Unit
The Control unit monitors the TWI bus and generates responses corresponding to settings in the
TWI Control Register (TWCR). When an event requiring the attention of the application occurs
on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta-
tus Register (TWSR) is updated with a status code identifying the event. The TWSR only
contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,
the TWSR contains a special status code indicating that no relevant status information is avail-
able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application
software to complete its tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition.
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a Slave.
• When a bus error has occurred due to an illegal START or STOP condition.
6.19.6 TWI Register Description
6.19.6.1 TWI Bit Rate Register – TWBR

Bit 7 6 5 4 3 2 1 0
TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR
• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a fre-
quency divider which generates the SCL clock frequency in the Master modes. See “Bit
Rate Generator Unit” on page 237 for calculating bit rates.
6.19.6.2 TWI Control Register – TWCR

Bit 7 6 5 4 3 2 1 0
TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR
Read/Write R/W R/W R/W R/W R R/W R R/W
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector.
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While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be
cleared by software by writing a logic one to it. Note that this flag is not automatically cleared
by hardware when executing the interrupt routine. Also note that clearing this flag starts the
operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status
Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this
flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to
one, the ACK pulse is generated on the TWI bus if the following conditions are met:
The device’s own slave address has been received.
A general call has been received, while the TWGCE bit in the TWAR is set.
A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to
one again.
• Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the
2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START
condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP
condition is detected, and then generates a new START condition to claim the bus Master
status. TWSTA must be cleared by software when the START condition has been
transmitted.
• Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared
automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error
condition. This will not generate a STOP condition, but the TWI returns to a well-defined
unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when
TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is writ-
ten to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins,
enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is
switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be
activated for as long as the TWINT Flag is high.
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6.19.6.3 TWI Status Register – TWSR
Bit 7 6 5 4 3 2 1 0
TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR
• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status
codes are described later in this section. Note that the value read from TWSR contains both
the 5-bit status value and the 2-bit prescaler value. The application designer should mask
the prescaler bits to zero when checking the Status bits. This makes status checking inde-
pendent of prescaler setting. This approach is used in this datasheet, unless otherwise
noted.
This bit is reserved and will always read as zero.
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 6-88. TWI Bit Rate Prescaler

TWPS1 TWPS0 Prescaler Value
0 0 1
0 1 4
1 0 16
1 1 64
To calculate bit rates, see “Bit Rate Generator Unit” on page 237. The value of TWPS1..0 is
used in the equation.
6.19.6.4 TWI Data Register – TWDR

Bit 7 6 5 4 3 2 1 0
TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the 2-wire Serial Bus.
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6.19.6.5 TWI (Slave) Address Register – TWAR

Bit 7 6 5 4 3 2 1 0
TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
6.19.6.6 TWI (Slave) Address Mask Register – TWAMR

Bit 7 6 5 4 3 2 1 0
TWAM[6:0] – TWAMR
Read/Write R/W R/W R/W R/W R/W R/W R/W R
• Bits 7..1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR
can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If
the mask bit is set to one then the address match logic ignores the compare between the
incoming address bit and the corresponding bit in TWAR. Figure 6-86 shown the address
match logic in detail.
Figure 6-86. TWI Address Match Logic, Block Diagram
TWAR0
Address
Match
Address
Bit 0
TWAMR0
Address Bit Comparator 0
Address Bit Comparator 6..1

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6.19.7 Using the TWI
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 6-87 is a simple example of how the application can interface to the TWI hardware. In this
example, a Master wishes to transmit a single data byte to a Slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired behavior is also presented.
Figure 6-87. Interfacing the Application to the TWI in a Typical Transmission

3. Check TWSR to see if START was 5. Check TWSR to see if SLA+W was
1. Application sent. Application loads SLA+W into 7. Check TWSR to see if data was sent
sent and ACK received.
Application
writes to TWCR to TWDR, and loads appropriate control and ACK received.
Application loads data into TWDR, and
Action
initiate signals into TWCR, makin sure that Application loads appropriate control
loads appropriate control signals into
transmission of TWINT is written to one, signals to send STOP into TWCR,
TWCR, making sure that TWINT is
START and TWSTA is written to zero. making sure that TWINT is written to one
written to one
TWI bus START SLA+W A Data A STOP
Indicates
4. TWINT set.
Hardware
2. TWINT set. 6. TWINT set. TWINT set

Action
Status code indicates

TWI
Status code indicates Status code indicates

SLA+W sent, ACK
START condition sent data sent, ACK received
received
1. The first step in a TWI transmission is to transmit a START condition. This is done by
writing a specific value into TWCR, instructing the TWI hardware to transmit a START
condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI
will not start any operation as long as the TWINT bit in TWCR is set. Immediately after
the application has cleared TWINT, the TWI will initiate transmission of the START
condition.
2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the START condition has success-
fully been sent.
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3. The application software should now examine the value of TWSR, to make sure that the
START condition was successfully transmitted. If TWSR indicates otherwise, the appli-
cation software might take some special action, like calling an error routine. Assuming
that the status code is as expected, the application must load SLA+W into TWDR.
Remember that TWDR is used both for address and data. After TWDR has been
loaded with the desired SLA+W, a specific value must be written to TWCR, instructing
the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is
described later on. However, it is important that the TWINT bit is set in the value written.
Writing a one to TWINT clears the flag. The TWI will not start any operation as long as
the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT,
the TWI will initiate transmission of the address packet.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the address packet has success-
fully been sent. The status code will also reflect whether a Slave acknowledged the
packet or not.
address packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must load a data packet into TWDR. Subsequently, a specific value
must be written to TWCR, instructing the TWI hardware to transmit the data packet
present in TWDR. Which value to write is described later on. However, it is important
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag.
The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immedi-
ately after the application has cleared TWINT, the TWI will initiate transmission of the
data packet.
6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the data packet has successfully
been sent. The status code will also reflect whether a Slave acknowledged the packet
or not.
data packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must write a specific value to TWCR, instructing the TWI hardware to
transmit a STOP condition. Which value to write is described later on. However, it is
important that the TWINT bit is set in the value written. Writing a one to TWINT clears
the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate transmission
of the STOP condition. Note that TWINT is NOT set after a STOP condition has been
sent.
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Even though this example is simple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
• When the TWI has finished an operation and expects application response, the TWINT Flag
is set. The SCL line is pulled low until TWINT is cleared.
• When the TWINT Flag is set, the user must update all TWI Registers with the value relevant
for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be
transmitted in the next bus cycle.
• After all TWI Register updates and other pending application software tasks have been
completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a
one to TWINT clears the flag. The TWI will then commence executing whatever operation
was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note that the code
below assumes that several definitions have been made, for example by using include-files.
244 ATA6612/ATA6613
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Table 6-89.
Assembly Code Example C Example Comments
ldi r16, (1<<TWINT)|(1<<TWSTA)| TWCR = (1<<TWINT)|(1<<TWSTA)|
1 (1<<TWEN) (1<<TWEN) Send START condition
out TWCR, r16
wait1: while (!(TWCR & (1<<TWINT)))
in r16,TWCR ; Wait for TWINT Flag set. This
2 indicates that the START condition
sbrs r16,TWINT has been transmitted
rjmp wait1
in r16,TWSR if ((TWSR & 0xF8) != START) Check value of TWI Status
andi r16, 0xF8 ERROR(); Register. Mask prescaler bits. If
cpi r16, START status different from START go to
ERROR
brne ERROR
3
ldi r16, SLA_W TWDR = SLA_W;
out TWDR, r16 TWCR = (1<<TWINT) | (1<<TWEN); Load SLA_W into TWDR Register.
Clear TWINT bit in TWCR to start
ldi r16, (1<<TWINT) | (1<<TWEN) transmission of address
out TWCR, r16
wait2: while (!(TWCR & (1<<TWINT))) Wait for TWINT Flag set. This
in r16,TWCR ; indicates that the SLA+W has been
4
sbrs r16,TWINT transmitted, and ACK/NACK has
been received.
rjmp wait2
in r16,TWSR if ((TWSR & 0xF8) != Check value of TWI Status
andi r16, 0xF8 MT_SLA_ACK) Register. Mask prescaler bits. If
cpi r16, MT_SLA_ACK ERROR(); status different from MT_SLA_ACK
go to ERROR
brne ERROR
5
ldi r16, DATA TWDR = DATA;
out TWDR, r16 TWCR = (1<<TWINT) | (1<<TWEN); Load DATA into TWDR Register.
Clear TWINT bit in TWCR to start
ldi r16, (1<<TWINT) | (1<<TWEN) transmission of data
out TWCR, r16
wait3: while (!(TWCR & (1<<TWINT))) Wait for TWINT Flag set. This
in r16,TWCR ; indicates that the DATA has been
6
sbrs r16,TWINT transmitted, and ACK/NACK has
been received.
rjmp wait3
in r16,TWSR if ((TWSR & 0xF8) != Check value of TWI Status
andi r16, 0xF8 MT_DATA_ACK) Register. Mask prescaler bits. If
cpi r16, MT_DATA_ACK ERROR(); status different from
7 MT_DATA_ACK go to ERROR
brne ERROR
ldi r16, (1<<TWINT)|(1<<TWEN)| TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO) (1<<TWSTO); Transmit STOP condition
out TWCR, r16
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6.19.8 Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In Figure 6-89 on page 249 to Figure 6-95 on page 259, circles are used to indicate that the
TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the
prescaler bits masked to zero. At these points, actions must be taken by the application to con-
tinue or complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is
cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate soft-
ware action. For each status code, the required software action and details of the following serial
transfer are given in Table 6-90 on page 248 to Table 6-93 on page 258. Note that the prescaler
bits are masked to zero in these tables.
6.19.8.1 Master Transmitter Mode

In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see Figure 6-88 on page 247). In order to enter a Master mode, a START condition must be
transmitted. The format of the following address packet determines whether Master Transmitter
or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if
SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
246 ATA6612/ATA6613
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Figure 6-88. Data Transfer in Master Transmitter Mode

VCC
Device 1 Device 2
MASTER SLAVE Device 3 ........ Device n R1 R2
TRANSMITTER RECEIVER
SDA
SCL
A START condition is sent by writing the following value to TWCR:

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE
value 1 X 1 0 X 1 0 X
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans-
mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will
then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the
status code in TWSR will be 0x08 (see Table 6-90 on page 248). In order to enter MT mode,
SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
value 1 X 0 0 X 1 0 X
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes
is detailed in Table 6-90 on page 248.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-
ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
value 1 X 0 0 X 1 0 X
This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
value 1 X 0 1 X 1 0 X
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A REPEATED START condition is generated by writing the following value to TWCR:
value 1 X 1 0 X 1 0 X
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-
out losing control of the bus.
Table 6-90. Status codes for Master Transmitter Mode

Status Code Application Software Response
(TWSR) Status of the 2-wire Serial To TWCR
Prescaler Bits Bus and 2-wire Serial
are 0 Interface Hardware To/from TWDR STA STO TWINT TWEA Next Action Taken by TWI Hardware
A START condition has Load SLA+W 0 0 1 X SLA+W will be transmitted;
0x08
been transmitted ACK or NOT ACK will be received
Load SLA+W or 0 0 1 X SLA+W will be transmitted;
A repeated START
ACK or NOT ACK will be received
0x10 condition has been
Load SLA+R 0 0 1 X SLA+R will be transmitted;
transmitted
Logic will switch to Master Receiver mode
Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT
ACK will be received
SLA+W has been No TWDR action or 1 0 1 X Repeated START will be transmitted
0x18 transmitted; No TWDR action or 0 1 1 X STOP condition will be transmitted and
ACK has been received TWSTO Flag will be reset
No TWDR action 1 1 1 X STOP condition followed by a START condition
will be transmitted and TWSTO Flag will be reset
SLA+W has been
No TWDR action or 1 0 1 X Repeated START will be transmitted
transmitted;
0x20 No TWDR action or 0 1 1 X STOP condition will be transmitted and
NOT ACK has been
received TWSTO Flag will be reset
Data byte has been No TWDR action or 1 0 1 X Repeated START will be transmitted
0x28 transmitted; No TWDR action or 0 1 1 X STOP condition will be transmitted and
ACK has been received TWSTO Flag will be reset
No TWDR action 1 1 1 STOP condition followed by a START condition
Data byte has been Repeated START will be transmitted
transmitted; No TWDR action or 1 0 1 X
0x30 No TWDR action or 0 1 1 X STOP condition will be transmitted and
NOT ACK has been
TWSTO Flag will be reset
received
No TWDR action or 0 0 1 X 2-wire Serial Bus will be released and not
Arbitration lost in SLA+W or addressed Slave mode entered
0x38
data bytes No TWDR action 1 0 1 X A START condition will be transmitted when the
bus becomes free
248 ATA6612/ATA6613
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Figure 6-89. Formats and States in the Master Transmitter Mode

MT
Successfull
transmission S SLA W A DATA A P
to a slave
receiver
$08 $18 $28
Next transfer
started with a RS SLA W
repeated start
condition
$10
Not acknowledge R
received after the A P
slave address
$20
MR
Not acknowledge
received after a data A P
byte
$30
Arbitration lost in slave Other master Other master

address or data byte A or A A or A
continues continues
$38 $38
Arbitration lost and Other master

addressed as slave A
continues
To corresponding
$68 $78 $B0 states in slave mode
Any number of data bytes

From master to slave DATA A and their associated acknowledge bits
From slave to master This number (contained in TWSR) corresponds

n to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
6.19.8.2 Master Receiver Mode

In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter
(Slave see Figure 6-90 on page 250). In order to enter a Master mode, a START condition must
be transmitted. The format of the following address packet determines whether Master Transmit-
ter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if
SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
249
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Figure 6-90. Data Transfer in Master Receiver Mode
VCC
Device 1 Device 2
MASTER SLAVE Device 3 ........ Device n R1 R2
RECEIVER TRANSMITTER
SDA
SCL
A START condition is sent by writing the following value to TWCR:

value 1 X 1 0 X 1 0 X
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI
will then test the 2-wire Serial Bus and generate a START condition as soon as the bus
becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-
ware, and the status code in TWSR will be 0x08 (see Table 6-90 on page 248). In order to enter
MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished
by writing the following value to TWCR:
value 1 X 0 0 X 1 0 X
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes
is detailed in Table 6-91 on page 251. Received data can be read from the TWDR Register
when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has
been received. After the last byte has been received, the MR should inform the ST by sending a
NACK after the last received data byte. The transfer is ended by generating a STOP condition or
a repeated START condition. A STOP condition is generated by writing the following value to
TWCR:
value 1 X 0 1 X 1 0 X
A REPEATED START condition is generated by writing the following value to TWCR:

value 1 X 1 0 X 1 0 X
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After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-
out losing control over the bus.
Table 6-91. Status codes for Master Receiver Mode

(TWSR) Status of the 2-wire Serial
To TWCR
A START condition has been Load SLA+R 0 0 1 X SLA+R will be transmitted
0x08
transmitted ACK or NOT ACK will be received
Load SLA+R or 0 0 1 X SLA+R will be transmitted
A repeated START condition ACK or NOT ACK will be received
0x10
has been transmitted Load SLA+W 0 0 1 X SLA+W will be transmitted
Logic will switch to Master Transmitter mode
No TWDR action or 0 0 1 X 2-wire Serial Bus will be released and not
Arbitration lost in SLA+R or addressed Slave mode will be entered
0x38
NOT ACK bit No TWDR action 1 0 1 X A START condition will be transmitted when the
bus becomes free
No TWDR action or 0 0 1 0 Data byte will be received and NOT ACK will be
SLA+R has been transmitted; returned
0x40
ACK has been received No TWDR action 0 0 1 1 Data byte will be received and ACK will be
returned
No TWDR action or 1 0 1 X Repeated START will be transmitted
No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO
SLA+R has been transmitted;
0x48 Flag will be reset
NOT ACK has been received
Read data byte or 0 0 1 0 Data byte will be received and NOT ACK will be
Data byte has been received; returned
0x50
ACK has been returned Read data byte 0 0 1 1 Data byte will be received and ACK will be
returned
Read data byte or 1 0 1 X Repeated START will be transmitted
Data byte has been received; Read data byte or 0 1 1 X STOP condition will be transmitted and TWSTO
0x58 Flag will be reset
NOT ACK has been returned
Read data byte 1 1 1 X STOP condition followed by a START condition
251
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Figure 6-91. Formats and States in the Master Receiver Mode
MR
Successfull
reception S SLA R A DATA A DATA A P
from a slave
receiver
$08 $40 $50 $58
Next transfer
started with a RS SLA R
repeated start
condition
$10
Not acknowledge W
received after the A P
slave address
$48
MT
Arbitration lost in slave Other master Other master
address or data byte A or A A
continues continues
$38 $38
Arbitration lost and Other master

addressed as slave A
continues
To corresponding
$68 $78 $B0
states in slave mode


6.19.8.3 Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see Figure 6-92). All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.
Figure 6-92. Data Transfer in Slave Receiver Mode

VCC
Device 1 Device 2
SLAVE MASTER Device 3 ........ Device n R1 R2
RECEIVER TRANSMITTER
SDA
SCL
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To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
value Device’s Own Slave Address
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),
otherwise it will ignore the general call address.
value 0 1 0 0 0 1 0 X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable
the acknowledgement of the device’s own slave address or the general call address. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in Table 6-92 on
page 254. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in
the Master mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA
after the next received data byte. This can be used to indicate that the Slave is not able to
receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave
address. However, the 2-wire Serial Bus is still monitored and address recognition may resume
at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate
the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and
the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by
writing it to one). Further data reception will be carried out as normal, with the AVR clocks run-
ning as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be
held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these Sleep modes.
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Table 6-92. Status Codes for Slave Receiver Mode
(TWSR) To TWCR
Prescaler Status of the 2-wire Serial
Bits Bus and 2-wire Serial
Own SLA+W has been No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be
0x60 received; returned
ACK has been returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned
Arbitration lost in SLA+R/W as No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be
Master; own SLA+W has been returned
0x68
received; ACK has been
No TWDR action X 0 1 1 Data byte will be received and ACK will be returned
returned
General call address has been No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be
0x70 received; ACK has been returned
returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned
Arbitration lost in SLA+R/W as No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be
Master; General call address returned
0x78
has been received; ACK has No TWDR action X 0 1 1 Data byte will be received and ACK will be returned
been returned
Previously addressed with own Read data byte or X 0 1 0 Data byte will be received and NOT ACK will be
SLA+W; data has been returned
0x80
received; ACK has been
Read data byte X 0 1 1 Data byte will be received and ACK will be returned
returned
Read data byte or 0 0 1 0 Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Previously addressed with own Read data byte or 1 0 1 0 Switched to the not addressed Slave mode;
SLA+W; data has been no recognition of own SLA or GCA;
0x88
received; NOT ACK has been a START condition will be transmitted when the bus
returned becomes free
Read data byte 1 0 1 1 Switched to the not addressed Slave mode;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
254 ATA6612/ATA6613
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Table 6-92. Status Codes for Slave Receiver Mode (Continued)

(TWSR) To TWCR
Previously addressed with Read data byte or X 0 1 0 Data byte will be received and NOT ACK will be
general call; data has been returned
0x90
received; ACK has been Read data byte X 0 1 1 Data byte will be received and ACK will be returned
returned
Previously addressed with Read data byte or 1 0 1 0 Switched to the not addressed Slave mode;
general call; data has been no recognition of own SLA or GCA;
0x98
received; NOT ACK has been a START condition will be transmitted when the bus
returned becomes free
Read data byte 1 0 1 1 Switched to the not addressed Slave mode;
becomes free
No action 0 0 1 0 Switched to the not addressed Slave mode;
0 0 1 1 Switched to the not addressed Slave mode;
A STOP condition or repeated 1 0 1 0 Switched to the not addressed Slave mode;
START condition has been no recognition of own SLA or GCA;
0xA0
received while still addressed a START condition will be transmitted when the bus
as Slave becomes free
1 0 1 1 Switched to the not addressed Slave mode;
becomes free
255
9111E–AUTO–07/08
Figure 6-93. Formats and States in the Slave Receiver Mode
Reception of the own
slave address and one or S SLA W A DATA A DATA A P or S
more data bytes. All are
acknowledged
$60 $80 $80 $A0
Last data byte received

is not acknowledged A P or S
$88
Arbitration lost as master

and addressed as slave A
$68
Reception of the general call

address and one or more data General Call A DATA A DATA A P or S
bytes
$70 $90 $90 $A0
Last data byte received is

not acknowledged A P or S
$98
Arbitration lost as master and

addressed as slave by general call A
$78


6.19.8.4 Slave Transmitter Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see Figure 6-94). All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.
Figure 6-94. Data Transfer in Slave Transmitter Mode

VCC
Device 1 Device 2
SLAVE MASTER Device 3 ........ Device n R1 R2
TRANSMITTER RECEIVER
SDA
SCL
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To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
value Device’s Own Slave Address
The upper seven bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),
otherwise it will ignore the general call address.
value 0 1 0 0 0 1 0 X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable
the acknowledgement of the device’s own slave address or the general call address. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in Table 6-93 on
page 258. The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is
in the Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-
fer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver
transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave
mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives
all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by
transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expect-
ing NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire
Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.
This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial
Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and
the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared
(by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks
running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may
be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these sleep modes.
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Table 6-93. Status Codes for Slave Transmitter Mode
(TWSR) To TWCR
Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK
Own SLA+R has been
should be received
0xA8 received;
Load data byte X 0 1 1 Data byte will be transmitted and ACK should be
ACK has been returned
received
Arbitration lost in SLA+R/W as Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK
Master; own SLA+R has been should be received
0xB0
received; ACK has been Load data byte X 0 1 1 Data byte will be transmitted and ACK should be
returned received
Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK
Data byte in TWDR has been should be received
0xB8 transmitted; ACK has been
Load data byte X 0 1 1 Data byte will be transmitted and ACK should be
received
received
No TWDR action or 0 0 1 0 Switched to the not addressed Slave mode;
Data byte in TWDR has been
no recognition of own SLA or GCA;
0xC0 transmitted; NOT ACK has
been received a START condition will be transmitted when the
bus becomes free
No TWDR action 1 0 1 1 Switched to the not addressed Slave mode;
a START condition will be transmitted when the
bus becomes free
Last data byte in TWDR has
no recognition of own SLA or GCA;
0xC8 been transmitted (TWEA =
“0”); ACK has been received a START condition will be transmitted when the
bus becomes free
No TWDR action 1 0 1 1 Switched to the not addressed Slave mode;
a START condition will be transmitted when the
bus becomes free
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Figure 6-95. Formats and States in the Slave Transmitter Mode

Reception of the own
slave address and one or S SLA R A DATA A DATA A P or S
more data bytes
$A8 $B8 $C0
Arbitration lost as master

and addressed as slave A
$B0
Last data byte transmitted.

Switched to not addressed A All 1's P or S
slave (TWEA = '0')
$C8


6.19.8.5 Miscellaneous States

There are two status codes that do not correspond to a defined TWI state (see Table 6-94).
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Table 6-94. Miscellaneous States

(TWSR) Status of the 2-wire Serial
To TWCR
No relevant state information
0xF8 No TWDR action No TWCR action Wait or proceed current transfer
available; TWINT = “0”
Only the internal hardware is affected, no STOP
Bus error due to an illegal
0x00 No TWDR action 0 1 1 X condition is sent on the bus. In all cases, the bus
START or STOP condition
is released and TWSTO is cleared.
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6.19.8.6 Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multi master sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 6-96. Combining Several TWI Modes to Access a Serial EEPROM

Master Transmitter Master Receiver
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
S = START Rs = REPEATED START P = STOP
Transmitted from master to slave Transmitted from slave to master
6.19.9 Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
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Figure 6-97. An Arbitration Example

VCC
Device 1 Device 2 Device 3

MASTER MASTER SLAVE ........ Device n R1 R2
TRANSMITTER TRANSMITTER RECEIVER
SDA
SCL
Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same Slave. In this
case, neither the Slave nor any of the masters will know about the bus contention.
• Two or more masters are accessing the same Slave with different data or direction bit. In this
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in Figure 6-98. Possible status values are given in circles.
Figure 6-98. Possible Status Codes Caused by Arbitration
START SLA Data STOP
Arbitration lost in SLA Arbitration lost in Data
Own No 38 TWI bus will be released and not addressed slave mode will be entered
Address / General Call
A START condition will be transmitted when the bus becomes free
received
Yes
Write 68/78 Data byte will be received and NOT ACK will be returned
Direction
Data byte will be received and ACK will be returned
Read Last data byte will be transmitted and NOT ACK should be received
B0 Data byte will be transmitted and ACK should be received
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6.20 Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger
the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate
interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on com-
parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 6-99.
The Power Reduction ADC bit, PRADC, in “Power Reduction Register - PRR” on page 66 must
be disabled by writing a logical zero to be able to use the ADC input MUX.
Figure 6-99. Analog Comparator Block Diagram(2)

BANDGAP
REFERENCE VCC
ACBG
ACD
ACIE
AIN0
ANALOG
INTERRUPT COMPARATOR
SELECT IRQ
ACI
AIN1
ACIS1 ACIS0 ACIC
ACME
ADEN
TO T/C1 CAPTURE
TRIGGER MUX
ACO
ADC MULTIPLEXER
OUTPUT (1)
Notes: 1. See Table 6-96 on page 264.

2. Refer to Table 6-38 on page 104 for Analog Comparator pin placement.
6.20.1 ADC Control and Status Register B – ADCSRB

Bit 7 6 5 4 3 2 1 0
– ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero),
the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is
written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a
detailed description of this bit (see “Analog Comparator Multiplexed Input” on page 264).
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6.20.2 Analog Comparator Control and Status Register – ACSR

Bit 7 6 5 4 3 2 1 0
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0
• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This
bit can be set at any time to turn off the Analog Comparator. This will reduce power con-
sumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator
Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Ana-
log Comparator (see “Internal Voltage Reference” on page 73).
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO.
The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode
defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the
ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog
Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be
triggered by the Analog Comparator. The comparator output is in this case directly con-
nected to the input capture front-end logic, making the comparator utilize the noise canceler
and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic
zero, no connection between the Analog Comparator and the input capture function exists.
To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in
the Timer Interrupt Mask Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in Table 6-95 on page 264.
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Table 6-95. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle.
0 1 Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
6.20.3 Analog Comparator Multiplexed Input

It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com-
parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be
switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in
ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX
select the input pin to replace the negative input to the Analog Comparator, as shown in Table
6-96. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog
Comparator.
Table 6-96. Analog Comparator Multiplexed Input

ACME ADEN MUX2..0 Analog Comparator Negative Input
0 x xxx AIN1
1 1 xxx AIN1
1 0 000 ADC0
1 0 001 ADC1
1 0 010 ADC2
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7
6.20.3.1 Digital Input Disable Register 1 – DIDR1

Bit 7 6 5 4 3 2 1 0
– – – – – – AIN1D AIN0D DIDR1

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The
corresponding PIN Register bit will always read as zero when this bit is set. When an analog
signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
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6.21 Analog-to-Digital Converter
6.21.1 Features
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy
• 13 - 260 µs Conversion Time
• Up to 15 kSPS at Maximum Resolution
• 6 Multiplexed Single Ended Input Channels
• 2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN Package only)
• Optional Left Adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 1.1V ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
The ATA6612/ATA6613 features a 10-bit successive approximation ADC. The ADC is con-
nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs
constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 6-100
on page 266.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±
0.3V from VCC. See the paragraph “ADC Noise Canceler” on page 272 on how to connect this
pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage refer-
ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.
The Power Reduction ADC bit, PRADC, in “Power Reduction Register - PRR” on page 66 must
be disabled by writing a logical zero to enable the ADC.
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Figure 6-100. Analog to Digital Converter Block Schematic Operation
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
ADIE
ADIF
15 0
ADC MULTIPLEXER ADC CTRL. & STATUS ADC DATA REGISTER
SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL)
ADLAR
REFS1
MUX3
MUX2
MUX1
MUX0
REFS0
ADPS2
ADPS1
ADPS0
ADEN
ADSC
ADFR
ADIF
ADC[9:0]
MUX DECODER
PRESCALER
CHANNEL SELECTION
CONVERSION LOGIC
AVCC
INTERNAL 1.1V
REFERENCE SAMPLE and HOLD
COMPARATOR
AREF
10-BIT DAC -
+
GND
BANDGAP
REFERENCE
ADC7
ADC6
INPUT ADC MULTIPLEXER

ADC5
MUX OUTPUT
ADC4
ADC3
ADC2
ADC1
ADC0
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V reference voltage may be con-
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve
noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended
inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-
age reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering power saving sleep modes.
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The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
6.21.2 Starting a Conversion

A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in “Power
Reduction Register - PRR” on page 66 by writing a logical zero to it and writing a logical one to
the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress
and will be cleared by hardware when the conversion is completed. If a different data channel is
selected while a conversion is in progress, the ADC will finish the current conversion before per-
forming the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting con-
versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.
Figure 6-101. ADC Auto Trigger Logic

ADTS[2:0]
PRESCALER
START CLKADC
ADIF ADATE
SOURCE 1
. CONVERSION
. LOGIC
.
. EDGE
SOURCE n DETECTOR
ADSC
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Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
6.21.3 Prescaling and Conversion Timing
Figure 6-102. ADC Prescaler

ADEN
START Reset
7-BIT ADC PRESCALER
CK
CK/128
CK/64
CK/32
CK/16
CK/2
CK/4
CK/8
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
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When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times (see Table 6-97 on page
270).
Figure 6-103. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion Conversion
Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3
ADC Clock
ADEN
ADSC
ADIF
ADCH Sign and MSB of Result
ADCL LSB of Result
MUX and REFS Conversion MUX and REFS

Update Sample & Hold Complete Update
Figure 6-104. ADC Timing Diagram, Single Conversion

One Conversion Next Conversion
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3
ADC Clock
ADSC
ADIF
ADCL LSB of Result
Sample & Hold

Conversion MUX and REFS
MUX and REFS Complete Update
Update
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Figure 6-105. ADC Timing Diagram, Auto Triggered Conversion
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
ADC Clock
Trigger
Source
ADATE
ADIF
ADCL LSB of Result
Sample & Conversion Prescaler

Prescaler Hold Complete Reset
Reset
MUX and REFS
Update
Figure 6-106. ADC Timing Diagram, Free Running Conversion

11 12 13 1 2 3 4
Cycle Number
ADC Clock
ADSC
ADIF
ADCL LSB of Result
Conversion Sample & Hold

Complete MUX and REFS
Update
Table 6-97. ADC Conversion Time

Sample & Hold (Cycles from
Condition Start of Conversion) Conversion Time (Cycles)
First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto Triggered conversions 2 13.5
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6.21.4 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values
to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
6.21.4.1 ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
6.21.4.2 ADC Voltage Reference

The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single
ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as
either AVCC, internal 1.1V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is gener-
ated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the
external AREF pin is directly connected to the ADC, and the reference voltage can be made
more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can
also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high
impedant source, and only a capacitive load should be connected in a system.
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If the user has a fixed voltage source connected to the AREF pin, the user may not use the other
reference voltage options in the application, as they will be shorted to the external voltage. If no
external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as ref-
erence selection. The first ADC conversion result after switching reference voltage source may
be inaccurate, and the user is advised to discard this result.
6.21.5 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC
Noise Reduction and Idle mode. To make use of this feature, the following procedure should be
used:
a. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC conversion complete interrupt must be
enabled.
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
c. If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the CPU and execute the ADC Conversion Complete interrupt
routine. If another interrupt wakes up the CPU before the ADC conversion is com-
plete, that interrupt will be executed, and an ADC Conversion Complete interrupt
request will be generated when the ADC conversion completes. The CPU will
remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
6.21.5.1 Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 6-107 on page 273 An
analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin,
regardless of whether that channel is selected as input for the ADC. When the channel is
selected, the source must drive the S/H capacitor through the series resistance (combined resis-
tance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher imped-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.
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Figure 6-107. Analog Input Circuitry
IIH
ADCn
1..100 kW
CS/H = 14 pF
IIL
VCC/2
6.21.5.2 Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
a. Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane, and keep them well away from high-speed switching digi-
tal tracks.
b. The AVCC pin on the device should be connected to the digital VCC supply voltage
via an LC network as shown in Figure 6-108 on page 274.
c. Use the ADC noise canceler function to reduce induced noise from the CPU.
d. If any ADC [3..0] port pins are used as digital outputs, it is essential that these do
not switch while a conversion is in progress. However, using the 2-wire Interface
(ADC4 and ADC5) will only affect the conversion on ADC4 and ADC5 and not the
other ADC channels.
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Figure 6-108. ADC Power Connections
PC4 (ADC4/SDA)
PC5 (ADC5/SCL)
PC3 (ADC3)
PC2 (ADC2)
Analog Ground Plane

GND
VCC
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
10 mH
AREF
ADC6
100 nF
AVCC
PB5
6.21.5.3 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
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Figure 6-109. Offset Error

Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
• Gain error: After adjusting for offset, the gain error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Figure 6-110. Gain Error

Output Code Gain
Error
Ideal ADC
Actual ADC
VREF Input Voltage
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.
Figure 6-111. Integral Non-linearity (INL)

Output Code
INL
Ideal ADC
Actual ADC
VREF Input Voltage
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval
between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
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Figure 6-112. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
0 VREF Input Voltage
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,
a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
• Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to
an ideal transition for any code. This is the compound effect of offset, gain error, differential
error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.
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6.21.6 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
For single ended conversion, the result is
V IN ⋅ 1024
ADC = ----------------------------
-
V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 6-98 on page 277 and Table 6-99 on page 278). 0x000 represents analog ground, and
0x3FF represents the selected reference voltage minus one LSB.
6.21.6.1 ADC Multiplexer Selection Register – ADMUX

Bit 7 6 5 4 3 2 1 0
REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R R/W R/W R/W R/W
• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 6-98. If these bits are
changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used
if an external reference voltage is being applied to the AREF pin.
Table 6-98. Voltage Reference Selections for ADC

REFS1 REFS0 Voltage Reference Selection
0 0 AREF, Internal Vref turned off
0 1 AVCC with external capacitor at AREF pin
1 0 Reserved
1 1 Internal 1.1V Voltage Reference with external capacitor at AREF pin
• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Reg-
ister. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any
ongoing conversions. For a complete description of this bit (see “The ADC Data Register –
ADCL and ADCH” on page 280).
• Bits 3:0 – MUX3:0: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. See Table
6-99 on page 278 for details. If these bits are changed during a conversion, the change will
not go in effect until this conversion is complete (ADIF in ADCSRA is set).
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Table 6-99. Input Channel Selections
MUX3..0 Single Ended Input
0000 ADC0
0001 ADC1
0010 ADC2
0011 ADC3
0100 ADC4
0101 ADC5
0110 ADC6
0111 ADC7
1000 (reserved)
1001 (reserved)
1010 (reserved)
1011 (reserved)
1100 (reserved)
1101 (reserved)
1110 1.1V (VBG)
1111 0V (GND)
6.21.6.2 ADC Control and Status Register A – ADCSRA

Bit 7 6 5 4 3 2 1 0
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning
the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running
mode, write this bit to one to start the first conversion. The first conversion after ADSC has
been written after the ADC has been enabled, or if ADSC is written at the same time as the
ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion
performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is com-
plete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a
conversion on a positive edge of the selected trigger signal. The trigger source is selected
by setting the ADC Trigger Select bits, ADTS in ADCSRB.
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• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are
set. ADIF is cleared by hardware when executing the corresponding interrupt handling vec-
tor. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a
Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the
SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete
Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input
clock to the ADC.
Table 6-100. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor
0 0 0 2
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
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6.21.6.3 The ADC Data Register – ADCL and ADCH
ADLAR = 0
Bit 15 14 13 12 11 10 9 8
– – – – – – ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
7 6 5 4 3 2 1 0
R R R R R R R R
0 0 0 0 0 0 0 0
ADLAR = 1
Bit 15 14 13 12 11 10 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 – – – – – – ADCL
7 6 5 4 3 2 1 0
R R R R R R R R
0 0 0 0 0 0 0 0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result”
on page 277.
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6.21.6.4 ADC Control and Status Register B – ADCSRB

Bit 7 6 5 4 3 2 1 0
– ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
• Bit 7, 5:3 – Res: Reserved Bits

These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trig-
ger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A
conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that
switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion.
Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the
ADC Interrupt Flag is set.
Table 6-101. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match A
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
6.21.6.5 Digital Input Disable Register 0 – DIDR0

Bit 7 6 5 4 3 2 1 0
– – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R R R/W R/W R/W R/W R/W R/W

These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.
• Bit 5..0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set.
When an analog signal is applied to the ADC5..0 pin and the digital input from this pin is not
needed, this bit should be written logic one to reduce power consumption in the digital input
buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not
require Digital Input Disable bits.
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6.22 debugWIRE On-chip Debug System
6.22.1 Features
• Complete Program Flow Control
• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin
• Real-time Operation
• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
• Unlimited Number of Program Break Points (Using Software Break Points)
• Non-intrusive Operation
• Electrical Characteristics Identical to Real Device
• Automatic Configuration System
• High-Speed Operation
• Programming of Non-volatile Memories
6.22.2 Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the
program flow, execute AVR instructions in the CPU and to program the different non-volatile
memories.
6.22.3 Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,
the debugWIRE system within the target device is activated. The RESET port pin is configured
as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-
nication gateway between target and emulator.
Figure 6-113. The debugWIRE Setup

2.7 - 5.5
VCC
dW dW(RESE)
GND
Figure 6-113 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator
connector. The system clock is not affected by debugWIRE and will always be the clock source
selected by the CKSEL Fuses.
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When designing a system where debugWIRE will be used, the following observations must be
made for correct operation:
• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor
is not required for debugWIRE functionality.
• Connecting the RESET pin directly to VCC will not work.
• Capacitors connected to the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.
6.22.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a
Break Point in AVR Studio® will insert a BREAK instruction in the Program memory. The instruc-
tion replaced by the BREAK instruction will be stored. When program execution is continued, the
stored instruction will be executed before continuing from the Program memory. A break can be
inserted manually by putting the BREAK instruction in the program.
The Flash must be re-programmed each time a Break Point is changed. This is automatically
handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore
reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to
end customers.
6.22.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External
Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is
enabled.
The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,
when the program in the CPU is running. When the CPU is stopped, care must be taken while
accessing some of the I/O Registers via the debugger (AVR Studio).
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep
modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should
be disabled when debugWire is not used.
6.22.6 debugWIRE Related Register in I/O Memory

The following section describes the registers used with the debugWire.
6.22.6.1 debugWire Data Register – DWDR

Bit 7 6 5 4 3 2 1 0
DWDR[7:0] DWDR
The DWDR Register provides a communication channel from the running program in the MCU
to the debugger. This register is only accessible by the debugWIRE and can therefore not be
used as a general purpose register in the normal operations.
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6.23 Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and ATA6613
In ATA6612 and ATA6613, the Boot Loader Support provides a real Read-While-Write Self-Pro-
gramming mechanism for downloading and uploading program code by the MCU itself. This
feature allows flexible application software updates controlled by the MCU using a Flash-resi-
dent Boot Loader program. The Boot Loader program can use any available data interface and
associated protocol to read code and write (program) that code into the Flash memory, or read
the code from the program memory. The program code within the Boot Loader section has the
capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can
thus even modify itself, and it can also erase itself from the code if the feature is not needed any-
more. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has
two separate sets of Boot Lock bits which can be set independently. This gives the user a
unique flexibility to select different levels of protection.
6.23.1 Boot Loader Features

• Read-While-Write Self-Programming
• Flexible Boot Memory Size
• High Security (Separate Boot Lock Bits for a Flexible Protection)
• Separate Fuse to Select Reset Vector
• Optimized Page(1) Size
• Code Efficient Algorithm
• Efficient Read-Modify-Write Support
Note: 1. A page is a section in the Flash consisting of several bytes (see Table 6-123 on page 306)
used during programming. The page organization does not affect normal operation.
6.23.2 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot
Loader section (see Figure 6-115 on page 287). The size of the different sections is configured
by the BOOTSZ Fuses as shown in Table 6-107 on page 298 and Figure 6-115 on page 287.
These two sections can have different level of protection since they have different sets of Lock
bits.
6.23.2.1 Application Section

The Application section is the section of the Flash that is used for storing the application code.
The protection level for the Application section can be selected by the application Boot Lock bits
(Boot Lock bits 0), see Table 6-103 on page 288. The Application section can never store any
Boot Loader code since the SPM instruction is disabled when executed from the Application
section.
6.23.2.2 BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-
ware must be located in the BLS since the SPM instruction can initiate a programming when
executing from the BLS only. The SPM instruction can access the entire Flash, including the
BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader
Lock bits (Boot Lock bits 1), see Table 6-104 on page 288.
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6.23.3 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-
ware update is dependent on which address that is being programmed. In addition to the two
sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also
divided into two fixed sections, the Read-While-Write (RWW) section and the No
Read-While-Write (NRWW) section. The limit between the RWW- and NRWW sections is given
in Table 6-108 on page 298 and Figure 6-115 on page 287. The main difference between the
two sections is:
• When erasing or writing a page located inside the RWW section, the NRWW section can be
read during the operation.
• When erasing or writing a page located inside the NRWW section, the CPU is halted during
the entire operation.
Note that the user software can never read any code that is located inside the RWW section dur-
ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which
section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.
6.23.3.1 RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible
to read code from the Flash, but only code that is located in the NRWW section. During an
on-going programming, the software must ensure that the RWW section never is being read. If
the user software is trying to read code that is located inside the RWW section (i.e., by a
call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown
state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-
tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy
bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read
as logical one as long as the RWW section is blocked for reading. After a programming is com-
pleted, the RWWSB must be cleared by software before reading code located in the RWW
section. See “Store Program Memory Control and Status Register – SPMCSR” on page 289 for
details on how to clear RWWSB.
6.23.3.2 NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU
is halted during the entire Page Erase or Page Write operation.
Table 6-102. Read-While-Write Features

Which Section Can be
Which Section does the Z-pointer Read During Is the CPU Read-While-Write
Address During the Programming? Programming? Halted? Supported?
RWW Section NRWW Section No Yes
NRWW Section None Yes No
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Figure 6-114. Read-While-Write versus No Read-While-Write
Read-While-Write
(RWW) Section
Z-pointer
Addresses NRWW
Section
Z-pointer
Addresses RWW No Read-While-Write
Section (NRWW) Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation
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Figure 6-115. Memory Sections

Program Memory Program Memory
BOOTSZ = '11' BOOTSZ = '10'
0x0000 0x0000
Read-While-Write Section
Application Flash Section Application Flash Section
No Read-While-Write Section
End RWW End RWW
Start NRWW Start NRWW
End Application
End Application Start Boot Loader
Start Boot Loader Boot Loader Flash Section
Boot Loader Flash Section
Flashend Flashend
Program Memory Program Memory

BOOTSZ = '01' BOOTSZ = '00'
0x0000 0x0000
End RWW, End Application

End RWW
Start NRWW Start NRWW, Start Boot Loader
End Application
Start Boot Loader
Flashend Flashend
Note: 1. The parameters in the figure above are given in Table 6-107 on page 298.
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6.23.4 Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU.
• To protect only the Boot Loader Flash section from a software update by the MCU.
• To protect only the Application Flash section from a software update by the MCU.
• Allow software update in the entire Flash.
See Table 6-103 and Table 6-104 for further details. The Boot Lock bits can be set in software
and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command
only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash
memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not
control reading nor writing by LPM/SPM, if it is attempted.
Table 6-103. Boot Lock Bit0 Protection Modes (Application Section)(1)

BLB0 Mode BLB02 BLB01 Protection
1 1 1 No restrictions for SPM or LPM accessing the Application section.
2 1 0 SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read from
3 0 0 the Application section. If Interrupt Vectors are placed in the Boot
Loader section, interrupts are disabled while executing from the
Application section.
LPM executing from the Boot Loader section is not allowed to read
from the Application section. If Interrupt Vectors are placed in the
4 0 1
Boot Loader section, interrupts are disabled while executing from
the Application section.
Note: 1. “1” means unprogrammed, “0” means programmed
Table 6-104. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB1 Mode BLB12 BLB11 Protection
No restrictions for SPM or LPM accessing the Boot Loader
1 1 1
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read from
3 0 0 the Boot Loader section. If Interrupt Vectors are placed in the
Application section, interrupts are disabled while executing from
the Boot Loader section.
LPM executing from the Application section is not allowed to read
from the Boot Loader section. If Interrupt Vectors are placed in the
4 0 1
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6.23.5 Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may
be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,
the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash
start address after a reset. In this case, the Boot Loader is started after a reset. After the applica-
tion code is loaded, the program can start executing the application code. Note that the fuses
cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-
grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be
changed through the serial or parallel programming interface.
Table 6-105. Boot Reset Fuse(1)

BOOTRST Reset Address
1 Reset Vector = Application Reset (address 0x0000)
0 Reset Vector = Boot Loader Reset (see Table 6-107 on page 298)
6.23.5.1 Store Program Memory Control and Status Register – SPMCSR

The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the
SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as
the SELFPRGEN bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is ini-
tiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW
section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to
one after a Self-Programming operation is completed. Alternatively the RWWSB bit will
automatically be cleared if a page load operation is initiated.
This bit is a reserved bit in the ATA6612/ATA6613 and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section,
the user software must wait until the programming is completed (SELFPRGEN will be
cleared). Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the
next SPM instruction within four clock cycles re-enables the RWW section. The RWW sec-
tion cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write
(SELFPRGEN is set). If the RWWSRE bit is written while the Flash is being loaded, the
Flash load operation will abort and the data loaded will be lost.
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• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within
four clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The
data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically
be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within
four clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the
SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the
Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software”
• Bit 2 – PGWRT: Page Write
four clock cycles executes Page Write, with the data stored in the temporary buffer. The
page address is taken from the high part of the Z-pointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM
instruction is executed within four clock cycles. The CPU is halted during the entire Page
Write operation if the NRWW section is addressed.
• Bit 1 – PGERS: Page Erase
four clock cycles executes Page Erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple-
tion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU
is halted during the entire Page Write operation if the NRWW section is addressed.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together
with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have
a special meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon
completion of an SPM instruction, or if no SPM instruction is executed within four clock
cycles. During Page Erase and Page Write, the SELFPRGEN bit remains high until the
operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the
lower five bits will have no effect.
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6.23.6 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.
Bit 15 14 13 12 11 10 9 8
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
7 6 5 4 3 2 1 0
Since the Flash is organized in pages (see Table 6-123 on page 306), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is1 shown in Figure 6-116. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the Boot Loader software
addresses the same page in both the Page Erase and Page Write operation. Once a program-
ming operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits.
The content of the Z-pointer is ignored and will have no effect on the operation. The LPM
instruction does also use the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 6-116. Addressing the Flash During SPM(1)

BIT 15 ZPCMSB ZPAGEMSB 1 0
Z - REGISTER 0
PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER
PAGE ADDRESS WORD ADDRESS

WITHIN THE FLASH WITHIN A PAGE
PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]:

PAGE 00
INSTRUCTION WORD
01
02
PAGEEND
Note: 1. The different variables used in Figure 6-116 are listed in Table 6-109 on page 298.
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6.23.7 Self-Programming the Flash
The program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page buf-
fer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Write operation:
Alternative 1, fill the buffer before a Page Erase
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,
the Boot Loader provides an effective Read-Modify-Write feature which allows the user software
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not possible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page address used in both the Page Erase and Page Write operation is addressing the same
page. See “Simple Assembly Code Example for a Boot Loader” on page 296 for an assembly
code example.
6.23.7.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
6.23.7.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
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6.23.7.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
6.23.7.4 Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of
polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors
should be moved to the BLS section to avoid that an interrupt is accessing the RWW section
when it is blocked for reading. How to move the interrupts is described in “Watchdog Timer” on
page 74.
6.23.7.5 Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
6.23.7.6 Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS
as described in “Watchdog Timer” on page 74, or the interrupts must be disabled. Before
addressing the RWW section after the programming is completed, the user software must clear
the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader”
on page 296 for an example.
6.23.7.7 Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-
ware update by the MCU.
Bit 7 6 5 4 3 2 1 0
R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1
See Table 6-103 on page 288 and Table 6-104 on page 288 for how the different settings of the
Boot Loader bits affect the Flash access.
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If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SELFPRGEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it is rec-
ommended to load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future
compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock
bits. When programming the Lock bits the entire Flash can be read during the operation.
6.23.7.8 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
6.23.7.9 Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to Table 6-116 on page
302 for a detailed description and mapping of the Fuse Low byte.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to Table 6-117 on page 302 for detailed description and mapping of the
Fuse High byte.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
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When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to Table 6-116 on page 302 for detailed description and mapping of the Extended
Fuse byte.
Bit 7 6 5 4 3 2 1 0
Rd – – – – EFB3 EFB2 EFB1 EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
6.23.7.10 Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low VCC reset protection circuit
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
6.23.7.11 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 6-106 shows the typical pro-
gramming time for Flash accesses from the CPU.
Table 6-106. SPM Programming Time

Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write, and
3.7 ms 4.5 ms
write Lock bits by SPM)
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6.23.7.12 Simple Assembly Code Example for a Boot Loader
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)
call Do_spm
; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
call Do_spm
; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
Wrloop:
ld r0, Y+
ld r1, Y+
ldi spmcrval, (1<<SELFPRGEN)
call Do_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256
brne Wrloop
; execute Page Write

subi ZL, low(PAGESIZEB) ;restore pointer
sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256
ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)
call Do_spm

call Do_spm
; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
subi YL, low(PAGESIZEB) ;restore pointer
sbci YH, high(PAGESIZEB)
Rdloop:
lpm r0, Z+
ld r1, Y+
cpse r0, r1
jmp Error
sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256
brne Rdloop
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; return to RWW section

; verify that RWW section is safe to read
Return:
in temp1, SPMCSR
sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet
ret
call Do_spm
rjmp Return
Do_spm:
; check for previous SPM complete
Wait_spm:
in temp1, SPMCSR
sbrc temp1, SELFPRGEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret
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6.23.7.13 ATA6612 Boot Loader Parameters
In Table 6-107 through Table 6-109 on page 298, the parameters used in the description of the
self programming are given.
Table 6-107. Boot Size Configuration, ATA6612

Boot Boot Reset
Application Loader End Address (Start
Boot Flash Flash Application Boot Loader
BOOTSZ1 BOOTSZ0 Size Pages Section Section Section Section)
128 0xF80 -
1 1 4 0x000 - 0xF7F 0xF7F 0xF80
words 0xFFF
256 0xF00 -
1 0 8 0x000 - 0xEFF 0xEFF 0xF00
words 0xFFF
512 0xE00 -
0 1 16 0x000 - 0xDFF 0xDFF 0xE00
words 0xFFF
1024 0xC00 -
0 0 32 0x000 - 0xBFF 0xBFF 0xC00
words 0xFFF
Note: The different BOOTSZ Fuse configurations are shown in Figure 6-115 on page 287.
Table 6-108. Read-While-Write Limit, ATA6612

Section Pages Address
Read-While-Write section (RWW) 96 0x000 - 0xBFF
No Read-While-Write section (NRWW) 32 0xC00 - 0xFFF
For details about these two section, see “NRWW – No Read-While-Write Section” on page 285
and “RWW – Read-While-Write Section” on page 285.
Table 6-109. Explanation of Different Variables used in Figure 6-116 on page 291 and the
Mapping to the Z-pointer, ATA6612
Corresponding
Variable Z-value(1) Description
Most significant bit in the Program Counter. (The
PCMSB 11
Program Counter is 12 bits PC[11:0])
Most significant bit which is used to address the words
PAGEMSB 4 within one page (32 words in a page requires 5 bits PC
[4:0]).
Bit in Z-register that is mapped to PCMSB. Because
ZPCMSB Z12
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB. Because
ZPAGEMSB Z5
Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1.
Program counter page address: Page select, for page
PCPAGE PC[11:5] Z12:Z6
erase and page write
Program counter word address: Word select, for filling
PCWORD PC[4:0] Z5:Z1 temporary buffer (must be zero during page write
operation)
Note: 1. Z15:Z13: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See “Addressing the Flash During Self-Programming” on page 291 for details about the use of
Z-pointer during Self-Programming.
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6.23.7.14 ATA6613 Boot Loader Parameters

In Table 6-110 through Table 6-112, the parameters used in the description of the self program-
ming are given.
Table 6-110. Boot Size Configuration, ATA6613
Boot Boot Reset
Application Loader End Address (Start
Boot Flash Flash Application Boot Loader
BOOTSZ1 BOOTSZ0 Size Pages Section Section Section Section)
128 0x0000 - 0x1F80 -
1 1 2 0x1F7F 0x1F80
words 0x1F7F 0x1FFF
256 0x0000 - 0x1F00 -
1 0 4 0x1EFF 0x1F00
words 0x1EFF 0x1FFF
512 0x0000 - 0x1E00 -
0 1 8 0x1DFF 0x1E00
words 0x1DFF 0x1FFF
1024 0x0000 - 0x1C00 -
0 0 16 0x1BFF 0x1C00
words 0x1BFF 0x1FFF
Note: The different BOOTSZ Fuse configurations are shown in Figure 6-115 on page 287.
Table 6-111. Read-While-Write Limit, ATA6613

Section Pages Address
Read-While-Write section (RWW) 112 0x0000 - 0x1BFF
No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF
For details about these two section, see “NRWW – No Read-While-Write Section” on page 285
and “RWW – Read-While-Write Section” on page 285.
Table 6-112. Explanation of Different Variables used in Figure 6-116 on page 291 and the
Mapping to the Z-pointer, ATA6613
Corresponding
Variable Z-value(1) Description
Most significant bit in the Program Counter. (The
PCMSB 12
Program Counter is 12 bits PC[11:0])
Most significant bit which is used to address the
PAGEMSB 5 words within one page (64 words in a page
requires 6 bits PC [5:0])
Bit in Z-register that is mapped to PCMSB. Because
ZPCMSB Z13
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB. Because
ZPAGEMSB Z6
Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1.
Program counter page address: Page select, for page
PCPAGE PC[12:6] Z13:Z7
erase and page write
Program counter word address: Word select, for filling
PCWORD PC[5:0] Z6:Z1 temporary buffer (must be zero during page write
operation)
Note: 1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See “Addressing the Flash During Self-Programming” on page 291 for details about the use of
Z-pointer during Self-Programming.
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6.24 Memory Programming
6.24.1 Program And Data Memory Lock Bits

The ATA6612/ATA6613 provides six Lock bits which can be left unprogrammed (“1”) or can be
programmed (“0”) to obtain the additional features listed in Table 6-114. The Lock bits can only
be erased to “1” with the Chip Erase command. The SPM instruction is enabled for the whole
Flash if the SELFPRGEN fuse is programmed (“0”), otherwise it is disabled.
Table 6-113. Lock Bit Byte(1)

Lock Bit Byte Bit No Description Default Value
7 – 1 (unprogrammed)
6 – 1 (unprogrammed)
(2)
BLB12 5 Boot Lock bit 1 (unprogrammed)
(2)
BLB02(2) 3 Boot Lock bit 1 (unprogrammed)
(2)
LB2 1 Lock bit 1 (unprogrammed)
LB1 0 Lock bit 1 (unprogrammed)
Notes: 1. “1” means unprogrammed, “0” means programmed

2. Only on ATA6612/ATA6613
Table 6-114. Lock Bit Protection Modes(1)(2)

Memory Lock Bits Protection Type
LB Mode LB2 LB1
1 1 1 No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
2 1 0 Parallel and Serial Programming mode. The Fuse bits are locked
in both Serial and Parallel Programming mode.(1)
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Boot
3 0 0
Lock bits and Fuse bits are locked in both Serial and Parallel
Programming mode.(1)
Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
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Table 6-115. Lock Bit Protection Modes(1)(2). Only ATA6612/ATA6613.

BLB0 Mode BLB02 BLB01
1 1 1 No restrictions for SPM or LPM accessing the Application section.
2 1 0 SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read from
3 0 0 the Application section. If Interrupt Vectors are placed in the Boot
Loader section, interrupts are disabled while executing from the
Application section.
LPM executing from the Boot Loader section is not allowed to read
from the Application section. If Interrupt Vectors are placed in the
4 0 1
Boot Loader section, interrupts are disabled while executing from
the Application section.
BLB1 Mode BLB12 BLB11
No restrictions for SPM or LPM accessing the Boot Loader
1 1 1
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read from
3 0 0 the Boot Loader section. If Interrupt Vectors are placed in the
LPM executing from the Application section is not allowed to read
from the Boot Loader section. If Interrupt Vectors are placed in the
4 0 1
Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
6.24.2 Fuse Bits

The ATA6612/ATA6613 has three Fuse bytes. Table 6-116 to Table 6-118 on page 303
describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes.
Note that the fuses are read as logical zero, “0”, if they are programmed.
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Table 6-116. Extended Fuse Byte for ATA6612/ATA6613
Extended Fuse Byte Bit No Description Default Value
– 7 – 1
– 6 – 1
– 5 – 1
– 4 – 1
– 3 – 1
Select Boot Size
BOOTSZ1 2 0 (programmed)(1)
(see Table 113 for details)
Select Boot Size
BOOTSZ0 1 0 (programmed)(1)
(see Table 113 for details)
BOOTRST 0 Select Reset Vector 1 (unprogrammed)
Note: 1. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 6-119 on page
305 for details.
Table 6-117. Fuse High Byte

High Fuse Byte Bit No Description Default Value
RSTDISBL(1) 7 External Reset Disable 1 (unprogrammed)
DWEN 6 debugWIRE Enable 1 (unprogrammed)
Enable Serial Program and 0 (programmed, SPI
SPIEN(2) 5
Data Downloading programming enabled)
WDTON(3) 4 Watchdog Timer Always On 1 (unprogrammed)
EEPROM memory is preserved 1 (unprogrammed), EEPROM
EESAVE 3
through the Chip Erase not reserved
BODLEVEL2(4) 2 Brown-out Detector trigger level 1 (unprogrammed)
BODLEVEL1(4) 1 Brown-out Detector trigger level 1 (unprogrammed)
(4)
BODLEVEL0 0 Brown-out Detector trigger level 1 (unprogrammed)
Notes: 1. See “Alternate Functions of Port C” on page 101 for description of RSTDISBL Fuse.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See “Watchdog Timer Control Register - WDTCSR” on page 78 for details.
4. See Table 6-21 on page 71 for BODLEVEL Fuse decoding.
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Table 6-118. Fuse Low Byte

Low Fuse Byte Bit No Description Default Value
CKDIV8(4) 7 Divide clock by 8 0 (programmed)
(3)
CKOUT 6 Clock output 1 (unprogrammed)
SUT1 5 Select start-up time 1 (unprogrammed)(1)
SUT0 4 Select start-up time 0 (programmed)(1)
CKSEL3 3 Select Clock source 0 (programmed)(2)
CKSEL1 1 Select Clock source 1 (unprogrammed)(2)
Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 6-12 on page 57 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 6-11 on
page 57 for details.
3. The CKOUT Fuse allows the system clock to be output on PORTB0. See “Clock Output Buffer”
4. See “System Clock Prescaler” on page 60 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
6.24.2.1 Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.
6.24.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space.
6.24.3.1 ATA6612 Signature Bytes

1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x93 (indicates 8KB Flash memory).
3. 0x002: 0x0A (indicates ATA6612 device when 0x001 is 0x93).
6.24.3.2 ATA6613 Signature Bytes

1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x94 (indicates 16KB Flash memory).
3. 0x002: 0x06 (indicates ATA6613 device when 0x001 is 0x94).
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6.24.4 Calibration Byte
The ATA6612/ATA6613 has a byte calibration value for the internal RC Oscillator. This byte
resides in the high byte of address 0x000 in the signature address space. During reset, this byte
is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated
RC Oscillator.
6.24.5 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATA6612/ATA6613. Pulses are assumed
to be at least 250 ns unless otherwise noted.
6.24.5.1 Signal Names

In this section, some pins of the ATA6612/ATA6613 are referenced by signal names describing
their functionality during parallel programming (see Figure 6-117 and Table 6-119 on page 305).
Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 6-121 on page 305.
When pulsing WR or OE, the command loaded determines the action executed. The different
Commands are shown in Table 6-122 on page 305.
Figure 6-117. Parallel Programming

+5V
RDY/BSY PD1
VCC
OE PD2 +5V
WR PD3 AVCC
BS1 PD4 PC[1:0]:PB[5:0] DATA

XA0 PD5
XA1 PD6
PAGEL PD7
+12 V RESET
BS2 PC2
XTAL1
GND
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Table 6-119. Pin Name Mapping

Signal Name in
Programming Mode Pin Name I/O Function
0: Device is busy programming, 1: Device is
RDY/BSY PD1 O
ready for new command
OE PD2 I Output Enable (Active low)
WR PD3 I Write Pulse (Active low)
Byte Select 1 (“0” selects Low byte, “1” selects
BS1 PD4 I
High byte)
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
PAGEL PD7 I Program memory and EEPROM Data Page Load
Byte Select 2 (“0” selects Low byte, “1” selects
BS2 PC2 I
2’nd High byte)
DATA {PC[1:0]: PB[5:0]} I/O Bi-directional Data bus (Output when OE is low)
Table 6-120. Pin Values Used to Enter Programming Mode

Pin Symbol Value
PAGEL Prog_enable[3] 0
XA1 Prog_enable[2] 0
XA0 Prog_enable[1] 0
BS1 Prog_enable[0] 0
Table 6-121. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed
Load Flash or EEPROM Address (High or low address byte determined by
0 0
BS1).
0 1 Load Data (High or Low data byte for Flash determined by BS1).
1 0 Load Command
1 1 No Action, Idle
Table 6-122. Command Byte Bit Coding

Command Byte Command Executed
1000 0000 Chip Erase
0100 0000 Write Fuse bits
0010 0000 Write Lock bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes and Calibration byte
0000 0100 Read Fuse and Lock bits
0000 0010 Read Flash
0000 0011 Read EEPROM
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Table 6-123. No. of Words in a Page and No. of Pages in the Flash
No. of
Device Flash Size Page Size PCWORD Pages PCPAGE PCMSB
4K words
ATA6612 32 words PC[4:0] 128 PC[11:5] 11
(8K bytes)
8K words
ATA6613 64 words PC[5:0] 128 PC[12:6] 12
(16K bytes)
Table 6-124. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Page No. of
Device Size Size PCWORD Pages PCPAGE EEAMSB
ATA6612 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
ATA6613 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
6.24.6 Serial Programming Pin Mapping
Table 6-125. Pin Mapping Serial Programming

Symbol Pins I/O Description
MOSI PB3 I Serial Data in
MISO PB4 O Serial Data out
SCK PB5 I Serial Clock
6.24.7 Parallel Programming
6.24.7.1 Enter Programming Mode

The following algorithm puts the device in parallel programming mode:
1. Apply 4.5 - 5.5V between VCC and GND.
2. Set RESET to “0” and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in Table 6-120 on page 305 to “0000” and wait at least
100 ns.
4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after
+12V has been applied to RESET, will cause the device to fail entering programming
mode.
5. Wait at least 50 µs before sending a new command.
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6.24.7.2 Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory
locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
6.24.7.3 Chip Erase

The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are
not reset until the program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.
6.24.7.4 Programming the Flash

The Flash is organized in pages (see Table 6-123 on page 306). When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be pro-
grammed simultaneously. The following procedure describes how to program the entire Flash
memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address low byte.
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C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte (0x00 - 0xFF).
3. Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes (see Figure 6-119 on page
309 for signal waveforms).
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address
the pages within the FLASH. This is illustrated in Figure 6-118 on page 309. Note that if less
than eight bits are required to address words in the page (pagesize < 256), the most significant
bit(s) in the address low byte are used to address the page when performing a Page Write.
G. Load Address High byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data.
RDY/BSY goes low.
2. Wait until RDY/BSY goes high (see Figure 6-119 on page 309 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals
are reset.
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Figure 6-118. Addressing the Flash Which is Organized in Pages(1)

PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER
PAGE ADDRESS WORD ADDRESS

WITHIN THE FLASH WITHIN A PAGE
PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]:

PAGE 00
INSTRUCTION WORD
01
02
PAGEEND
Note: 1. PCPAGE and PCWORD are listed in Table 6-123 on page 306.
Figure 6-119. Programming the Flash Waveforms(1)

F
A B C D E B C D E G H
0x10 ADDR. LOW DATA LOW DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX ADDR. HIGH XX
DATA
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note: 1. “XX” is do not care. The letters refer to the programming description above.
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6.24.7.5 Programming the EEPROM
The EEPROM is organized in pages (see Table 6-124 on page 306). When programming the
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
follows (refer to “Programming the Flash” on page 307 for details on Command, Address and
Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. C: Load Data (0x00 - 0xFF).
5. E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS1 to “0”.
2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. Wait until to RDY/BSY goes high before programming the next page (see Figure 6-120
for signal waveforms).
Figure 6-120. Programming the EEPROM Waveforms

K
A G B C E B C E L
0x11 ADDR. HIGH ADDR. LOW DATA XX ADDR. LOW DATA XX
DATA
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
6.24.7.6 Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on
page 307 for details on Command and Address loading):
1. A: Load Command “0000 0010”.
4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6. Set OE to “1”.
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6.24.7.7 Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”
on page 307 for details on Command and Address loading):
1. A: Load Command “0000 0011”.
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
6.24.7.8 Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”
on page 307 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
6.24.7.9 Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming the
Flash” on page 307 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.
5. Set BS1 to “0”. This selects low data byte.
6.24.7.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the
Flash” on page 307 for details on Command and Data loading):
1. 1. A: Load Command “0100 0000”.
2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.
4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. 5. Set BS2 to “0”. This selects low data byte.
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Figure 6-121. Programming the FUSES Waveforms
Write Fuse Low byte Write Fuse high byte Write Extended Fuse byte
A C A C A C
0x40 DATA XX 0x40 DATA XX 0x40 DATA XX
DATA
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
6.24.7.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on
page 307 for details on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any
External Programming mode.
The Lock bits can only be cleared by executing Chip Erase.
6.24.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”
on page 307 for details on Command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be
read at DATA (“0” means programmed).
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be
read at DATA (“0” means programmed).
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now
be read at DATA (“0” means programmed).
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at
DATA (“0” means programmed).
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Figure 6-122. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
Fuse Low Byte 0
0
Extended Fuse Byte 1
DATA
BS2
Lock Bits 0
1
BS1
Fuse High Byte 1
BS2
6.24.7.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
6.24.7.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
6.24.7.15 Parallel Programming Characteristics
Figure 6-123. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
XTAL1
tDVXH tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH tPLBX tBVWL

tWLBX
PAGEL tPHPL
tWLWH
WR tPLWL
WLRL
RDY/BSY
tWLRH
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Figure 6-124. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)
tXLXH tXLPH tPLXH

XTAL1
BS1
PAGEL
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 6-123 on page 313 (i.e., tDVXH, tXHXL, and tXLDX) also
apply to loading operation.
Figure 6-125. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE tOHDZ
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 6-123 on page 313 (i.e., tDVXH, tXHXL, and tXLDX) also
apply to reading operation.
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Table 6-126. Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol Parameter Min Typ Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 µA
tDVXH Data and Control Valid before XTAL1 High 67 ns
tXLXH XTAL1 Low to XTAL1 High 200 ns
tXHXL XTAL1 Pulse Width High 150 ns
tXLDX Data and Control Hold after XTAL1 Low 67 ns
tXLWL XTAL1 Low to WR Low 0 ns
tXLPH XTAL1 Low to PAGEL high 0 ns
tPLXH PAGEL low to XTAL1 high 150 ns
tBVPH BS1 Valid before PAGEL High 67 ns
tPHPL PAGEL Pulse Width High 150 ns
tPLBX BS1 Hold after PAGEL Low 67 ns
tWLBX BS2/1 Hold after WR Low 67 ns
tPLWL PAGEL Low to WR Low 67 ns
tBVWL BS1 Valid to WR Low 67 ns
tWLWH WR Pulse Width Low 150 ns
tWLRL WR Low to RDY/BSY Low 0 1 µs
(1)
tWLRH WR Low to RDY/BSY High 3.7 4.5 ms
(2)
tWLRH_CE WR Low to RDY/BSY High for Chip Erase 7.5 9 ms
tXLOL XTAL1 Low to OE Low 0 ns
tBVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 ns
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
6.24.8 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 6-125 on page 306, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
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Figure 6-126. Serial Programming and Verify(1)
+2.7V to 5.5V
VCC
+2.7V to 5.5V(2)
MOSI AVCC
MISO
SCK
XTAL1
RESET
GND
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8V - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
6.24.8.1 Serial Programming Algorithm

When writing serial data to the ATA6612/ATA6613, data is clocked on the rising edge of SCK.
When reading data from the ATA6612/ATA6613, data is clocked on the falling edge of SCK. See
Figure 6-127 on page 318 for timing details.
To program and verify the ATA6612/ATA6613 in the serial programming mode, the following
sequence is recommended (see four byte instruction formats in Table 6-128 on page 318):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
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3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 8 MSB
of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing
the next page (see Table 6-127 on page 318). Accessing the serial programming inter-
face before the Flash write operation completes can result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user must
wait at least tWD_EEPROM before issuing the next byte (see Table 6-127 on page 318). In
a chip erased device, no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
6.24.8.2 Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value 0xFF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be writ-
ten. Note that the entire page is written simultaneously and any address within the page can be
used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming
this value, the user will have to wait for at least tWD_FLASH before programming the next page. As
a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to
contain 0xFF, can be skipped. See Table 6-127 on page 318 for tWD_FLASH value.
6.24.8.3 Data Polling EEPROM

When a new byte has been written and is being programmed into EEPROM, reading the
address location being programmed will give the value 0xFF. At the time the device is ready for
a new byte, the programmed value will read correctly. This is used to determine when the next
byte can be written. This will not work for the value 0xFF, but the user should have the following
in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that
are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-pro-
grammed without chip erasing the device. In this case, data polling cannot be used for the value
0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See
Table 6-127 on page 318 for tWD_EEPROM value.
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Table 6-127. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 3.6 ms
tWD_ERASE 9.0 ms
Figure 6-127. Serial Programming Waveforms

SERIAL DATA INPUT MSB LSB
(MOSI)
SERIAL DATA OUTPUT MSB LSB

(MISO)
SERIAL CLOCK INPUT

(SCK)
SAMPLE
Table 6-128. Serial Programming Instruction Set

Instruction Format
Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation
1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET
Programming Enable
goes low.
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
0010 H000 000a aaaa bbbb bbbb oooo oooo Read H (high or low) data o from
Read Program Memory
Program memory at word address a:b.
0100 H000 000x xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program
Memory page at word address b. Data
Load Program Memory Page low byte must be loaded before Data
high byte is applied within the same
address.
0100 1100 000a aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at address
Write Program Memory Page
a:b.
1010 0000 000x xxaa bbbb bbbb oooo oooo Read data o from EEPROM memory at
Read EEPROM Memory
address a:b.
1100 0000 000x xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at
Write EEPROM Memory
address a:b.
1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page
Load EEPROM Memory Page
buffer. After data is loaded, program
(page access)
EEPROM page.
Write EEPROM Memory Page 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx
Write EEPROM page at address a:b.
(page access)
0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” =
Read Lock bits unprogrammed. See Table 6-113 on
318 ATA6612/ATA6613
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Table 6-128. Serial Programming Instruction Set (Continued)

Instruction Format
Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation
1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to program
Write Lock bits Lock bits. See Table 6-113 on page 300
for details.
Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
Write Fuse bits unprogram. See Table XXX on page
XXX for details.
1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
Write Fuse High bits unprogram. See Table 6-97 on page 270
for details.
1010 1100 1010 0100 xxxx xxxx xxxx xxii Set bits = “0” to program, “1” to
Write Extended Fuse Bits unprogram. See Table 6-116 on page
302 for details.
0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1” =
Read Fuse bits unprogrammed. See Table XXX on
page XXX for details.
0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed,
Read Fuse High bits “1” = unprogrammed. See Table 6-97 on
0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” =
Read Extended Fuse Bits programmed, “1” = unprogrammed. See
Table 6-116 on page 302 for details.
Read Calibration Byte 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte
1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still
Poll RDY/BSY busy. Wait until this bit returns to “0”
before applying another command.
Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = do not care
6.24.8.4 SPI Serial Programming Characteristics

For characteristics of the SPI module see “SPI Timing Characteristics” on page 326.
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6.25 Electrical Characteristics
6.25.1 Absolute Maximum Ratings*

Operating Temperature, Tcase (1) ....................-40° C to +125° C *NOTICE: Stresses beyond those listed under “Absolute Max-
imum Ratings” may cause permanent damage to
Junction Temperature, Tj ..............................-40° C to +125° C
the device. This is a stress rating only and func-
Storage Temperature......................................-65°C to +150°C tional operation of the device at these or other con-
Voltage on any Pin except RESET ditions beyond those indicated in the operational
with respect to Ground ................................ -0.5V to VCC+0.5V sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
Voltage on RESET with respect to Ground ..... -0.5V to +13.0V extended periods may affect device reliability.
Maximum Operating Voltage .............................................6.0V Notes: 1. Tcase means the temperature of the heat slug (back-
DC Current per I/O Pin ................................................40.0 mA side). It is mandatory that this backside temperature
DC Current VCC and GND Pins ................................200.0 mA is ≤ 125° C in the application.
Injection Current at VCC = 0V ...................................±5.0 mA(2) 2. Maximum current per port = ±30 mA
Injection Current at VCC = 5V ......................................±1.0 mA
6.25.2 DC Characteristics
Tcase = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min.(5) Typ. Max.(5) Units
Input Low Voltage, Except
VIL VCC = 2.7V - 5.5V -0.5 0.3VCC(1) V
XTAL1 and Reset pin
Input Low Voltage,
VIL1 VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V
XTAL1 pin
Input Low Voltage, RESET
VIL2 VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V
pin
Input High Voltage, Except
VIH VCC = 2.7V - 5.5V 0.6VCC(2) VCC + 0.5 V
XTAL1 and RESET pins
Input High Voltage, XTAL1
VIH1 VCC = 2.7V - 5.5V 0.7VCC(2) VCC + 0.5 V
pin
Input High Voltage, RESET
VIH2 VCC = 2.7V - 5.5V 0.9VCC(2) VCC + 0.5 V
pin
IOL = 20mA, VCC = 5V 0.8
VOL Output Low Voltage(3) V
IOL = 5mA, VCC = 3V 0.5
IOH = -20mA, VCC = 5V 4.1
VOH Output High Voltage(4) V
IOH = -10mA, VCC = 3V 2.3
Input Leakage VCC = 5.5V, pin low
IIL 50 nA
Current I/O Pin (absolute value)
Input Leakage VCC = 5.5V, pin high
IIH 50 nA
Current I/O Pin (absolute value)
RRST Reset Pull-up Resistor Vcc = 5.0V, Vin = 0V 30 60 kΩ
RPU I/O Pin Pull-up Resistor 20 50 kΩ
320 ATA6612/ATA6613
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6.25.2 DC Characteristics (Continued)

Tcase = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min.(5) Typ. Max.(5) Units
Active 4MHz, VCC = 3V
1.8 3.0 mA
(ATA6612/ATA6613L)
6.0 10 mA
(ATA6612/ATA6613)
10.0 16 mA
(6)
(ATA6612/ATA6613)
Power Supply Current
Idle 4MHz, VCC = 3V
0.4 1 mA
(ATA6612/ATA6613V)
ICC Idle 8MHz, VCC = 5V
1.4 2.4 mA
(ATA6612/ATA6613L)
Idle 15MHz, VCC = 5V
2.8 4 mA
(ATA6612/ATA6613)
WDT enabled, VCC = 3V 8 30 µA
WDT enabled, VCC = 5V 12.6 50 µA
Power-down mode
WDT disabled, VCC = 3V 5 24 µA
WDT disabled, VCC = 5V 6.6 36 µA
Analog Comparator VCC = 5V
VACIO 10 40 mV
Input Offset Voltage Vin = VCC/2
Analog Comparator VCC = 5V
IACLK -50 50 nA
Input Leakage Current Vin = VCC/2
Analog Comparator
tACID VCC = 4.5V 140 ns
Propagation Delay
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATA6612/ATA6613:
1] The sum of all IOL, for ports C0 - C5, should not exceed 100 mA.
2] The sum of all IOL, for ports C6, D0 - D4, should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B7, D5 - D7, should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATA6612/ATA6613:
1] The sum of all IOH, for ports C0 - C5, should not exceed 100 mA.
2] The sum of all IOH, for ports C6, D0 - D4, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B7, D5 - D7, should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. All DC Characteristics contained in this datasheet are based on actual ATA6612 microcontrollers characterization.
6. Values with “Power Reduction REgister - PRR” enabled (0xEF).
321
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6.25.3 External Clock Drive Waveforms
Figure 6-128. External Clock Drive Waveforms

tCHCX
tCHCX tCLCH tCHCL
VIH1
VIL1
tCLCX
tCLCL
6.25.4 External Clock Drive
Table 6-129. External Clock Drive

VCC = 2.7V-5.5V VCC = 4.5V-5.5V
Symbol Parameter Min. Max. Min. Max. Units
1/tCLCL Oscillator Frequency 0 8 0 16 MHz
tCLCL Clock Period 125 62.5 ns
tCHCX High Time 50 25 ns
tCLCX Low Time 50 25 ns
tCLCH Rise Time 1.6 0.5 µs
tCHCL Fall Time 1.6 0.5 µs
Change in period from one
ΔtCLCL 2 2 %
clock cycle to the next
6.25.5 Maximum Speed versus VCC

Maximum frequency is dependent on VCC. As shown in Figure 6-129, the Maximum Frequency
vs. VCC curve is linear between 2.7V < VCC < 4.5V.
Figure 6-129. Maximum Frequency versus VCC, ATA6612/ATA6613
16 MHz
8 MHz
Safe Operating Area
2.7V 4.5V 5.5V
322 ATA6612/ATA6613
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6.26 LIN Re-synchronization Algorithm
6.26.1 Synchronization Algorithm

The possibility to change the value of OSCCAL during the Oscillator operation allows for in-situ
calibration of the slave node to entering Master frames. The principle of operation is to measure
the TBit during the SYNCH Byte and to change the calibration value of OSCCAL to recover from
local frequency drifts due to local voltage or temperature deviation. The algorithm used for the
synchronization of the internal RC oscillator is depicted in Figure 6-130.
Figure 6-130. Dichotomic Algorithm Used for LIN Slave Clock Re-synchronization
Measuring
actual TBit
Y
-2% < Delta(TBit) < 2% STOP:
Oscillator
Calibrated
Decrement
OSCCAL Delta(TBit) > 2%
Increment
Delta(TBit) < -2%
OSCCAL
6.26.2 Precaution Against OSCCAL Discontinuity

The Figure 7-26 on page 340 illustrates the on-purpose discontinuity of RC Frequency versus
OSCCAL value. For one correct re-synchronization, the frequency change must be kept on the
same side of the discontinuity (no change of OSCCAL[7]). Since there will be no device having
frequency changed by more than 10% (see Figure 7-24 on page 339), thus no reason to
change the frequency value by more than 10%. Therefore, when calibration tries to cross the
border because of subsequent increase (or decrease) in OSCCAL values, then the routine must
be stopped.
Example: For parts operating in the lower part of the curve, if New_OSCCAL >127 then
New_OSCCAL = 127. Similar for parts operating on the high side of the discontinuity.
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6.26.2.1 RC Oscillator Precision for LIN Slave implementation
For LIN slave devices, the precision of the RC oscillator before and after re-synchronization are
described in the Table 6-130.
Table 6-130. Oscillator Tolerance Before and After Re-synchronization Algorithm

(2.7V < VCC < 5.5V, -40° C to +125° C)
Parameter Clock Tolerance ΔF/FMaster
Deviation of slave node clock from the nominal clock rate before
FTOL_UNSYNCH synchronization; relevant for nodes making use of ±14.0%
synchronization and direct SYNCH BREAK detection.
Deviation of slave node clock relative to the master node clock
after synchronization; relevant for nodes making use of
synchronization; any slave node must stay within this tolerance
FTOL_SYNCH for all fields of a frame which follow the SYNCH FIELD. ±2.0%
Note: For communication between any two nodes their bit

rate must not differ by more than ±2%.
7. 2-wire Serial Interface Characteristics

Table 7-1 describes the requirements for devices connected to the 2-wire Serial Bus. The ATA6612/ATA6613 2-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 7-1 on page 326.
Table 7-1. 2-wire Serial Bus Requirements

Symbol Parameter Condition Min Max Units
VIL Input Low-voltage -0.5 0.3 VCC V
VIH Input High-voltage 0.7 VCC VCC + 0.5 V
(1) (2)
Vhys Hysteresis of Schmitt Trigger Inputs 0.05 VCC – V
(1)
VOL Output Low-voltage 3 mA sink current 0 0.4 V
tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb(2,3) 300 ns
tof(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb(2,3) 250 ns
(1) (2)
tSP Spikes Suppressed by Input Filter 0 50 ns
Ii Input Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA
Notes: 1. In ATA6612/ATA6613, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATA6612/ATA6613 2-wire Serial Interface operation. Other devices connected to the 2-wire
Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATA6612/ATA6613 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be
greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the ATA6612/ATA6613 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time
requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATA6612/ATA6613 devices connected to the
bus may communicate at full speed (400 kHz) with other ATA6612/ATA6613 devices, as well as any other device with a
proper tLOW acceptance margin.
324 ATA6612/ATA6613
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ATA6612/ATA6613
Table 7-1. 2-wire Serial Bus Requirements (Continued)

Symbol Parameter Condition Min Max Units
Ci(1) Capacitance for each I/O Pin – 10 pF
fSCL SCL Clock Frequency fCK(4) (5)
> max(16fSCL, 250kHz) 0 400 kHz
V CC – 0,4V 1000ns
fSCL ≤100 kHz ---------------------------- ------------------- Ω
3mA Cb
Rp Value of Pull-up resistor
V CC – 0,4V 300ns
fSCL > 100 kHz ---------------------------- ---------------- Ω
3mA Cb
fSCL ≤100 kHz 4.0 – µs

tHD;STA Hold Time (repeated) START Condition
fSCL > 100 kHz 0.6 – µs
fSCL ≤100 kHz (6)
4.7 – µs
tLOW Low Period of the SCL Clock
(7)
fSCL > 100 kHz 1.3 – µs
tHIGH High period of the SCL clock
fSCL > 100 kHz 0.6 – µs
tSU;STA Set-up time for a repeated START condition
fSCL > 100 kHz 0.6 – µs
fSCL ≤100 kHz 0 3.45 µs
tHD;DAT Data hold time
fSCL > 100 kHz 0 0.9 µs
fSCL ≤100 kHz 250 – ns
tSU;DAT Data setup time
fSCL > 100 kHz 100 – ns
tSU;STO Setup time for STOP condition
fSCL > 100 kHz 0.6 – µs
Bus free time between a STOP and START fSCL ≤100 kHz 4.7 – µs
tBUF
condition fSCL > 100 kHz 1.3 – µs
Notes: 1. In ATA6612/ATA6613, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATA6612/ATA6613 2-wire Serial Interface operation. Other devices connected to the 2-wire
Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATA6612/ATA6613 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be
greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the ATA6612/ATA6613 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time
requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATA6612/ATA6613 devices connected to the
bus may communicate at full speed (400 kHz) with other ATA6612/ATA6613 devices, as well as any other device with a
proper tLOW acceptance margin.
325
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Figure 7-1. 2-wire Serial Bus Timing
tof tHIGH tr
tLOW tLOW
SCL
tSU;STA tHD;STA tHD;DAT tSU;DAT
tSU;STO
SDA
tBUF
7.1 SPI Timing Characteristics

See Figure 7-2 on page 327 and Figure 7-3 on page 327 for details.
Table 7-2. SPI Timing Parameters

Description Mode Min Typ Max
1 SCK period Master See Table 6-69 on page 190
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • tsck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
ns
10 SCK period Slave 4 • tck
11 SCK high/low(1) Slave 2 • tck
12 Rise/Fall time Slave 1600
13 Setup Slave 10
14 Hold Slave tck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
326 ATA6612/ATA6613
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Figure 7-2. SPI Interface Timing Requirements (Master Mode)
SS
6 1
SCK
(CPOL = 0)
2 2
SCK
(CPOL = 1)
4 5 3
MISO
MSB ... LSB
(Data Input)
7 8
MOSI
MSB ... LSB
(Data Output)
Figure 7-3. SPI Interface Timing Requirements (Slave Mode)
SS
10 16
9
SCK
(CPOL = 0)
11 11
SCK
(CPOL = 1)
13 14 12
MOSI
MSB ... LSB
(Data Input)
15 17
MISO
MSB ... LSB X
(Data Output)
327
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7.2 ADC Characteristics
Table 7-3. ADC Characteristics

Resolution 10 Bits
VREF = 4V, VCC = 4V,
2 3.5 LSB
Absolute accuracy (Including ADC clock = 200 kHz
INL, DNL, quantization error, VREF = 4V, VCC = 4V,
gain and offset error) ADC clock = 200 kHz 2 3.5 LSB
Noise Reduction Mode
Integral Non-Linearity (INL) 0.6 2.5 LSB
ADC clock = 200 kHz
Differential Non-Linearity VREF = 4V, VCC = 4V,
0.40 1.0 LSB
(DNL) ADC clock = 200 kHz
Gain Error -3.5 -1.3 3.5 LSB
ADC clock = 200 kHz
Offset Error 1.8 3.5 LSB
ADC clock = 200 kHz
Conversion Time Free Running Conversion 13 cycles µs
Clock Frequency 50 200 kHz
AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
VREF Reference Voltage 1.0 AVCC V
VIN Input Voltage GND VREF V
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 22.4 32 41.6 kΩ
RAIN Analog Input Resistance 100 MΩ
328 ATA6612/ATA6613
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7.3 ATA6612/ATA6613 Typical Characteristics
Note: Values of Temp refer to Tcase
7.3.1 Active Supply Current
Figure 7-4. Active Supply Current versus Frequency (1 MHz to 20 MHz), Temp = 125°C
20
18
16
5.5 V
14
5.0 V
ICC(mA)
12
4.5 V
10
8 3.3 V
3.0 V
6
2.7 V
4
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
Figure 7-5. Idle Supply Current versus Frequency (1 MHz to 20 MHz), Temp = 125°C
6
4
5.5 V
ICC(mA)
5.0 V
4.5 V
2 3.3 V
3.0 V
2.7 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
329
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7.3.1.1 Power-down Supply Current
Figure 7-6. Power-down Supply Current versus VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. V CC

WATCHDOG TIMER DISABLED / Vt Fast corners excluded
5 125
85
ICC (uA)
4
25
3 -40
0
3 3.5 4 4.5 5 5.5
V CC (V)
Figure 7-7. Power-down Supply Current versus VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. V CC

WATCHDOG TIMER DISABLED / Vt Fast corners excluded
5 125
85
ICC (uA)
4
25
3 -40
0
2.5 3 3.5 4 4.5 5 5.5
V CC (V)
330 ATA6612/ATA6613
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7.3.1.2 Pin Pull-up
Figure 7-8. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

VCC = 5V
160
125
140
120
-40
100
IOP (uA)
80
60
40
20
0
0 1 2 3 4 5 6
V OP (V)
Figure 7-9. Output Low Voltage vs. Output Low Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

Vcc = 5.00v
0.8
0.7
0.6 125 ˚C
85 ˚C
0.5
25 ˚C
Vol (V)
0.4
-40 ˚C
0.3
0.2
0.1
0
0 2 4 6 8 10 12 14 16 18 20
IOL (mA)
331
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Figure 7-10. Output Low Voltage vs. Output Low Current (VCC = 3V)

Vcc = 3V
1.2
1 125 ˚C
85 ˚C
0.8
IOL (mA)
25 ˚C
0.6
-40 ˚C
0.4
0.2
0
0 2 4 6 8 10 12 14 16 18 20
VOL (V)
Figure 7-11. Output High Voltage vs. Output High Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

Vcc = 5.00v
5.2
4.8
Voh (V)
4.6
-40 ˚C
25 ˚C
4.4 85 ˚C
125 ˚C
4.2
4
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
332 ATA6612/ATA6613
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Figure 7-12. Output High Voltage vs. Output High Current (VCC = 3V)

V CC = 3V
3.5
2.5
-40 ˚C
25 ˚C
Current (V)
2 85 ˚C
125 ˚C
1.5
0.5
0
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
Figure 7-13. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

VCC = 5V
160
125
140
120
-40
100
IOP (uA)
80
60
40
20
0
0 1 2 3 4 5 6
V OP (V)
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7.3.1.3 Pin Driver Strength
Figure 7-14. Output Low Voltage versus Output Low Current (VCC = 5V)

Vcc = 5.00v
0.8
0.7
0.6 125 ˚C
85 ˚C
0.5
25 ˚C
Vol (V)
0.4
-40 ˚C
0.3
0.2
0.1
0
0 2 4 6 8 10 12 14 16 18 20
IOL (mA)
Figure 7-15. Output Low Voltage versus Output Low Current (VCC = 3V)

Vcc = 3V
1.2
1 125 ˚C
85 ˚C
0.8
IOL (mA)
25 ˚C
0.6
-40 ˚C
0.4
0.2
0
0 2 4 6 8 10 12 14 16 18 20
VOL (V)
334 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 7-16. Output High Voltage versus Output High Current (VCC = 5V)

Vcc = 5.00v
5.2
4.8
Voh (V)
4.6
-40 ˚C
25 ˚C
4.4 85 ˚C
125 ˚C
4.2
4
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
Figure 7-17. Output High Voltage versus Output High Current (VCC = 3V)

V CC = 3V
3.5
2.5
-40 ˚C
25 ˚C
Current (V)
2 85 ˚C
125 ˚C
1.5
0.5
0
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
335
9111E–AUTO–07/08
7.3.1.4 Pin Thresholds and Hysteresis
Figure 7-18. I/O Pin Input Threshold versus VCC (VIH, I/O Pin Read as 1)
IO INPUT THRESHOLD VOLTAGE vs. VCC

VIH, IO PIN READ AS '1'
3.5
2.5 125
85
Vih (V)
25
2
-40
1.5
1
2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Figure 7-19. I/O Pin Input Threshold versus VCC (VIL, I/O Pin Read as 0)
IO INPUT THRESHOLD VOLTAGE vs. VCC

VIL, IO PIN READ AS '0'
3
125 ˚C
-40 ˚C
2.5
2
Vil (V)
1.5
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5 6
V CC (V)
336 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 7-20. Reset Input Threshold Voltage versus VCC (VIH, Reset Pin Read as 1)
RESET INPUT THRESHOLD VOLTAGE vs. V CC

VIH, IO PIN READ AS '1'
3.5
-40 ˚C
2.5 25 ˚C
Threshold (V)
85 ˚C
125 ˚C
2
1.5
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Figure 7-21. Reset Input Threshold Voltage versus VCC (VIL, Reset Pin Read as 0)
2.5 125 ˚C
85 ˚C
25 ˚C
-40 ˚C
2
Threshold (V)
1.5
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
337
9111E–AUTO–07/08
7.3.1.5 Internal Oscillator Speed
Figure 7-22. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
130
128
126
-40 ˚C
124 25 ˚C
122
FRC (kHz)
120
85 ˚C
118 125 ˚C
116
114
112
110
2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Figure 7-23. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED XXXMHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.4
8.3
8.2
5.0 V
8.1
FRC (MHz)
2.7 V
8
7.9
7.8
7.7
7.6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature
338 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 7-24. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
CALIBRATED XXXMHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
8.4
8.2
125 ˚C
85 ˚C
8 25 ˚C
-40 ˚C
FRC (MHz)
7.8
7.6
7.4
7.2
7
2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Figure 7-25. Calibrated 8 MHz RC Oscillator Frequency vs. OSCAL Value (for ATA6613)
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

Vcc = 3.0v
16
125 ˚C
85 ˚C
14
25 ˚C
-40 ˚C
12
FRC (MHz)
10
2
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
339
9111E–AUTO–07/08
Figure 7-26. Calibrated 8 MHz RC Oscillator Frequency vs. OSCAL Value (for ATA6612 only)
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
14 125 ˚C
85 ˚C
25 ˚C
12 -40 ˚C
10
FRC (MHz)
2
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
7.3.1.6 BOD Thresholds and Analog Comparator Offset
Figure 7-27. BOD Threshold versus Temperature (BODLEVEL is 4.0V)

4.6
4.5
Threshold (V)
Rising VCC
4.4
4.3
Falling VCC
4.2
4.1
4
-55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Temperature (C)
340 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 7-28. BOD Threshold versus Temperature (BODLEVEL is 2.7V)

3
2.9
Threshold (V)
2.8
Rising VCC
2.7
Falling VCC
2.6
2.5
2.4
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (C)
Figure 7-29. Bandgap Voltage versus VCC

1.1
1.095
Bandgap Voltage (V)
1.09
85 ˚C
25 ˚C
125 ˚C
1.085
1.08
-40 ˚C
1.075
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
341
9111E–AUTO–07/08
7.3.1.7 Peripheral Units
Figure 7-30. Analog to Digital Converter GAIN versus VCC

0.00
-0.20
-0.40
Error (LSB) -0.60
4V IDLE
-0.80
4V STD
-1.00
-1.20
-1.40
-1.60
-50 0 50 100 150
Temperature
Figure 7-31. Analog to Digital Converter OFFSET versus VCC

2.50
2.00
Error (LSB)
1.50
4V IDLE
4V STD
1.00
0.50
0.00
-50 0 50 100 150
Temperature
342 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 7-32. Analog to Digital Converter DNL versus VCC

0.40
0.35
0.30
Error (LSB)
0.25 4V IDLE
0.20
4V STD
0.15
0.10
0.05
0.00
-50 0 50 100 150
Temperature
Figure 7-33. Analog to Digital Converter INL versus VCC

0.70
0.60
0.50
Error (LSB)
0.40
4V IDLE
4V STD
0.30
0.20
0.10
0.00
-50 0 50 100 150
Temperature
343
9111E–AUTO–07/08
7.4 Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved – – – – – – – –
(0xFE) Reserved – – – – – – – –
(0xFD) Reserved – – – – – – – –
(0xFC) Reserved – – – – – – – –
(0xFB) Reserved – – – – – – – –
(0xFA) Reserved – – – – – – – –
(0xF9) Reserved – – – – – – – –
(0xF8) Reserved – – – – – – – –
(0xF7) Reserved – – – – – – – –
(0xF6) Reserved – – – – – – – –
(0xF5) Reserved – – – – – – – –
(0xF4) Reserved – – – – – – – –
(0xF3) Reserved – – – – – – – –
(0xF2) Reserved – – – – – – – –
(0xF1) Reserved – – – – – – – –
(0xF0) Reserved – – – – – – – –
(0xEF) Reserved – – – – – – – –
(0xEE) Reserved – – – – – – – –
(0xED) Reserved – – – – – – – –
(0xEC) Reserved – – – – – – – –
(0xEB) Reserved – – – – – – – –
(0xEA) Reserved – – – – – – – –
(0xE9) Reserved – – – – – – – –
(0xE8) Reserved – – – – – – – –
(0xE7) Reserved – – – – – – – –
(0xE6) Reserved – – – – – – – –
(0xE5) Reserved – – – – – – – –
(0xE4) Reserved – – – – – – – –
(0xE3) Reserved – – – – – – – –
(0xE2) Reserved – – – – – – – –
(0xE1) Reserved – – – – – – – –
(0xE0) Reserved – – – – – – – –
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATA6612/ATA6613 is
a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for
the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
5. Only valid for ATA6612/ATA6613
344 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
7.4 Register Summary (Continued)

(0xDF) Reserved – – – – – – – –
(0xDE) Reserved – – – – – – – –
(0xDD) Reserved – – – – – – – –
(0xDC) Reserved – – – – – – – –
(0xDB) Reserved – – – – – – – –
(0xDA) Reserved – – – – – – – –
(0xD9) Reserved – – – – – – – –
(0xD8) Reserved – – – – – – – –
(0xD7) Reserved – – – – – – – –
(0xD6) Reserved – – – – – – – –
(0xD5) Reserved – – – – – – – –
(0xD4) Reserved – – – – – – – –
(0xD3) Reserved – – – – – – – –
(0xD2) Reserved – – – – – – – –
(0xD1) Reserved – – – – – – – –
(0xD0) Reserved – – – – – – – –
(0xCF) Reserved – – – – – – – –
(0xCE) Reserved – – – – – – – –
(0xCD) Reserved – – – – – – – –
(0xCC) Reserved – – – – – – – –
(0xCB) Reserved – – – – – – – –
(0xCA) Reserved – – – – – – – –
(0xC9) Reserved – – – – – – – –
(0xC8) Reserved – – – – – – – –
(0xC7) Reserved – – – – – – – –
(0xC6) UDR0 USART I/O Data Register 212
(0xC5) UBRR0H USART Baud Rate Register High 217
(0xC4) UBRR0L USART Baud Rate Register Low 217
(0xC3) Reserved – – – – – – – –
UCSZ01 UCSZ00 /
(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCPOL0 215/228
/UDORD0 UCPHA0
(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 214
(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 213
345
9111E–AUTO–07/08
(0xBF) Reserved – – – – – – – –
(0xBE) Reserved – – – – – – – –
(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 – 241
(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 238
(0xBB) TWDR 2-wire Serial Interface Data Register 240
(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 241
(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 240
(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 238
(0xB7) Reserved – – – – – – –
(0xB6) ASSR – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 181
(0xB5) Reserved – – – – – – – –
(0xB4) OCR2B Timer/Counter2 Output Compare Register B 178
(0xB3) OCR2A Timer/Counter2 Output Compare Register A 178
(0xB2) TCNT2 Timer/Counter2 (8-bit) 178
(0xB1) TCCR2B FOC2A FOC2B – – WGM22 CS22 CS21 CS20 177
(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 174
(0xAF) Reserved – – – – – – – –
(0xAE) Reserved – – – – – – – –
(0xAD) Reserved – – – – – – – –
(0xAC) Reserved – – – – – – – –
(0xAB) Reserved – – – – – – – –
(0xAA) Reserved – – – – – – – –
(0xA9) Reserved – – – – – – – –
(0xA8) Reserved – – – – – – – –
(0xA7) Reserved – – – – – – – –
(0xA6) Reserved – – – – – – – –
(0xA5) Reserved – – – – – – – –
(0xA4) Reserved – – – – – – – –
(0xA3) Reserved – – – – – – – –
(0xA2) Reserved – – – – – – – –
(0xA1) Reserved – – – – – – – –
(0xA0) Reserved – – – – – – – –
(0x9F) Reserved – – – – – – – –
346 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613

(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) Reserved – – – – – – – –
(0x96) Reserved – – – – – – – –
(0x95) Reserved – – – – – – – –
(0x94) Reserved – – – – – – – –
(0x93) Reserved – – – – – – – –
(0x92) Reserved – – – – – – – –
(0x91) Reserved – – – – – – – –
(0x90) Reserved – – – – – – – –
(0x8F) Reserved – – – – – – – –
(0x8E) Reserved – – – – – – – –
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved – – – – – – – –
(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 159
(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 159
(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 159
(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 159
(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 160
(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 160
(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 159
(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 159
(0x83) Reserved – – – – – – – –
(0x82) TCCR1C FOC1A FOC1B – – – – – – 158
(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 157
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 155
(0x7F) DIDR1 – – – – – – AIN1D AIN0D 264
(0x7E) DIDR0 – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 281
347
9111E–AUTO–07/08
(0x7D) Reserved – – – – – – – –
(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 277
(0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 281
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 278
(0x79) ADCH ADC Data Register High byte 280
(0x78) ADCL ADC Data Register Low byte 280
(0x77) Reserved – – – – – – – –
(0x76) Reserved – – – – – – – –
(0x75) Reserved – – – – – – – –
(0x74) Reserved – – – – – – – –
(0x73) Reserved – – – – – – – –
(0x72) Reserved – – – – – – – –
(0x71) Reserved – – – – – – – –
(0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 179
(0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 160
(0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 130
(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 112
(0x6C) PCMSK1 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 112
(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 112
(0x6A) Reserved – – – – – – – –
(0x69) EICRA – – – – ISC11 ISC10 ISC01 ISC00 109
(0x68) PCICR – – – – – PCIE2 PCIE1 PCIE0
(0x67) Reserved – – – – – – – –
(0x66) OSCCAL Oscillator Calibration Register 58
(0x65) Reserved – – – – – – – –
(0x64) PRR PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC 66
(0x63) Reserved – – – – – – – –
(0x62) Reserved – – – – – – – –
(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 61
(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 78
348 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613

0x3F (0x5F) SREG I T H S V N Z C 35
5.
0x3E (0x5E) SPH – – – – – (SP10) SP9 SP8 37
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 37
0x3C (0x5C) Reserved – – – – – – – –
0x3B (0x5B) Reserved – – – – – – – –
0x3A (0x5A) Reserved – – – – – – – –
0x39 (0x59) Reserved – – – – – – – –
0x38 (0x58) Reserved – – – – – – – –
0x37 (0x57) SPMCSR SPMIE (RWWSB)5. – (RWWSRE)5. BLBSET PGWRT PGERS SELFPRGEN 289
0x36 (0x56) Reserved – – – – – – – –
0x35 (0x55) MCUCR – – – PUD – – IVSEL IVCE
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF
0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE 63
0x32 (0x52) Reserved – – – – – – – –
0x31 (0x51) Reserved – – – – – – – –
0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 263
0x2F (0x4F) Reserved – – – – – – – –
0x2E (0x4E) SPDR SPI Data Register 191
0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 191
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 189
0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 50
0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 50
0x29 (0x49) Reserved – – – – – – – –
0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B
0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A
0x26 (0x46) TCNT0 Timer/Counter0 (8-bit)
0x25 (0x45) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00
0x23 (0x43) GTCCR TSM – – – – – PSRASY PSRSYNC 133/183
5.
0x22 (0x42) EEARH (EEPROM Address Register High Byte) 45
0x21 (0x41) EEARL EEPROM Address Register Low Byte 45
0x20 (0x40) EEDR EEPROM Data Register 45
349
9111E–AUTO–07/08
0x1F (0x3F) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 45
0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 50
0x1D (0x3D) EIMSK – – – – – – INT1 INT0 110
0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 110
0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0
0x1A (0x3A) Reserved – – – – – – – –
0x19 (0x39) Reserved – – – – – – – –
0x18 (0x38) Reserved – – – – – – – –
0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 179
0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 161
0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0
0x14 (0x34) Reserved – – – – – – – –
0x13 (0x33) Reserved – – – – – – – –
0x12 (0x32) Reserved – – – – – – – –
0x11 (0x31) Reserved – – – – – – – –
0x10 (0x30) Reserved – – – – – – – –
0x0F (0x2F) Reserved – – – – – – – –
0x0E (0x2E) Reserved – – – – – – – –
0x0D (0x2D) Reserved – – – – – – – –
0x0C (0x2C) Reserved – – – – – – – –
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 107
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 108
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 108
0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 107
0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 107
0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 107
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 107
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 107
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 107
0x02 (0x22) Reserved – – – – – – – –
0x01 (0x21) Reserved – – – – – – – –
0x0 (0x20) Reserved – – – – – – – –
350 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
7.5 Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ←Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ←Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ←Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ←Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ←Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ←Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ←Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ←Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ←Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ←Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ←Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ←Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ←Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ←0xFF −Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ←0x00 −Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ←Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ←Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ←Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ←Rd −1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ←Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ←Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ←0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ←Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ←Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ←Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ←(Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ←(Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ←(Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ←PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ←Z None 2
JMP(1) k Direct Jump PC ←k None 3
RCALL k Relative Subroutine Call PC ←PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ←Z None 3
CALL (1)
k Direct Subroutine Call PC ←k None 4
RET Subroutine Return PC ←STACK None 4
RETI Interrupt Return PC ←STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ←PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd −Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd −Rr −C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd −K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ←PC + 2 or 3 None 1/2/3
Note: 1. These instructions are only available in ATA6613
351
9111E–AUTO–07/08
7.5 Instruction Set Summary (Continued)
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ←PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ←PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ←PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ←PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ←PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ←PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ←PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ←PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ←PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ←PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ←PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ←PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ←PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ←PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ←PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ←PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ←PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ←PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ←1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ←0 None 2
LSL Rd Logical Shift Left Rd(n+1) ←Rd(n), Rd(0) ←0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ←Rd(n+1), Rd(7) ←0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)←Rd(n),C ←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ←1 SREG(s) 1
BCLR s Flag Clear SREG(s) ←0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ←Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ←T None 1
SEC Set Carry C ←1 C 1
CLC Clear Carry C ←0 C 1
SEN Set Negative Flag N ←1 N 1
CLN Clear Negative Flag N ←0 N 1
SEZ Set Zero Flag Z ←1 Z 1
CLZ Clear Zero Flag Z ←0 Z 1
SEI Global Interrupt Enable I ←1 I 1
352 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613

CLI Global Interrupt Disable I ←0 I 1
SES Set Signed Test Flag S ←1 S 1
CLS Clear Signed Test Flag S ←0 S 1
SEV Set Twos Complement Overflow. V ←1 V 1
CLV Clear Twos Complement Overflow V ←0 V 1
SET Set T in SREG T ←1 T 1
CLT Clear T in SREG T ←0 T 1
SEH Set Half Carry Flag in SREG H ←1 H 1
CLH Clear Half Carry Flag in SREG H ←0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ←Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ←Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ←K None 1
LD Rd, X Load Indirect Rd ←(X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ←(X), X ←X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ←X - 1, Rd ←(X) None 2
LD Rd, Y Load Indirect Rd ←(Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ←(Y), Y ←Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ←Y - 1, Rd ←(Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ←(Y + q) None 2
LD Rd, Z Load Indirect Rd ←(Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ←(Z), Z ←Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ←Z - 1, Rd ←(Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ←(Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ←(k) None 2
ST X, Rr Store Indirect (X) ←Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ←Rr, X ←X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ←X - 1, (X) ←Rr None 2
ST Y, Rr Store Indirect (Y) ←Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ←Rr, Y ←Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ←Y - 1, (Y) ←Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ←Rr None 2
ST Z, Rr Store Indirect (Z) ←Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ←Rr, Z ←Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ←Z - 1, (Z) ←Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ←Rr None 2
STS k, Rr Store Direct to SRAM (k) ←Rr None 2
LPM Load Program Memory R0 ←(Z) None 3
LPM Rd, Z Load Program Memory Rd ←(Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ←(Z), Z ←Z+1 None 3
SPM Store Program Memory (Z) ←R1:R0 None -
IN Rd, P In Port Rd ←P None 1
OUT P, Rr Out Port P ←Rr None 1
353
9111E–AUTO–07/08
PUSH Rr Push Register on Stack STACK ←Rr None 2
POP Rd Pop Register from Stack Rd ←STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A
354 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
8. Application
Figure 8-1. Typical LIN Slave Application
C1
100 nF
48
47
46
45
44
43
42
41
40
39
38
37
PB4
PB3
PB2
PB1
PB0
PD7
PD6
PD5
PB7
PB6
VDD2
GND2
1 36
100 nF PB5 VDD1 C2
2 35
AVDD GND1 100 nF
3 34 220 pF
ADC6 PD4
4 33
AREF PD3 LIN
5 32
GND4 LIN
6 31
ADC7 ATA6612/ATA6613 GND
7 30
PC0 WAKE
8 29
PC1 NTRIG
9 28
PC2 EN VBAT
10 27
PC3 VS
11 26
PC4 VCC PVCC
12 25 GND
WD_OSC
PC5 PVCC
MODE
KL_15
NRES
RXD
TDX
PC6
PD0
PD1
PD2
INH
TM
+
13
14
15
16
17
18
19
20
21
22
23
24
100 nF 22 µF
+
100 nF 100 nF 10 µF
10 kΩ
51 kΩ
KL_15
1
INH DEBUG PB4 PVCC
PB5 PB3
51 kΩ 10 kΩ PC6
ISP
Note: All open pins of the SiP can be used for application-specific purposes.
AVR: Internal clock, no ADC application, TXD, RXD, NRES, EN and NTRIG connected for LIN
Slave. The connection between the LIN-SBC and the AVR requires the software being pro-
grammed correspondingly.
SBC: LIN slave operation with watchdog, 5V regulator and KL15 wake up
RF emissions: Best results for RF emissions will be achieved by connecting the blocking capaci-
tors of the microcontroller supply (C1 and C2) between the microcontroller pins and the
GND/PVCC line. See also Figure 8-1.
355
9111E–AUTO–07/08
Figure 8-2. Typical LIN Master Application
1
PB4 PVCC
22 pF 22 pF PB5 PB3
XTAL C1 PC6
48 100 nF ISP
47
46
45
44
43
42
41
40
39
38
37
PB4
PB3
PB2
PB1
PB0
PD7
PD6
PD5
PB7
PB6
VDD2
GND2
1 36
100 nF PB5 VDD1 C2
2 35
AVDD GND1 100 nF
3 34 220 pF
100 nF ADC6 PD4
4 33
AREF PD3 LIN
5 32
GND4 LIN
6 31
ADC7 ATA6612/ATA6613 GND 33 kΩ WAKE
7 30
PC0 WAKE
8 29 10 nF
PC1 NTRIG
9 28 10 kΩ
PC2 EN VBAT
10 27
PC3 VS
11 26
PC4 VCC PVCC
12 25 GND
WD_OSC
PC5 PVCC
MODE
KL_15
NRES
RXD
1 kΩ
TDX
PC6
PD0
PD1
PD2
INH
TM
+
13
14
15
16
17
18
19
20
21
22
23
24
100 nF 22 µF
+
100 nF 10 µF
ADC6 ADC7 10 kΩ
AVR: TXD, RXD, NRES and EN connected for LIN Master. The connection between the LIN-SBC
and the AVR requires the software being programmed correspondingly. Analog Digital Converter
active with port ADC6 and ADC7; system clock from external crystal.
LIN-SBC: Master application, 1k Master resistance connected via diode to VBAT, local wake up
via pin WAKE; watchdog is disabled.
356 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
Figure 8-3. LIN Slave Application with Minimum External Components
C1
100 nF
48
47
46
45
44
43
42
41
40
39
38
37
PB4
PB3
PB2
PB1
PB0
PD7
PD6
PD5
PB7
PB6
VDD2
GND2
1 36
100 nF PB5 VDD1 C2
2 35
AVDD GND1 100 nF 220 pF
3 34
ADC6 PD4
4 33
AREF PD3 LIN
5 32
GND4 LIN
6 31
ADC7 ATA6612/ATA6613 GND
7 30
PC0 WAKE
8 29
PC1 NTRIG
9 28
PC2 EN VBAT
10 27
PC3 VS
11 26
PC4 VCC PVCC
12 25 GND
WD_OSC
PC5 PVCC
MODE
KL_15
NRES
RXD
TDX
PC6
PD0
PD1
PD2
INH
TM
+
13
14
15
16
17
18
19
20
21
22
23
24
100 nF 22 µF
+
100 nF 10 µF
10 kΩ
1
INH PB4 PVCC
PB5 PB3
PC6
ISP
AVR: Internal clock, no ADC application, TXD, RXD, NRES and EN connected for LIN Slave. The
connection between the LIN-SBC and the AVR requires the software being programmed corre-
spondingly.
SBC: LIN slave operation with 5V regulator
357
9111E–AUTO–07/08
Figure 8-4. Typical LIN Master Application
LIN Master Pull-up Switched Off during Sleep Mode
1
PB4 PVCC
22 pF 22 pF PB5 PB3
XTAL C1 PC6
100 nF ISP
48
47
46
45
44
43
42
41
40
39
38
37
PB4
PB3
PB2
PB1
PB0
PD7
PD6
PD5
PB7
PB6
VDD2
GND2
1 36
100 nF PB5 VDD1 C2
2 35
AVDD GND1 100 nF
3 34 220 pF
100 nF ADC6 PD4 10 kΩ
4 33
AREF PD3 LIN
5 32
GND4 LIN
6 31
ADC7 ATA6612/ATA6613 GND 33 kΩ WAKE
7 30
PC0 WAKE
8 29 10 nF
PC1 NTRIG
9 28 10 kΩ
PC2 EN VBAT
10 27
PC3 VS
11 26
PC4 VCC PVCC
12 25 GND
WD_OSC
PC5 PVCC
MODE
KL_15
NRES
RXD
1 kΩ
TDX
PC6
PD0
PD1
PD2
INH
TM
+
13
14
15
16
17
18
19
20
21
22
23
24
100 nF 22 µF
+
100 nF 10 µF
ADC6 ADC7
10 kΩ
AVR: TXD, RXD, NRES and EN connected for LIN Master. The connection between the LIN-SBC
and the AVR requires the software being programmed correspondingly. Analog Digital Converter
active with port ADC6 and ADC7; system clock from external crystal.
LIN-SBC: Master application, 1k Master resistance connected via diode to VBAT, local wake up
via pin WAKE; watchdog is disabled.
358 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
9. Ordering Information
Extended Type Number Program Memory Package MOQ
ATA6612P-PLQW 8 kB flash QFN48, 7× 7 4,000 pieces
ATA6612P-PLPW 8 kB flash QFN48, 7× 7 1,000 pieces
ATA6613P-PLQW 16 kB flash QFN48, 7× 7 4,000 pieces
ATA6613P-PLPW 16 kB flash QFN48, 7× 7 1,000 pieces
10. Package Information
Package: QFN 48 - 7 x 7
Exposed pad 5.8 x 5.8
Dimensions in mm
Not indicated tolerances ± 0.05 7
1 max. 5.8
+0
0.05-0.05 5.5
48 37 48
1 36 1
technical drawings
according to DIN
specifications
12 25 12
0.23
24 13
0.4±0.1
0.5 nom.
Drawing-No.: 6.543-5089.03-4
Issue: 1; 22.01.03
359
9111E–AUTO–07/08
11. Errata
11.1 ATA6612
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Flash security
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in
the cycle before an overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
2. Flash security
Improved security functions in Flash memory.
11.2 ATA6613
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Flash security
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in
the cycle before an overflow interrupt occurs, the interrupt may be lost.
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
2. Flash security
Improved security functions in Flash memory.
360 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
• Table 2-2 “Maximum Ratings of the SiP” on page 4 changed
• Section 4 “Absolute Maximum Ratings” on page 20 changed
• Figure 8-1 “Typical LIN Slave Application” on page 355 changed
9111E-AUTO-07/08 • Figure 8-2 “Typical LIN Master Application” on page 356 changed
• Figure 8-3 “LIN Slave Application with Minimum External Components”
on page 357 changed
• Figure 8-4 “Typical LIN Master Application LIN Master Pull-up Switched
Off during Sleep Mode” on page 358 added
• Figure 3-1 “Block Diagram” on page 6 changed
• Section 3.3 “Functional Description” on pages 7 to 18 changed
9111D-AUTO-06/08
• Section 6.5.3.2 “The EEPROM Address Register – EEARH and EEARL”
on page 45 changed
9111C-AUTO-02/08 • Figure 8-2 “Typical LIN Master Application” on page 356 changed
• Section 5 “Electrical Characteristics” on pages 21 to 26 changed
• Section 6.6.6 “Calibrated Internal RC Oscillator” on page 57 changed
9111B-AUTO-11/07
• Figure 8-3 “LIN Slave Application with Minimum External Components
on page 357 added
361
9111E–AUTO–07/08
13. Table of Contents
General Features....................................................................................... 1
1 Description ............................................................................................... 1
2 Pin Configuration ..................................................................................... 2
3 LIN System-basis-chip Block .................................................................. 5

3.1 Features ...............................................................................................................5
3.2 Description ...........................................................................................................5
3.3 Functional Description ..........................................................................................7
4 Absolute Maximum Ratings .................................................................. 20
5 Electrical Characteristics ...................................................................... 21
6 Microcontroller Block ............................................................................ 28

6.1 Features .............................................................................................................28
6.2 Overview ............................................................................................................29
6.3 About Code Examples .......................................................................................33
6.4 AVR CPU Core ..................................................................................................33
6.5 AVR ATA6612/ATA6613 Memories ...................................................................41
6.6 System Clock and Clock Options .......................................................................51
6.7 Power Management and Sleep Modes .............................................................62
6.8 System Control and Reset .................................................................................68
6.9 Interrupts ............................................................................................................79
6.10 I/O-Ports .............................................................................................................88
6.11 External Interrupts ............................................................................................108
6.12 8-bit Timer/Counter0 with PWM .......................................................................113
6.13 Timer/Counter0 and Timer/Counter1 Prescalers .............................................131
6.14 16-bit Timer/Counter1 with PWM .....................................................................133
6.15 8-bit Timer/Counter2 with PWM and Asynchronous Operation .......................162
6.16 Serial Peripheral Interface – SPI ......................................................................184
6.17 USART0 ...........................................................................................................193
6.18 USART in SPI Mode ........................................................................................220
6.19 2-wire Serial Interface ......................................................................................230
6.20 Analog Comparator ...........................................................................................262
6.21 Analog-to-Digital Converter ..............................................................................265
6.22 debugWIRE On-chip Debug System ................................................................282
362 ATA6612/ATA6613
9111E–AUTO–07/08
ATA6612/ATA6613
6.23 Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and

ATA6613 ........................................................................................................284
6.24 Memory Programming ......................................................................................300
6.25 Electrical Characteristics ..................................................................................320
6.26 LIN Re-synchronization Algorithm ....................................................................323
7 2-wire Serial Interface Characteristics ............................................... 324

7.1 SPI Timing Characteristics ...............................................................................326
7.2 ADC Characteristics .........................................................................................328
7.3 ATA6612/ATA6613 Typical Characteristics .....................................................329
7.4 Register Summary ...........................................................................................344
7.5 Instruction Set Summary ..................................................................................351
8 Application ........................................................................................... 355
9 Ordering Information ........................................................................... 358
10 Package Information ............................................................................ 358
11 Errata ..................................................................................................... 359

11.1 ATA6612 ..........................................................................................................359
11.2 ATA6613 ..........................................................................................................359
12 Revision History ................................................................................... 360
13 Table of Contents ................................................................................. 361
363
9111E–AUTO–07/08
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General Features

• Single-package Fully-integrated AVR® 8-bit Microcontroller with LIN Transceiver,

Figure 1-1. Application Diagram

Table 2-1. Pin Description

Table 2-1. Pin Description (Continued)

3. LIN System-basis-chip Block

3.3 Functional Description

3.3.1 Physical Layer Compatibility

3.3.2 Supply Pin (VS)

3.3.3 Ground Pin (GND)

3.3.4 Voltage Regulator Output Pin (VCC)

3.3.5 Voltage Regulator Sense Pin (PVCC)

3.3.6 Bus Pin (LIN)

3.3.8 TXD Dominant Time-out Function

3.3.9 Output Pin (RXD)

3.3.10 Enable Input Pin (EN)

3.3.11 Wake Input Pin (WAKE)

3.3.12 Mode Input Pin (MODE)

3.3.13 TM Input Pin

3.3.14 KL_15 Pin

3.3.15 INH Output Pin

3.3.16 Reset Output Pin (NRES)

3.3.17 WD_OSC Output Pin

3.3.18 NTRIG Input Pin

3.3.19 Wake-up Events from Sleep or Silent Mode

Figure 3-2. Modes of Operation

Unpowered Mode a: VS > 5V

b VCC: With undervoltage monitoring b

3.3.20.1 Normal Mode

3.3.20.2 Silent Mode

Figure 3-3. Switch to Silent Mode

Normal Mode Silent Mode

Mode select window

Delay time silent mode

LIN switches directly to recessive mode

Node in silent mode

RXD High Low High

Watchdog Watchdog off Start watchdog lead time td

NRES Undervoltage detection active

3.3.20.3 Sleep Mode

Figure 3-5. Switch to Sleep Mode

Mode select window

Delay time sleep mode

LIN switches directly to recessive mode

3.3.20.4 Fail-safe Mode

3.3.20.5 Unpowered Mode

RXD Low or floating Low

Watchdog Watchdog off Start watchdog lead time td

Table 3-1. Table of Modes

3.3.21 Wake-up Scenarios from Silent to Sleep Mode

3.3.21.1 Remote Wake-up via Dominant Bus State

3.3.21.2 Local Wake-up via Pin Wake

3.3.21.3 Local Wake-up via Pin KL_15

3.3.21.4 Wake-up Source Recognition

3.3.23 Voltage Regulator

Figure 3-7. VCC Voltage Regulator: Ramp Up and Undervoltage Detection

TVCC TReset Tres_f t

Figure 3-8. Timing Sequence with RWD_OSC = 51 kΩ

Undervoltage Reset Watchdog Reset