[dsp TIPS&TRICKS] Randy Yates

and Richard Lyons

DC Blocker Algorithms

entiator has infinite attenuation at 0 Hz The location of the pole z = p of this

“DSP Tips and Tricks” introduces
practical design and implementa- and perfectly blocks dc. However, the dif- nonlinear-phase filter presents a tradeoff
tion signal processing algorithms ferentiator also attenuates spectral com- between the filter’s bandwidth and time-
that you may wish to incorporate ponents close to dc as shown by the domain transient response. The magni-
into your designs. We welcome dashed curve in Figure 1. tude responses of H(z) for various values
readers to submit their contribu- The standard method of shoring up of p are shown in Figure 1.
tions to the Associate Editors Rick that drooping frequency response of a Cascaded filters implementing (3)
Lyons ([email protected]) or Britt differentiator is to place a pole just inside work fine in a floating-point number sys-
Rorabaugh ([email protected]). the z-plane zero at z = 1 using a single- tem and have been described in the liter-
pole filter whose transfer function is ature [1]–[2]. Next we discuss a potential
problem in fixed-point implementations
1

T
he removal of a dc bias (a S(z) = , (2) of (3).
1–pz–1
constant-amplitude compo-
nent) from a signal is a com- where p is a real pole and 0 < p < 1. FIXED-POINT IMPLEMENTATION
mon requirement in signal Equation (2) describes a leaky integrator, To understand the effects of fixed-point
processing systems. Thus, a a nonideal integrator that leaks some arithmetic on the dc blocker algorithm in
good dc blocking algorithm is a desirable energy away rather than perfectly inte- (3), let’s consider the differentiator and
tool to have in one’s bag of signal pro- grating dc. The integrator’s response to a leaky integrator sections independently
cessing tricks. In this article we present dc input will not be an ever-increasing using the network in Figure 2(a). Assume
both a nonlinear phase fixed-point dc output, but rather an output that we are using 16-b input and output bina-
blocker (using a noise-shaping trick that increases for a time and then levels off. ry words as indicated in the figure.
eliminates a signal’s dc bias using fixed- The term “leaky” is carried over from The differentiator’s difference equa-
point arithmetic) and a general linear- analog design in which the capacitor tion is
phase dc blocker network that may prove used to implement an integrator was
useful in various DSP applications. imperfect due to the flow of leakage cur- w[n] = x[n] – x[n – 1]. (4)
rent. The cascaded differentiator/integra-
FIXED-POINT DC BLOCKER tor transfer function is given by Note that, at most, the computation in
Simple fixed-point implementations of a (4) will require one more bit than the
dc blocker algorithm have a vexing quan- 1 – z–1 input (17 b total) to avoid possible over-
H(z) = R(z)S(z) = . (3)
tization problem that can create more dc 1 – pz–1 flow, which happens when the input
bias than they block. In this section we
present a “leaky integrator” and a noise-
shaping trick called “fraction-saving” to
eliminate the quantization problem 0
when using fixed-point arithmetic.
Magnitude (dB)

−5
The simplest filter that blocks dc is p = 0 (Pure Differentiator)
the digital differentiator, whose transfer p = 0.7
−10
function is given by p = 0.8
p = 0.9
−15
R(z) = 1 – z–1 . (1)
−20
0 0.1 0.2 0.3 0.4 0.5
Having a z-plane zero at z = 1, the differ-
Freq, xFs

Digital Object Identifier 10.1109/MSP.2007.914713 [FIG1] Cascaded differentiator/integrator frequency response.

IEEE SIGNAL PROCESSING MAGAZINE [132] MARCH 2008 1053-5888/08/$25.00©2008IEEE

 all that is required is to save the fraction
of the quantizer input and feed it back
Differentiator Leaky Integrator
with Truncation y [n] in the next update. Hence the term
x [n] w [n]
+ + “fraction-saving.’’ This process is shown
− p in Figure 2(b). Note that sequence
z −1 z −1 f [n] = u [n]–s [n] is the fractional part
Truncation
16-b Data
Q of u [n] in two’s complement arithmetic
32-b Data
after quantization by truncation. This
(a)
can be illustrated as follows: let u be
w [n ] y [n] represented bit-wise as shown in Figure
+
2(c). Notice that s is u with the 15 least
f [n] significant bits truncated. So f = u–s is
− z −1 p
+ z −1 the fractional part of u.
u [n] Using the fraction-saving scheme in
s [n ] Q +
Figure 2(b) guarantees that the 16-b
Noise Shaper y [n] output will have a dc bias of zero
(b) [4]. (Detailed descriptions of noise-shap-
ing can be found in [5] and [6].) In the
u = u31 u30 u29 ... u16 u15 u14 u13 u12 ... u02 u01 u00 next section we describe a computation-
ally efficient linear-phase dc blocking
network.
s = u31 u30 u29 ... u16 u15

LINEAR-PHASE DC BLOCKER
f= 0 0 0 ... 0 0 u14 u13 u12 ... u02 u01 u00 Another approach to eliminate the dc
(c) bias of a signal is to compute the moving
average of a signal and subtract that
[FIG2] Fixed-point dc blocking filter: (a) simple structure, (b) optimized integrator average value from the signal as shown
structure, and (c) bit-wise representation of u, s, and f.
in Figure 3(a). The delay element in the
figure is a simple delay line, having a
changes sign and the magnitude of the cant dc offset error into the y[n] output, length equal to the averager’s group
difference is greater than 32,768. and the closer the pole is to the unit cir- delay, enabling us to time-synchronize
However, barring that case, we can cle the larger the potential dc error. the averager’s v [n] output with the x[n]
implement the differentiator without Like any quantizer, the quantiza- input in preparation for the subtraction
requiring extra precision in the interme- tion’s dc error can be shaped by placing operation.
diate computation and thus avoid the feedback around the quantizer. In order The most computationally efficient
associated requantization to 16 b at the to implement our noise-shaping trick, form of a D-point moving averager (MA)
output. Also note that the differentiator
is nonrecursive, so quantization effects,
if they do occur, are not circulated back x [n] y [n]
through the differentiator. Delay +
−
The leaky integrator has a difference
v [n]
equation of Moving Average

(a)
y[n] = p · y[n – 1] + w[n]. (5)
MA
Because the goal is to implement (5) on x [n] − y [n]
a fixed-point (integer) processor, its + + MA +
−
terms must each be represented as an z−D +1 z −1 1/D
integer and the operations must be per-
formed using integer arithmetic. If we
z −1
want the x[n] input and y[n] output to
be scaled identically, then we must quan-
(b)
tize (truncate) the 32-b product result in
(5) to 16 b. It is precisely this quantiza- [FIG3] Linear-phase dc blocker: (a) moving average subtraction method and (b) dual-MA
tion that introduces a potentially signifi- implementation.

IEEE SIGNAL PROCESSING MAGAZINE [133] MARCH 2008

[dsp TIPS&TRICKS] continued

is the network whose transfer function is finite-impulse response (FIR) filter samples, yields an improved passband
defined by designs using least-squares error mini- peak-peak ripple of only 0.02 dB as well
mization, or the Parks-McClellan as a reduced-width transition region
1 1–z–D
H MA (z) = · . (6) method, require more than 100 taps to relative to the dual-MA implementa-
D 1–z–1
approximate our D = 32 dc blocking fil- tion. The dc blocker in Figure 4(b) con-
The second ratio in (6) is merely a recur- ter’s performance. tains four 1/ D scaling operations
sive running sum comprising a D-length On a practical note, the MAs in which, of course, can be combined and
comb filter followed by a digital integra- Figure 3(b) contain integrators that can implemented as a single binary right
tor. If D is an integer power of two, the experience data overflow. (An integra- shift by 4log2 (D) bits.
1/D scaling in (6) can be performed using tor’s gain is infinite at dc!) Using two’s
a binary right shift by log2 (D) bits. complement fixed-point arithmetic CONCLUSIONS
However, if D is an integer power of avoids integrator overflow errors if we We presented a nonlinear-phase, but
two, then the MA’s group delay is not an ensure that the number of integrator computationally efficient, dc blocking fil-
integer number of samples, making the (accumulator) bits are at least ter that achieves ideal operation when
synchronization of the delayed x[n] and output data quantization is used. In addi-
v[n] difficult. To solve that problem we tion, we described an alternate dc block-
accumulator bits
use two cascaded D-point MAs as shown ing filter that, at the expense of larger
in Figure 3(b). Because the dual-MA has = number of bits in q [n] data memory, exhibits a linear-phase fre-
an integer group delay of D–1 samples, + log2 (D ), (7) quency response.
our trick is to tap off the first averager’s
delay line, eliminating the bottom-path where q [n] is the input sequence to AUTHORS
“Delay” element in Figure 3(a). an accumulator and k means as fol- Randy Yates ([email protected]) is a con-
The magnitude response of our dual- lows: if k is not an integer, round it up to sultant in audio, communications, and
MA dc blocker, for D = 32, is shown in the next larger integer. signal processing systems at Digital
Figure 4(a). In the figure we show the For a narrower transition region Signal Labs, Inc. He is currently pursu-
details of this dc blocker’s passband with width, in the vicinity of 0 Hz, than that ing an M.S. degree in electrical engineer-
its peak-peak ripple of 0.42 dB. The fre- shown in Figure 4(a), we can set D to a ing at North Carolina State University,
quency axis value of 0.5 corresponds to a larger integer power of two. However, Raleigh, North Carolina.
cyclic frequency of half the input signal’s this will not reduce the dc blocker’s Richard Lyons ([email protected]) is
Fs sample rate. This dc blocker has the passband ripple. a consulting systems engineer and lec-
desired infinite attenuation at 0 Hz. At the expense of three additional turer with Besser Associates in Mountain
What we’ve created then is a linear- delay lines, and four new addition oper- View, California. He is the author of
phase, multiplierless, dc blocking net- ations per output sample, we can Understanding Digital Signal Processing
work having a narrow transition region implement the dc blocker shown in 2/E (Prentice-Hall, 2004), and editor of,
near 0 Hz. It’s worth noting that stan- Figure 4(b). That quad-MA implemen- and contributor to, Streamlining Digital
dard tapped delay-line, linear-phase tation, having a group delay of 2 D–2 Signal Processing, A Tricks of the Trade
Guidebook (IEEE Press/Wiley, 2007).

0
REFERENCES
–0.42 dB [1] C. Dick and F. Harris, “FPGA signal processing
dB

−2 using sigma-delta modulation,” IEEE Signal Proc.

D = 32 Mag., vol. 17, no. 1, pp. 200–35, Jan. 2000.
−4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 [2] K. Shenoi, Digital Signal Processing in
Communications Systems. New York: Chapman &
Freq, xFs Hall, 1994, p. 275.

(a) [3] A. Bateman, “Implementing a digital ac coupling

filter,” GlobalDSP Mag., Feb. 2003 [Online].
Available: http://www.globaldsp.com/index.asp
x [n] − y [n]
+ + MA MA MA + [4] R. Bristow-Johnson, “DSP trick: Fixed-point dc
– blocking filter with noise-shaping” [Online].
z−D+1 z−1 1 D Available: http://www.dspguru.com/comp.dsp/
tricks/alg/dc block.htm

[5] P. Aziz, H. Sorensen, and J. Van Der Spiegel, “An

z−1 z −D+1 overview of sigma-delta converters,” IEEE Signal
Proc. Mag., vol. 13, no. 1, pp. 61–84, Jan. 1996.
(b)
[6] G. Bourdopoulos, A. Pnevmatikakis, V.
Anastassopoulos, and T.L. Deliyannis, Delta-Sigma
[FIG4] DC blocker: (a) D = 32 dual-MA passband performance and (b) quad-MA Modulators: Modeling, Design and Applications.
implementation. London: Imperial College Press, 2003, pp. 36–40. [SP]

IEEE SIGNAL PROCESSING MAGAZINE [134] MARCH 2008