Faculty of Engineering and Technology

Electrical Engineering Department

ELE 215 – Logic Design

and Digital Circuits
Lecture 4 - Gate-Level Minimization

Dr. Nermin Salem

[email protected]
Course Outline
• Introduction
• Numbering System
• Logic Gates and Gate-Level Minimization
• Boolean Algebra ▪ Introduction
• K-maps ▪ The Karnaugh Map Method
(K-Map)
• Combinational Logic ▪ Three-Variable Map
▪ Four-Variable Map
• Synchronous Sequential Logic ▪ Product of Sums
Simplification
• Registers and Counters ▪ Don’t-Care Conditions
▪ NAND and NOR
• Memories and Programmable Logic Implementation
▪ Parity Generator and
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Checker
Introduction
• A K-map is a diagram made up of squares, with each square
representing one minterm of the function that is to be
minimized.
• The simplified expressions produced by the map are always in
one of the two standard forms:
• Sum of Products (Minterms)
• Product of Sums (Maxterms)
• It will be assumed that the simplest algebraic expression is an
algebraic expression with a minimum number of terms and
with the smallest possible number of literals in each term.
• This expression produces a circuit diagram with a minimum
number of gates and the minimum number of inputs to each
gate.
https://en.wikipedia.org/wiki/Maurice_Karnaugh

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 Two-Variable K-Map
• There are four minterms for two variables.
• The map consists of four squares, one for each minterm.
• Example: 2-variable K-Map
Represent 2-input AND and 2-input OR using K-Map.

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 Three-Variable K-Map
• There are eight minterms for three binary variables; therefore, the map consists of
eight squares.
• The minterms are arranged, not in a binary sequence, but in a sequence similar to
the Gray code → single variable change.
• Each cell of the map corresponds to a unique minterm.
• The Question: How the simplification occurs? Taking Minterms Groups
➢ One square represents one minterm, giving a term with three literals
➢ Two adjacent squares represent a term with two literals
➢ Four adjacent squares represent a term with one literals
➢ Eight adjacent squares produce a function that is always equal to 1
Note: each group of minterms must have at least one new minterm (was not taken before in any
group)

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 Example 1

Solution:

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 Example 2

Solution:

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 Example 3

Solution:

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 Example 4

Solution:

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Four-Variable K-Map

• The map for Boolean functions of four

binary variables (w, x, y, z) are listed the
16 minterms and the squares assigned to
each.
• The rows and columns are numbered in
a Gray code sequence, with only one
digit changing value between two
adjacent rows or columns.
• The minterm corresponding to each
square can be obtained from the
concatenation of the row number with
the column number.

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 Four-Variable K-Map
• The map minimization of four-variable works as follows:
➢One square represents one minterm, giving a term with four literals
➢Two adjacent squares represent a term with three literals
➢Four adjacent squares represent a term with two literals
➢Eight adjacent squares represent a term with one literal
➢Sixteen adjacent squares produce a function that is always equal to 1

https://en.wikipedia.org/wiki/Karnaugh_map

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 Example 5

Solution:

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 Example 6

Solution:

𝐹 = 𝐵′ 𝐷′ + 𝐵′ 𝐶 ′ + 𝐴′ 𝐶𝐷′

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 Prime Implicants

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 Example 7

Solution:

There are four possible ways that the

function can be expressed with four
product terms of two literals each:

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 Example 8

Solution:
1.
2.
3. Apply DeMorgan s’ thereom:

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 Example 8

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 Don’t-care Conditions
• There may be a combination of input values which
➢will never occur
➢if they do occur, the output is of no concern
• The function value for such combinations is called a don't care.
• They are usually denoted with (x). Each x may be arbitrarily assigned
the value 0 (in case of PoS) or 1 (in case of SoP) in an
implementation.
• Don’t cares can be used to further simplify a function.

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 Example 10

Solution:

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 Nand and Nor Implementation
1. NAND Circuits:

Example 11: Implement the following Boolean expression using ONLY

NAND gates.
𝐹 = 𝐴𝐵 + 𝐶𝐷

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 Solution:

Example 12

Implement the following

Boolean function with
NAND gates:
𝐹 = ∑(1, 2, 3, 4, 5, 7)

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 Solution:

Example 13

Consider the multilevel Boolean

function, Implement it using
NAND gates:

𝐹 = (𝐴𝐵′ + 𝐴′𝐵)(𝐶 + 𝐷′)

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 Nand and Nor Implementation
2. NOR Circuits:

Example 14: shows the NOR implementation of a function expressed as a product

of sums:
F = (A + B)(C + D)E
Solution:

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 Parity Generation (At Transmitter)
Design Problem Statement: Consider a three-bit message to be
transmitted together with an even-parity bit. The three bits are: x, y, and
z, constitute the message and are the inputs to the circuit. The parity bit
P is the output.
Requirement: For even parity, the bit P must be generated to make the
total number of 1’s (including P ) even.

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 Design Steps
1. From the specifications of the circuit, determine the required number
of inputs and outputs and assign a symbol to each
2. Derive the truth table that defines the required relationship between
inputs and outputs
3. Obtain the simplified Boolean functions for each output as a
function of the input variables
4. Draw the logic diagram and verify the correctness of the design
(manually or by simulation)

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 Parity Generator

𝑃 = ∑ 1,2,4,7 = x ⊕ 𝑦 ⊕ z Logic diagram of a parity generator

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 Parity Checker (At Receiver)

Logic diagram of a parity checker

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 Code Conversion Example
Design Statement: Convert BCD and excess-3
Solution:

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Code Conversion Example (Cont.)

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 Logic Diagram of the Conversion Problem

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 References
‒ M. Mano and M. Ciletti, Digital Design, with an introduction to the
Verilog HDL. 5th Ed. Pearson, 2013.
‒ John F. Wakerly, Digital Design: Principles and Practices. 4th Ed.
Pearson, 2005.
‒ R. Katz and G. Boriello, Contemporary Logic Design. 2nd Ed.
Pearson, 2005.

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 Thank You

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