Bachelor’s Thesis Project I

End-evaluation Report

Neuromorphic Computing Hardware for Machine Learning using Memristors

Thesis submitted in partial fulfilment of requirements for the degree of

Bachelor of Technology
in
Electrical Engineering

by
Shubhendu Pandey
20EE38022

Under the Supervision of

Prof Shyamal Kumar Das Mandal

Advanced Technology Developement Center Indian Institute of Technology,

Kharagpur
 DECLARATION
I certify that

1. The work contained in this report has been done by me under the guidance of my supervisor.

2. The work has not been submitted to any other Institute for any degree or diploma.

3. I have conformed to the norms and guidelines given in the Ethical Code of Conduct of the
Institute.

4. Whenever I have used materials (data, theoretical analysis, figures, and text) from other
sources, I have given due credit to them by citing them in the text of the thesis and giving
their details in the references. Further, I have taken permission from the copyright owners of
the sources, whenever necessary.

Date: November 27, 2023 Name: Shubhendu Pandey

Place: Kharagpur Roll Number: 20EE38022

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 Advanced Technology Development Center
INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR
Kharagpur - 721302, India

CERTIFICATE
This is to certify that the project report entitled “Neuromorphic Computing Hardware for
Machine Learning using Memristors” submitted by Shubhendu Pandey (Roll No. 20EE38022) to
the Indian Institute of Technology Kharagpur towards partial fulfillment of requirements for the
award of the degree of Bachelor of Technology in Electrical Engineering is a record of bonafide work
carried out by him under my supervision and guidance during Autumn Semester, 2023-24.

Supervisor(s) Signature Student’s Signature

Date: November , 2023 Date: November 27, 2023

Advanced Technology Development Roll No.: 20EE38022

Center
Place: Kharagpur
Indian Institute of Technology Kharagpur
Kharagpur - 721302, India

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 Acknowledgements

I would like to thank my Thesis supervisor Prof. Shyamal Kumar Das Mandal and co-supervisor
Prof. Fabien Alibart for directing, guiding, and supporting me throughout the project.

I am also thankful to Prof. Debdoot Sheet, coordinator of my Bachelor Thesis Project, for pro-
viding necessary facilities during the project work.

I am thankful to my Faculty Advisor Prof. Debashis Mandal, Department of Electrical Engi-

neering, Indian Institute of Technology Kharagpur, for always being very accommodating of all of
our requests and feedback.

I am grateful to my friends, who were a constant support behind me in every situation. And
last but not least, my parents for their invaluable trust and support in all my choices.

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 Abstract
Memristors are a recent innovation in semiconductor technology, distinguished by their unique
ability to alter their resistive state through the application of various voltage pulses. Initially con-
ceptualized by Chua in the 1970s, practical development didn’t occur until 2008 when HP brought
this concept to fruition. Since then, the memristor has revolutionized both the semiconductor and
artificial intelligence industries, owing to its diverse range of applications. One of the most sig-
nificant advantages of this device is its non-volatile nature, making it exceptionally well-suited for
in-memory stateful logic calculations. Additionally, it has played a crucial role in reducing time
and energy consumption in machine learning applications by a staggering factor of 100, primarily
due to its ability to facilitate parallel processing.

Given the wide-ranging applications of memristors and the ongoing robust research in this do-
main, comprehensive testing of the device is essential. However, until now, there has been a notable
absence of a System on Chip (SoC) capable of harnessing the full potential of parallelism by concur-
rently delivering parallel voltage pulses and measuring current responses. To address this limitation,
we have developed the LOTUS board.

In this research endeavor, our primary objectives include enhancing the user-friendliness and
precision of the LOTUS board. To achieve this, we plan to create a graphical user interface for
the board, optimizing its measurement capabilities. Moreover, we aim to showcase the board’s
capabilities by conducting a machine-learning experiment that leverages its unique features.

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Contents

1 Introduction 1
1.1 The world of Memristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Application of memristors and memristive crossbars . . . . . . . . . . . . . . . . . . 2

2 Overview 3
2.1 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Our Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Research Plan and Implementation 5

3.1 Simplified LOTUS Access: GUI Integration . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Improving the accuracy of measurements by the board . . . . . . . . . . . . . . . . 6
3.3 Accelerating Inference Tests in Machine Learning using crossbar . . . . . . . . . . . 6

4 Results 8
4.1 GUI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Crossbar Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.1 Fixing calibration errors incurred due to temperature differences . . . . . . . 9
4.2.2 Fixing Offset Current Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.3 Fixing errors due to parasitic components . . . . . . . . . . . . . . . . . . . 10

5 Conclusion and Future Work 11

5.1 Summary of work done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 References 12

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Chapter 1

Introduction

1.1 The world of Memristors

Memristors, short for “memory resistors” are a relatively recent innovation in the field of electronic
components. They were first theorized by Leon Chua, a professor at the University of California,
Berkeley, in 1971. Chua’s theoretical concept of a memristor completed a quartet of fundamental
circuit elements alongside resistors, capacitors, and inductors. This was a significant development
in the world of electronics, as it introduced a missing fundamental component that could store and
process information.

However, it wasn’t until nearly four decades later that researchers at Hewlett-Packard Labs, led
by R. Stanley Williams, announced the successful creation of a practical memristor device in 2008.
This milestone marked a turning point in the history of electronics, as memristors had the potential
to revolutionize computing, memory storage, and signal processing.

In the realm of advanced electronic devices and computing, memristors have emerged as an
exciting and groundbreaking technology. What makes memristors particularly intriguing is their
ability to exhibit a distinctive electrical property known as “memristance” Memristance refers to
the property of a device to alter its resistance in response to the magnitude and direction of the
applied voltage. This property enables memristors to “remember” the charge that has previously
flowed through them, effectively acting as non-volatile memory elements. In simpler terms, unlike a
simple resistor, a memristor can attain multiple resistive values depending on the applied voltage.
The I-V curve in the figure 1.1 (b) showcases a memristive device with six different stable resistance
states.

(a) Leon Chua’s Prediction (b) I-V curve of a memristor

Figure 1.1: Memristor - The Fourth Fundamental Circuit Element

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1.2 Application of memristors and memristive crossbars
The memory capabilities of memristors extend beyond simple storage. They can also perform com-
putational tasks within the memory itself, offering a novel approach to computing architecture.
This in-memory computation capability holds the potential to overcome one of the most significant
challenges in traditional computing systems—the Von Neumann bottleneck. The Von Neumann
bottleneck refers to the limited bandwidth and efficiency caused by the separation of memory and
processing units.

By integrating memory and computation, memristors enable parallelism, reducing the data
movement required in conventional architectures. In-memory computation allows data to be pro-
cessed within the memory itself, eliminating the need for frequent data transfers to and from the
central processing unit (CPU). This breakthrough has the potential to revolutionize computing,
particularly in domains that heavily rely on memory-intensive tasks such as machine learning (ML).

One key application of resistive memory in ML is the implementation of neural networks. Neural
networks serve as the backbone of modern ML algorithms, and their computational demands are
constantly increasing. By leveraging the parallelism enabled by resistive memory, neural network
computations can be executed efficiently and in close proximity to the data, minimizing latency and
energy consumption. This approach proves especially valuable for tasks such as pattern recognition,
image processing, and natural language understanding.

All of this is achieved by working with memristive crossbars. The fig () shows an ideal memristor
crossbar. In a memristive crossbar, memristor devices are arranged in a two-dimensional grid,
forming rows and columns of intersecting wires. This grid-like structure allows for a multitude of
connections and interactions between the memristors.
The key characteristics and applications of memristive crossbars include:

1. Non-Volatile Memory: Memristive crossbars can store data in a non-volatile manner. This
means that the data remains intact even when the power is turned off, making them suitable
for applications where persistent data storage is essential.

2. Analog Computation: Crossbars are capable of performing analog computations due to

the continuous range of resistance values that memristors can exhibit. This makes them well-
suited for tasks like signal processing and neural network operations that involve continuous
values.

3. Parallel Processing: Memristive crossbars enable parallel data processing. Multiple mem-
ristors can be accessed simultaneously, facilitating the efficient execution of operations in
applications like neural networks.

Figure 1.2: Memristive Crossbar

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Chapter 2

Overview

2.1 Literature Review

The field of information and communication technologies is currently undergoing a profound trans-
formation, characterized by the emergence of innovative computing solutions that go beyond conven-
tional approaches based on the von Neumann CMOS architecture [1]. Unlike traditional CPU-based
innovations, which focus primarily on algorithmic advancements, this transformation involves a syn-
ergy between hardware and software innovations, necessitating co-design methodologies between the
two [2]. This novel methodology places application-specific hardware at the forefront of research [3]
on the development of new circuits and systems.

In order to develop and iterate on these hardware designs, a profound understanding of their
behavior and underlying physical mechanism is required. For emerging types of memory for which
accurate models do not yet exist, an understanding of the material parameters of the fabricated
devices requires in-depth electrical characterizations, where hardware-in-the-loop simulations [4] are
preferred over standard simulations using complex models. Since integrated circuits and nanodevices
are often integrated with CMOS technologies, there is a growing demand for new hardware-specific
characterization instruments that are capable of handling both analog and digital signals.

One of the most promising approaches to overcoming the memory wall arising from von Neu-
mann’s architecture is the in-memory computing (IMC) paradigm [5], which is particularly suited to
artificial intelligence applications in the form of neuromorphic circuits [6] and memristive artificial
neural networks [7]. These IMC architectures leverage the analog behavior of emerging resistive
memory devices (also called memristors [8]), which can be implemented in multiple ways [9] and
in different topologies [10], such as passive and one-transistor-one-resistor (1T1R) crossbar arrays
[11]. In the absence of integrated CMOS-based control electronics, driving a memristive crossbar
requires external custom instrumentation electronics that can perform parallel voltage-current mea-
surements simultaneously, with both digital and analog signals. These instrumentation systems are
used to provide and measure electrical signals to and from the crossbar arrays, with the help of fast
programming pulses [12].

As crossbar arrays tend to have a high number of inputs and outputs, the strategy used until
recently was to multiplex a small number of these pulsed signals to the connections of the devices,
using commercially available instruments [13], [14] or custom ones [15]–[22] that integrate switching
matrices. However, these systems lack the capability to generate expansive parallel voltage vec-
tors and require the interconnection of multiple instruments in parallel to read parallel vectors of
currents. These drawbacks nullify one of the key advantages of IMC architectures, which is their

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ability to perform parallel calculations in a single operation [23], as required for vector-matrix mul-
tiplications (VMM) with artificial neural network applications [24]

Recently, a promising FPGA-based approach [15] has been proposed to address this issue of
parallelism, with the ability to perform both writing and reading operations in parallel. Instead of
using a switch matrix, the developers of this approach implemented one measuring channel for each
input and output connection. However, as a large quantity of electronic components was necessary
to achieve this, each channel design had to be optimized in terms of power consumption and circuit
simplicity. These choices led to limited reading speeds of 500 s and constrained signal flexibility,
as timings were shared between each group of eight channels. To achieve full parallelism without
losing accuracy and speed, new system architectures need to be considered. Such a system would
represent progress towards highly parallel innovative circuits, such as sensor matrices and quantum
dot interfacing, while opening novel avenues for the exploration of neuromorphic circuits.

2.2 Our Problem Statement

Taking into consideration the recent work going on in this field and the problems faced, we decided
to work on the LOTUS system, an FPGA-controlled high-speed, parallel current voltage measuring
platform optimized for the characterization of in-memory computing architecture and memristive
neuromorphic circuits. It incorporates 32 fully asynchronous analog channels, which enable the
generation of custom waveforms in the range ±5 V with timing resolutions of 6.25 ns. It also
includes 32 high-speed digital channels, which facilitate the interfacing of devices with up to 64 pins
with both analog and digital signals, within a compact, portable size. Test results demonstrate the
ability of LOTUS to generate high-speed voltage pulses as short as 25 ns, with voltage accuracy of
up to 0.05%. Moreover, the system achieves accurate current measurements of 0.5 % with reading
cycles of as little as 325 ns. The FPGA can gather up to 17.92 Gbps of current measurements,
while the system’s measuring channels allow for up to 1.53 GFLOPS on 16×16 crossbar arrays of
resistors. These characteristics arise from its innovative high-speed current sensing circuit design,
which allows for both accurate and high-speed measurements. The capabilities of the proposed
system in terms of parallelism, speed, and precision make it suitable for a multitude of applications
such as machine learning and memristive crossbar characterization.

Figure 2.1: Top-down photography of the assembled LOTUS system, where the components are (1)
the Zynq SOM, (2) a four-channel APMU group (eight in total), (3) the DUT interface, (4) a
variable voltage supply, (5) an eight-GPIO bank, (6) the external sensor connector, and (7) the
board-to-board (B2B) interface with (8) its input and (9) its output

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Chapter 3

Research Plan and Implementation

In this section, we will delve into the imminent tasks essential for the project’s progress. We’ll
provide a comprehensive breakdown of our implementation strategy. The project’s immediate focus
revolves around three key tasks:

3.1 Simplified LOTUS Access: GUI Integration

The LOTUS board is a versatile and powerful tool for memristor research. It can send and measure
16 values of pulses, both current and voltage simultaneously. This allows for parallel computations
on the memristor crossbar, which can significantly accelerate research in areas such as memristor
characterization, in-memory computation, and neuromorphic algorithms. While the LOTUS board
is a powerful tool, it can be complex to use. Researchers need to have a deep understanding of the
underlying electronics and software in order to get the most out of it. This can be a barrier to entry
for many researchers, and it can also lead to time-consuming troubleshooting.

We propose to develop a new graphical user interface (GUI) for the LOTUS board. This GUI
will be designed to be simple and easy to use, even for researchers with no prior experience with
electronics or programming. The GUI will allow researchers to perform the following tasks:

1. Waveform Creation: Create voltage waveforms as a sequence of desired voltage pulses

2. Parameter Alteration: Change the parameters of voltage pulses such as type, amplitude,
duration and frequency
3. Current Collection: Get the result of current pulses from the columns of the crossbar

Benefits of the new GUI: The new GUI will offer a number of benefits to researchers like
reduced learning curve and increased productivity. Since the researchers will be able to start
using the LOTUS board immediately, without having to learn complex electronics or programming
concepts of the internal architecture of the board.

Implementation: The GUI will be implemented using the QtCreator UI designer and the
PyQt library. The backend will be designed by integrating the GUI with the Python functions
available in the PyQt library. We believe that the new GUI will be a valuable tool for memristor
researchers, and we are excited to develop it.

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3.2 Improving the accuracy of measurements by the board
The device’s performance is currently afflicted by significant accuracy limitations attributable to a
confluence of factors. To test the working of the device under extreme conditions, we engineered
a resistive matrix characterized by a high resistance state to low resistance state ratio of 10M to
100. The large High Resistance State to Low Resistance State ratio makes the effect of
leakage currents quite significant and the task of minimizing the errors quite difficult. However, if
the device is able to perform well in these conditions, it will demonstrate its accuracy and usefulness
in a variety of real-world applications.
In other words, if the device can perform well under extreme conditions where leakage currents
are high, it is likely to be very accurate and useful in most real-world applications where leakage
currents are lower, usefulness of our device in various conditions.

Figure 3.1: Heatmap of % error in 16 by 16 resistive matrix

The Python code for operating with the board and finding the heatmap is here
The heatmap above shows that the % error in the measurement is quite high. The probable cuase
of the inaccuaries might be temperature variations, inadequate calibration procedures, neglectance
of parasitic resistances, and leakage currents. The aim in coming months is to address these issues
and enhance the device’s overall functionality and reliability.

3.3 Accelerating Inference Tests in Machine Learning using

crossbar
Performing inference operations in neural networks often involves a significant number of Multiply-
Accumulate (MAC) operations, which are computational tasks that require multiplying and sum-
ming values in various layers of the network. This process can be computationally intensive, time-
consuming, and energy-demanding, particularly in large-scale neural networks. However, by lever-
aging memristive crossbars, these challenges can be mitigated, and the number of MAC operations,
as well as the time and energy needed for inference, can be significantly reduced. Memristive cross-
bars support analog computing and the resistance can be varied by giving different voltage pulses
as input. Thus they can be used to perform vector and matrix multiplication in one clock cycle
thereby being 100 times more energy efficient than traditional computing method.

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 We intend to perform an inference experiment in the later stages of the project to demonstrate
the same. The process to be followed is as follows:

1. Train the model conventionally and find the weights to reduce the cost function

2. Map the weights to resistance values in the crossbar

3. Input vector X corresponds to the voltage input from rows

4. Output vector Y corresponds to the current output from columns

The following image demonstrates the idea more clearly

Figure 3.2: Model for performing inference experiment using memristor crossbar

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Chapter 4

Results
4.1 GUI Results
In addition to reviewing the literature and identifying and deciding on the work to be done, we
have created a basic model of a graphical user interface (GUI) to help other researchers use the
LOTUS board. The GUI is still under development, and we are adding new features to make it more
user-friendly. We will continue to work on the GUI until the LOTUS board is free of calibration
and leakage errors, so that it is reliable enough for researchers to use for their work.

The figure below shows a basic model of the GUI:

(a) 1st Window where you choose the type

of voltage pulse (b) Set the parameters of the pulse

(c) Waveform from pulses on

the right side of the window (d) Results obtained from the board

Figure 4.1: GUI for the LOTUS board

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4.2 Crossbar Results
A script was written for sending the pulses from the row APMUs and sensing the current from the
column APMUs. Then the resistance was calculated and the error from the expected resistance
was found. The heatmap shown below shows that the errors are huge and work needs to be done
to reduce them. This is the immediate goal for this project.

To understand better, let’s suppose we have just 2 nodes. I apply V1 voltage at the first node
and V2 voltage at the second node. I have connected the nodes together through a resistance.
The error in the measurement of resistance can arise from errors in the measurement of voltage or
current. The first two errors correspond to deviations in the desired voltage, and the third error is
due to an error in the measurement of current.

The causes of the errors are narrowed down to:

1. Calibration errors incurred due to temperature differences
2. Offset currents not taken into account
3. Parasitic resistance’s affect

4.2.1 Fixing calibration errors incurred due to temperature differences

Because we are working with semiconducting devices, temperature plays a crucial role in altering
the parameters of transistors within the device. There were significant temperature variations be-
tween developing and testing the device. Consequently, the initial approach was to recalibrate the
device to match the current temperature of the location, aiming to minimize calibration errors. The
error heatmap before and after recalibrating the device is shown in the following figure:

(a) Before re-calibrating the device (b) After re-calibrating the device

Figure 4.2: Error in measurement of Resistances

We see that recalibrating reduces the error for lower resistance values considerably but not for
higher resistance values. Thus we shift our focus to errors that might be induced due to wrong
current sensing.

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4.2.2 Fixing Offset Current Errors
Setting all nodes to 0 V should theoretically result in zero current being sensed by any of the
APMUs. However, during the experiment, it was observed that some current was still being sensed
by all nodes, as illustrated in the figure 4.3(a). To address this issue, we account for offset currents.
We calculate these offset currents by applying 0 voltage to all nodes, as demonstrated earlier. When
applying the desired voltage, we adjust our current readings by subtracting these calculated values.
This correction significantly enhances our resistance readings, as depicted in the figure 4.3(b).

(a) Offset Currents on applying 0 voltage (b) After re-calibrating the device

Figure 4.3: Inconsistency due to offset currents

As can be seen in the figure the mean error has gone down to 20% but the errors in the lowest
resistance state and the high resistance state are still high.

4.2.3 Fixing errors due to parasitic components

The challenge arises from the high HRS/LRS ratio, causing even slight microamp currents to sig-
nificantly affect readings for higher resistance states that should ideally exhibit low currents. Ad-
ditionally, an oversight of parasitic resistance in APMU transistors introduces another source of
error. To address this, we measure the voltage at the APMU’s end using an oscilloscope, compare
it with the expected voltage, and determine the parasitic resistance by identifying the voltage drop.
Subsequently, we recalibrate applied voltages with the equation vapmu * (rload + 2 * rline) / rload,
where rline is the parasitic resistance, resulting in the depicted heatmaps shown in Figure 4.4

Figure 4.4: Final Heatmap of errors

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Chapter 5

Conclusion and Future Work

5.1 Summary of work done

In this undertaking, we delve into the realm of memristors, focusing on developing a system capable
of concurrently generating high-speed parallel arbitrary voltage pulses and capturing current vectors
within IMC architectures and neuromorphic circuits. Recognizing the widespread applications of
the supporting system in neuromorphic computing, we construct an intuitive graphical user interface
(GUI). This GUI serves to empower researchers lacking in-depth knowledge of the board’s internal
workings to seamlessly engage with the system.
Furthermore, we enhance the board’s measurement accuracy by identifying and rectifying errors
associated with offset currents, parasitic components, and calibration. Through these refinements,
our device surpasses the performance of existing state-of-the-art devices.

5.2 Future work

The forthcoming efforts aim to leverage the device for executing machine learning (ML) operations
with minimized energy consumption and time requirements. Notably, the device allows for per-
forming Multiply-Accumulate (MAC) operations in a singular time step, a notable improvement
over the multiple steps typically required in traditional digital computing.
The existing graphical user interface (GUI) proves effective for conducting characterizations, pro-
viding a user-friendly platform. However, there is a need to further enhance the accuracy of current
sensing. Future endeavours will be directed towards refining this aspect of the system to ensure
optimal performance.

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Chapter 6

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