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CS 207 Computer Organization and Architecture

Memory Organization

Memory Hierarchy
 The memory unit is an essential component in any
digital computer since it is needed for storing
programs and data
 Not all accumulated information is needed by the
CPU at the same time.
 Therefore, it is more economical to use low-cost
storage devices to serve as a backup for storing the
information that is not currently used by CPU, as
shown in the figure. (next slide)

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Memory Hierarchy

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Memory Organization
 Main Memory : Memory unit that communicates directly with the
CPU (RAM)
 Auxiliary Memory : device that provide backup storage (Disk Drives)
 Cache Memory : special very-high-speed memory to increase the
processing speed (Cache Memory)
 I/O Processor: It loads and stores data into memory along with the
execution of I/O instructions. It acts as an interface between system
and devices. It involves a sequence of events to executing I/O
operations and then store the results into the memory.
A uxiliary m em o ry
M ag netic
tap es
M ain
I/O p ro cesso r
m em o ry
M ag netic
d isks

C ache
C PU
m em o ry

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Memory Hierarchy
 CPU logic is usually faster than main memory access time,
with the result that processing speed is limited primarily by the
speed of main memory.
 The cache is used for storing segments of programs currently
being executed in the CPU and temporary data frequently
needed in the present calculations.
 The typical access time ratio between cache and main memory
is about 1 to 7.
 Auxiliary memory access time is usually 1000 times that of
main memory.

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Main Memory
 Most of the main memory in a general purpose
computer is made up of RAM integrated circuits
chips, but a portion of the memory may be
constructed with ROM chips

 RAM– Random Access memory

 Integrated RAM are available in two possible operating
modes, Static and Dynamic
 ROM– Read Only memory

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Semiconductor Memories

• Nonvolatile • Volatile memory

memory – SRAM
– DRAM
– ROM
• Asynchronous
– PROM – DRAM
– FPM DRAM
– EPROM
• Synchronous
– EEPROM – SDRAM
– DDR SDRAM
– Flash memory – RDRAM

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Random-Access Memory (RAM)

• Static RAM (SRAM)
– Each cell stores bit with a six-transistor circuit.
– Retains value indefinitely, as long as it is kept powered.
– Relatively insensitive to disturbances such as electrical noise.
– Faster and more expensive than DRAM.
– Used in Cache memory and CPU register

• Dynamic RAM (DRAM)

– Each cell stores bit with a capacitor (usually MOS) and transistor/switch.
– Value (charge) must be refreshed every 10-100 ms.
– Sensitive to disturbances.
– Slower and cheaper than SRAM.
– Memory slice density is high.
– Used in most computer as main memory

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b
SRAM cell b'
Vsupply

word line

bit line bit line

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DRAM cell

word line

bit line

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SRAM vs DRAM Summary

Tran. Access
per bit time Persist? Sensitive? Cost Applications

SRAM 6 1X Yes No 100x cache memories

DRAM 1 10X No Yes 1X Main memories,

frame buffers

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Typical RAM Configuration

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ROM
• ROM : Read Only Memory
– Programmed when manufacturing is in process.
• PROM : Programmable Read Only Memory
– Programmable by user only once
– Flexible and convenient compared to ROM
– Programmed by burning the fuse using high
current pulse

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ROM
• ROM is used for storing programs/data that are permanently
resident in the computer and for tables of constants that do not
change, once the production of the computer is completed
• The ROM portion of main memory is needed for storing an
initial program called bootstrap loader, witch is to start the
computer software operating when power is turned off

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ROM

Typical RAM Configuration

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Memory Address Map

• Memory Address Map is a pictorial representation of assigned
address space for each chip in the system

• To demonstrate an example, assume that a computer system

needs 512 bytes of RAM and 512 bytes of ROM

• The RAM have 128 byte and need seven address lines, where
the ROM have 512 bytes and need 9 address lines. (PTO)

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Memory Address Map ….

• The hexadecimal address assigns a range of hexadecimal equivalent

address for each chip
• Line 8 and 9 represent four distinct binary combination to specify which
RAM we chose
• When line 10 is 0, CPU selects a RAM. And when it’s 1, it selects the
ROM

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Problems and Discussion

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Associative Memory
 This memory unit allows the accessing the stored data item by the content of
the data rather than by an address, also known as content addressable
memory (CAM).
 This concept reduces the time required to find an item stored in memory.
 When a word is written in an associative memory, no address is given.
 The memory is capable of finding an empty unused location to store the
word.
 When a word is to be read from an associative memory, the content of the
word, or part of the word, is specified. The memory locates all words which
match the specified content and marks them for reading.

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Associative Memory
 An associative memory is more
expensive than a random access
memory because each cell must have
storage capability as well as logic
circuits for matching its content with
an external argument.
 It is suitable only where the search
time is very important and must be
very short.

Hardware Organization 21

Associative Memory
 An associative memory is more
expensive than a random access memory
because each cell must have storage
capability as well as logic circuits for
matching its content with an external
argument.
 It is suitable only where the search time
is very important and must be very short.
 Argument register (A): It contains the
word to be searched. It has n bits (one for
each bit of the word).
 Key Register (K): This specifies which
part of the argument word needs to be
compared with words in memory. If all
bits in register are 1, The entire word
should be compared. Otherwise, only the
bits having k-bit set to 1 will be
compared.
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Associative Memory
Associative memory array: It contains the words which are to be compared with the
argument word.
Match Register (M): It has m bits, one bit corresponding to each word in the
memory array. After the matching process, the bits corresponding to matching
words in match register are set to 1.

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Associative Memory

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Match logic
 Let us include Key register. If Kj = 0 then there is no need to compare Aj and Fij.
 Only when Kj =1, comparison is needed.
 This achieved by ORing each term with Kj.

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Match logic
 Write operation:
 If the entire memory is loaded with new
information at once prior to search operation then
writing can be done by addressing each location
in sequence.
 Tag register contains as many bits as there are
words in memory.
 It contain 1 for active word and 0 for inactive
word.
 If the word is to be inserted, tag register is
scanned until 0 is found and word is written at
that position and bit is change to 1.
 Read Operation:
 When a word is to be read from an associative
memory, the contents of the word, or a part of
the word is specified.

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Match logic

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Cache memory
 If the active portions of the program and data are
placed in a fast small memory, the average memory
access time can be reduced,
 Thus reducing the total execution time of the program
 Such a fast small memory is referred to as cache
memory
 The cache is the fastest component in the memory
hierarchy and approaches the speed of CPU
component.

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Cache memory
 When CPU needs to access memory, the cache is
examined
 If the word is found in the cache, it is read from the fast
memory. It is called as a hit.
 If the word addressed by the CPU is not found in the
cache, the main memory is accessed to read the word. It is
called as a miss.
 The performance of cache memory is frequently
measured in terms of a quantity called hit ratio.
 When the CPU refers to memory and finds the word in
cache, it is said to produce a hit.
 Otherwise, it is a miss
 Hit ratio = hit / (hit+miss)

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Cache memory
 The basic characteristic of cache memory is its fast
access time,
 Therefore, very little or no time must be wasted when
searching the words in the cache

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Cache organization (Mapping Process)

The transformation of data from main memory to

cache memory is referred to as a mapping process,
there are three types of mapping:
 Associative mapping
 Direct mapping
 Set-associative mapping

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Associative Mapping
 Fastest and most flexible.
 Uses an associative memory.
 Stores both the address and content
(data) of the memory word.
 Permits any location in cache to
store any word from main memory.
 A CPU address of 15 bits is place
in the argument register and the
associative memory is searched for
a matching address.
 If the address is found, the
corresponding 12-bit data is read
and sent to the CPU. If not, then the
main memory is accessed for the
same word.
 If the cache is full, an address-data pair must be displaced to make the
room for new pair that is not available in cache (FIFO replacement policy).

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Direct Mapping
 Associative memories are expensive compared to RAM because of the
added logic associated with each cell.
 The CPU address of 15 bits is divided into two fields. The nine least
significant bits constitute the index field and the remaining six bits form
the tag field.
 The figure shows that main memory needs an address that includes both
the tag and the index bits.
 The number of bits in the index filed is equal to the number of address bits
required to access the cache memory.

Direct Mapping
• Each word in cache consists of the data word and its associated tag. When
a new word is first brought into the cache, the tag bits are stored alongside
the data bits. When the CPU generates a memory request, the index field is
used for the address to access the cache.

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Set-Associative Mapping
 In Direct mapping, two words with the same index (their address) but with
different tag values can’t reside in cache memory at the same time.
 Set-associative mapping based cache organization is an improvement over
the direct mapping where each word of cache can store two or more words of
memory under the same index address. Each word in cache consists of the
data word and its associated tag.

Set-Associative Mapping
 An example of a set-associative
cache organization for a set size of
two.
 Each tag requires six bits and each
data word has 12 bits, so the word
length is 2 (6 + 12) = 36 bits.
 An index address of nine bits can
accommodate 512 words. Thus the
size of cache memory is 512 x 36.
 It can accommodate 1024 words of
main memory since each word of
cache contains two data words.
 In general, a set-associative cache
of set size k will accommodate k
words of main memory in each
word of cache.

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