LIST OF EXPERIMENTS

Expt. No. 1 2 3 4 Date Name of the Experiment Adders and Subtractors Encoders and Decoders Multiplexers and Demultiplexers Flip Flops Page No. Remarks

EXPT NO: 01 DATE:

ADDERS AND SUBTRACTORS AIM To develop the source code for adders and subtractors by using VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. Step5: Write all possible combinations of input using the test bench. Step6: Obtain the place and route report. Step7: Obtain the design gate count, I/O configuration and Pin assignment Step8: Generate the configuration files (*.bit files for FPGA and *.mcs files for PROM) and download into the FPGA and check the result BASIC ADDERS & SUBTRACTORS A) HALF ADDER LOGIC DIAGRAM TRUTH TABLE

A 0 0 1 1 VERILOG SOURCE CODE: DATAFLOW MODELLING: module ha_data(a,b,sum,carry); input a,b; output sum,carry; assign sum = a ^ b; assign carry = a & b; endmodule BEHAVIORAL MODELING: module ha_behv(a, b, sum, carry);

B 0 1 0 1

SUM CARRY 0 1 1 0 0 0 0 1

input a; input b; output sum; output carry; reg sum, carry; always @ (a or b) begin sum = a^b; carry = a&b; end endmodule STRUCTURAL MODELING: module ha_struct(a, b, sum, carry); input a; input b; output sum; output carry; xor x1(sum,a,b); and a1(carry,a,b); endmodule TESTBENCH module HA_test_v; // Inputs reg a; reg b; // Outputs wire sum; wire carry; // Instantiate the Unit Under Test (UUT) ha_behv ha_tb (.a(a),.b(b),.sum(sum),.carry(carry)); initial begin // Initialize Inputs a <= 1'b0;

b <= 1'b0; #20 ; a <= 1'b0; b <= 1'b1; #35 a <= 1'b1; b <= 1'b0; #50 a <= 1'b1; b <= 1'b1; #75 a <= 1'b0; b <= 1'b0; end endmodule SIMULATION WAVEFORM

RTL SCHEMATIC:

UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "P74" ; NET "b" LOC = "P76" ; NET "carry" LOC = "P84" ; NET "sum" LOC = "P85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE B) HALF SUBTRACTOR LOGIC DIAGRAM TABLE A 0 0 1 1 B 0 1 0 1 TRUTH

DIFFERENCE BORROW 0 1 1 0 0 1 0 0

DATAFLOW MODELING: module hs_dataflow(a, b, dif, bor); input a; input b; output dif; output bor; wire abar; assign abar = ~a; assign dif = a ^ b; assign bor = b & abar; endmodule BEHAVIORAL MODELING: module hs_behv(a, b, dif, bor); input a; input b; output dif, bor; reg dif, bor; reg abar; always@(a or b) begin abar = ~a; dif = a ^ b; bor = b & abar; end endmodule STRUCTURAL MODELING module hs_struct(a, b, dif, bor); input a; input b; output dif; output bor; wire abar; xor x1(dif,a,b); not n1(abar,a); and a1(bor,abar,b);

endmodule TESTBENCH module HS_tb; // Inputs reg a; reg b; // Outputs wire dif; wire bor; // Instantiate the Unit Under Test (UUT) hs_behv ha_tb (.a(a),.b(b),.dif(dif),.bor(bor)); initial begin // Initialize Inputs a <= 1'b0; b <= 1'b0; #120 a <= 1'b0; b <= 1'b1; #135 a <= 1'b1; b <= 1'b0; #150 a <= 1'b1; b <= 1'b1; #175 a <= 1'b0; b <= 1'b0; end endmodule SIMULATION WAVEFORM

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UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "P74" ; NET "b" LOC = "P76" ; NET "bor" LOC = "P84" ; NET "dif" LOC = "P85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE C) FULL ADDER LOGIC DIAGRAM

LOGIC DIAGRAM USING 2 FULL ADDERS A 0 0 0 0 1 1 1 1 VERILOG SOURCE CODE DATAFLOW MODELING: module fulladddataflow(a, b, cin, sum, carry); input a; input b; input cin; output sum; output carry; assign sum = a ^ b ^ cin; B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1

TRUTH TABLE: SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

assign carry = (a & b) | (b & cin) | (cin & a); endmodule BEHAVIORAL MODELING module fabehavioral(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; reg sum,carry; reg t1,t2,t3; always @ (a or b or c) begin sum = (a ^ b) ^ c; t1 = a & b; t2 = b & c; t3 = a & c; carry = (t1 | t2) | t3; end endmodule STRUCTURAL MODELING module fa_struct(a, b, c, sum, carry); input a, b, c; output sum, carry; wire p,q,r,s; xor x1(p,a,b); xor x2(sum,p,c); and a1(q,a,b); and a2(r,b,c); and a3(s,a,c); or o1(carry,q,r,s); endmodule

TESTBENCH module FA_tb_v; // Inputs reg a, b, c; // Outputs wire sum, carry; // Instantiate the Unit Under Test (UUT) fa_struct fa_test(.a(a),.b(b),.c(c),.sum(sum),.carry(carry)); initial begin // Initialize Inputs a <= 1'b0; b <= 1'b0; c <= 1'b0; #20 a <= 1'b0; b <= 1'b0; c <= 1'b1; #35 a <= 1'b0; b <= 1'b1; c <= 1'b0; #50 a <= 1'b0; b <= 1'b1; c <= 1'b1; #75 a <= 1'b1; b <= 1'b0; c <= 1'b0; #100 a <= 1'b1; b <= 1'b0; c <= 1'b1; #150 a <= 1'b1; b <= 1'b1; c <= 1'b0; #175 a <= 1'b1; b <= 1'b1; c <= 1'b1; #185 a <= 1'b0; b <= 1'b0; c <= 1'b0; end endmodule SIMULATION WAVEFORM

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UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "P74" ; NET "b" LOC = "P76" ; NET "c" LOC = "P77" ; NET "carry" LOC = "P84" ; NET "sum" LOC = "P85" ; #PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE D) FULL SUBTRACTOR LOGIC DIAGRAM A 0 0 0 0 1 1 1 1 VERILOG SOURCE CODE DATAFLOW MODELING: module fsdataflow(a, b, cin, diff, borrow); input a, b, cin; output diff, borrow; wire abar; assign abar = ~ a; assign diff = a ^ b ^ cin; assign borrow = (abar & b) | (b & cin) |(cin & abar); endmodule BEHAVIORAL MODELING: module fsbehavioral(a, b, cin, diff, borrow); input a, b, cin; output diff, borrow; reg t1,t2,t3; reg diff,borrow; reg abar; always @ (a or b or cin) begin TRUTH TABLE: B C DIFFERENCE BORROW 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1

abar = ~ a; diff = (a ^ b) ^ cin; t1=abar & b; t2=b & cin; t3=cin & abar; borrow=(t1 | t2) | t3; end endmodule STRUCTURAL MODELING: module fs_struct(a, b, c, diff, borrow); input a, b, cin; output diff, borrow; wire abar,p,q,r,s; not n1(abar,a); xor x1(p,a,b); xor x2(diff,p,c); and a1(q,abar,b); and a2(r,abar,c); and a3(s,a,c); or o1(borrow,q,r,s); endmodule TESTBENCH module FS_tb_v; // Inputs reg a, b, cin; // Outputs wire diff, borrow; // Instantiate the Unit Under Test (UUT) fsdataflow fs_test(.a(a),.b(b),.cin(cin),.diff(diff),.borrow(borrow)); initial begin // Initialize Inputs a <= 1'b0; b <= 1'b0;

cin <= 1'b0; #20 a <= 1'b0; b <= 1'b0; cin <= 1'b1; #35 a <= 1'b0; b <= 1'b1; cin <= 1'b0; #50 a <= 1'b0; b <= 1'b1; cin <= 1'b1; #75 a <= 1'b1; b <= 1'b0; cin <= 1'b0; #100 a <= 1'b1; b <= 1'b0; cin <= 1'b1; #150 a <= 1'b1; b <= 1'b1; cin <= 1'b0; #175 a <= 1'b1; b <= 1'b1; cin <= 1'b1; #185 a <= 1'b0; b <= 1'b0; cin <= 1'b0; end endmodule SIMULATION OUTPUT

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UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "P74" ; NET "b" LOC = "P76" ; NET "borrow" LOC = "P84" ; NET "cin" LOC = "P77" ; NET "diff" LOC = "P85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE E) 8 BIT ADDERS VERILOG SOURCE CODE STRUCTURAL MODELING:

module clkadd(x, y, cin, sum, cout); input [7:0] x; input [7:0] y; input cin; output [7:0] sum; output cout; wire a1,a2,a3,a4,a5,a6,a7; fulladddataflow f1(x[0],y[0],cin,sum[0],a1), f2(x[1],y[1],a1,sum[1],a2), f3(x[2],y[2],a2,sum[2],a3), f4(x[3],y[3],a3,sum[3],a4), f5(x[4],y[4],a4,sum[4],a5), f6(x[5],y[5],a5,sum[5],a6), f7(x[6],y[6],a6,sum[6],a7), f8(x[7],y[7],a7,sum[7],cout); endmodule FULLADD COMPONENT SOURCE CODE: module fulladddataflow(a, b, cin, sum, carry); input a; input b; input cin; output sum; output carry; assign sum = a ^ b ^ cin; assign carry = (a & b) | (b & cin) | (cin & a); endmodule TESTBENCH module Adder_tb_v; // Inputs reg [7:0] x; reg [7:0] y; reg cin; // Outputs wire [7:0] sum; wire cout;

// Instantiate the Unit Under Test (UUT) clkadd adder_test(.x(x),.y(y),.cin(cin),.sum(sum),.cout(cout)); initial begin // Initialize Inputs x <= 8'b00000000; y <= 8'b0000000; cin <= 1'b0; #30 x <= 8'b00000001; y <= 8'b00000010; cin <= 1'b0; #50 x <= 8'b00000011; y <= 8'b00000010; cin <= 1'b0; #60 x <= 8'b00000111; y <= 8'b00001010; cin <= 1'b0; #70 x <= 8'b10000001; y <= 8'b00000010; cin <= 1'b1; #90 x <= 8'b00001111; y <= 8'b00011110; cin <= 1'b0; #100 x <= 8'b01100111; y <= 8'b00001110; cin <= 1'b1; end endmodule

SIMULATION OUTPUT

RTL SCHEMATIC

UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "cin" LOC = "P2" ; NET "cout" LOC = "P3" ; NET "sum<0>" LOC = "P4" ; NET "sum<1>" LOC = "P5" ; NET "sum<2>" LOC = "P7" ; NET "sum<3>" LOC = "P10" ; NET "sum<4>" LOC = "P11" ; NET "sum<5>" LOC = "P13" ; NET "sum<6>" LOC = "P15" ; NET "sum<7>" LOC = "P16" ; NET "x<0>" LOC = "P18" ; NET "x<1>" LOC = "P19" ; NET "x<2>" LOC = "P20" ; NET "x<3>" LOC = "P21" ; NET "x<4>" LOC = "P22" ; NET "x<5>" LOC = "P24" ;

NET "x<6>" NET "x<7>" NET "y<0>" NET "y<1>" NET "y<2>" NET "y<3>" NET "y<4>" NET "y<5>" NET "y<6>" NET "y<7>"

LOC = "P26" LOC = "P27" LOC = "P28" LOC = "P29" LOC = "P31" LOC = "P33" LOC = "P34" LOC = "P35" LOC = "P36" LOC = "P37"

; ; ; ; ; ; ; ; ; ;

#PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

RESULT Thus the OUTPUTs of Adders, Subtractors were verified by synthesizing and simulating the VERILOG code.

EXPT NO: 02 DATE: ENCODERS AND DECODERS AIM To develop the source code for Encoders and Decoders by using VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. Step5: Write all possible combinations of input using the test bench. Step6: Obtain the place and route report. Step7: Obtain the design gate count, I/O configuration and Pin assignment Step8: Generate the configuration files (*.bit files for FPGA and *.mcs files for PROM) and download into the FPGA and check the result A) ENCODER TRUTH TABLE D0 D1 D2 D3 D4 D5 D6 D7 X Y Z 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

LOGIC DIAGRAM

VERILOG SOURCE CODE DATAFLOW MODELING: module encod_data(d, x, y, z); input [7:0] d; output x, y, z; assign x=d[4]|d[5]|d[6]|d[7]; assign y=d[2]|d[3]|d[6]|d[7]; assign z=d[1]|d[3]|d[5]|d[7]; endmodule STRUCTURAL MODELING: module encod_struct(d, x, y, z); input [7:0] d; output x, y, z; or o1(x,d[4],d[5],d[6],d[7]); or o2(y,d[2],d[3],d[6],d[7]); or o3(z,d[1],d[3],d[5],d[7]); endmodule TESTBENCH module Encoder_tb_v; // Inputs reg [7:0] d; // Outputs wire x,y,z; // Instantiate the Unit Under Test (UUT) encod_data encoder_test(.d(d), .x(x),.y(y),.z(z)); initial begin // Initialize Inputs d = 8'b00000000; #20 d = 8'b10110000;

#30 d = 8'b11001100; #50 d = 8'b10101010; #80 d = 8'b10001100; #100 d = 8'b11001100; #120 d = 8'b10101010; #140 d = 8'b11001100; #160 d = 8'b10000000; end endmodule SIMULATION WAVEFORM

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UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENT FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "d<0>" LOC = "P74" ; NET "d<1>" LOC = "P76" ; NET "d<2>" LOC = "P77" ; NET "d<3>" LOC = "P78" ; NET "d<4>" LOC = "P79" ; NET "d<5>" LOC = "P81" ; NET "d<6>" LOC = "P82" ; NET "d<7>" LOC = "P83" ; NET "x" LOC = "P84" ; NET "y" LOC = "P85" ; NET "z" LOC = "P86" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE B) DECODER TRUTH TABLE A 0 0 1 1 B 0 1 0 1 E 1 1 1 1 Z(0 ) 0 1 1 1 Z(1 ) 1 0 1 1 Z(2 ) 1 1 0 1 Z(3) 1 1 1 0

LOGIC DIAGRAM

VERILOG SOURCE CODE DATAFLOW MODELING: module decoderdataflow (a, b, en, z); input a,b,en; output [0:3] z; wire abar,bbar; assign abar=~a; assign bbar =~b; assign z[0]=(abar & bbar & en); assign z[1]=(abar & b & en); assign z[2]=(a & bbar & en); assign z[3]=(a & b & en); endmodule BEHAVIORAL MODELING: module decoderbehv(a, b, en, z); input a, b, en; output [3:0] z; reg [3:0] z; always @ (a,b,en) begin z[0] = ~ ((~a) & (~b) & en); z[1] = ~ ((~a) & b & en); z[2] = ~ (a & (~b) & en); z[3] = ~ (a & b & en); end endmodule STRUCTURAL MODELING: module decod_struct(a, b, e, z); input a, b, e; output [3:0] z; wire abar,bbar;

not n1(abar,a); not n2(bbar,b); and a1(z[0],abar,bbar,e); and a2(z[1],abar,b,e); and a3(z[2],a,bbar,e); and a4(z[3],a,b,e); endmodule 3 TO 8 DECODER USING PROCESS STATEMENTS module decoder_3 (a, enable, y); input [2:0] a; input enable; output [7:0] y; reg [7:0] y; always @(enable or a) begin if (enable) y = 8'b11111111; else case (a) 3'b000 : y = 8'b01111111; 3'b001 : y = 8'b10111111; 3'b010 : y = 8'b11011111; 3'b011 : y = 8'b11101111; 3'b100 : y = 8'b11110111; 3'b101 : y = 8'b11111011; 3'b110 : y = 8'b11111101; 3'b111 : y = 8'b11111110; default : $display("Invalid signal"); endcase end endmodule TESTBENCH PROGRAM module decoder3_tb; wire [7:0]y1; reg [2:0]a1; reg enable1;

decoder_3 decoder3_test(a1,enable1,y1); initial fork enable1 = 1'b0; #35 enable1 = 1'b1; #50 enable1 = 1'b0; a1 = 3'b000; #5 a1 = 3'b001; #10 a1 = 3'b010; #14 a1 = 3'b011; #18 a1 = 3'b100; #19 a1 = 3'b101; #25 a1 = 3'b110; #34 a1 = 3'b111; #40 a1 = 3'b001; #45 a1 = 3'b101; #55 a1 = 3'b011; #65 a1 = 3'b111; #69 a1 = 3'b001; join endmodule SIMULATION WAVEFORM

RTL SCHEMATIC

UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "P74" ; NET "b" LOC = "P76" ; NET "en" LOC = "P77" ;

NET "z<0>" NET "z<1>" NET "z<2>" NET "z<3>"

LOC = "P84" LOC = "P85" LOC = "P86" LOC = "P87"

; ; ; ;

#PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE RESULT Thus the Outputs of Encoder and Decoder was verified by synthesizing and simulating the VERILOG code.

EXPT NO: 03 DATE: MULTIPLEXER AND DEMULTIPLEXER AIM To develop the source code for Multiplexer and Demultiplexer by using VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. Step5: Write all possible combinations of input using the test bench. Step6: Obtain the place and route report. Step7: Obtain the design gate count, I/O configuration and Pin assignment Step8: Generate the configuration files (*.bit files for FPGA and *.mcs files for PROM) and download into the FPGA and check the result A) MULTIPLEXER: SELECT INPUT S1 0 0 1 1 S0 0 1 0 1 OUTPUT Y D0 D1 D2 D3 TRUTH TABLE:

LOGIC DIAGRAM
D 0
1 2 8 9

D 1

1 2 8

9 2 3 4 5 9

D 2

1 2 8

D 3

1 2 8

S 1

S 0

VERILOG SOURCE CODE DATAFLOW MODELING: module muxdataflow(s, i, y);

input [1:0] s; input [3:0] i; output y; wire s2,s3,s4,s5,s6,s7; assign s2 = ~s[1]; assign s3 = ~s[0]; assign s4 = i[0]&s2&s3; assign s5 = i[1]&s2&s[0]; assign s6 = i[2]&s[1]&s3; assign s7 = i[3]&s[1]&s[0]; assign y = s4 | s5 | s6 | s7; endmodule ALTERNATE METHOD USING DATAFLOW MODELLING module mux4_data(a,b,c,d,s0,s1,y); input a,b,c,d,s0,s1; output y; assign y = ((a & (~s0) & (~s1)) | (b & (~s0) & s1) | (c & s0 & (~s1)) s1)); endmodule BEHAVIORAL MODELING: module mux4_behav(a,b,c,d,s,y); input a,b,c,d; input [1:0]s; output y; reg y; always @ (s or a or b or c or d ) case (s) 2'b00 : y = a; 2'b01 : y = b; 2'b10 : y = c; 2'b11 : y = d; default : $display ("Incorrect select signal"); endcase endmodule | (d & s0 &

STRUCTURAL MODELING: module mux_struct(i, s0, s1, y); input [3:0] i; input s0; input s1; output y; wire s2,s3,s4,s5,s6,s7; not n1(s2,s1); not n2(s3,s0); and a1(s4,i[0],s2,s3); and a2(s5,i[1],s2,s0); and a3(s6,i[2],s1,s3); and a4(s7,i[3],s1,s0); or o1(y,s4,s5,s6,s7); endmodule 4*1 MULTIPLEXER USING IF ELSE CONDITION module mux4_behav1(a,b,c,d,s,y); input a,b,c,d; input [1:0]s; output y; reg y; always @ (s or a or b or c or d ) begin if (s == 00) y = a; else if (s == 01) y = b; else if (s == 10) y = c; else if (s == 11) y = d; else $display ("Invalid Select no"); end end

endmodule TESTBENCH FOR 4*1 MULTIPLEXER module muxbehav_tb; wire y1; reg a1,b1,c1,d1; reg [1:0] s1; mux4_behav muxbehav_test(a1,b1,c1,d1,s1,y1); initial fork a1 = 1'b1; b1 = 1'b1; c1 = 1'b0; d1 = 1'b0; s1[0] = 1'b0; s1[1] = 1'b0; #5 s1[0] = 1'b0; #5 s1[1] = 1'b1; #15 s1[0] = 1'b1; #15 s1[1] = 1'b0; #25 s1[0] = 1'b1; #25 s1[1] = 1'b1; #7 a1 = 1'b0; #7 b1 = 1'b0; #7 c1 = 1'b1; #7 d1 = 1'b1; #20 a1 = 1'b1; #20 b1 = 1'b0; #20 c1 = 1'b1; #20 d1 = 1'b1; join endmodule SIMULATION WAVEFORM

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UCF (USER CONSTRAINTS FILE) OR PIN ASSIGNMENTS FILE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "i<0>" LOC = "P2" ; NET "i<1>" LOC = "P3" ; NET "i<2>" LOC = "P4" ; NET "i<3>" LOC = "P5" ; NET "s<0>" LOC = "P7" ; NET "s<1>" LOC = "P9" ; NET "y" LOC = "P10" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE B) DEMULTIPLEXER TRUTH TABLE

D 1 1 1 1

INPUT S0 0 0 1 1

S1 0 1 0 1

Y0 1 0 0 0

OUTPUT Y1 Y2 Y3 0 0 0 1 0 0 0 1 0 0 0 1 `
S 0

LOGIC DIAGRAM
S 1

D i n

2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5

Y 0

Y 1

Y 2

Y 3

E n a b l e

VERILOG SOURCE CODE

DATAFLOW MODELING module demuxdataflow(s0,s1,i,y); input s0,s1,i; output [3:0] y; wire s2,s3; assign s2=~s0; assign s3=~s1; assign y[0]=i&s2&s3; assign y[1]=i&s2&s1; assign y[2]=i&s0&s3; assign y[3]=i&s0&s1; endmodule BEHAVIORAL MODELING module demux_behv(s0, s1, i, y); input s0, s1, i; output [3:0] y; reg [3:0] y; reg s2,s3; always@(i or s0 or s1) begin s2=~s0; s3=~s1; y[0]=i & s2 & s3; y[1]=i & s2 & s1; y[2]=i & s0 & s3; y[3]=i & s0 & s1; end endmodule ALTERNATE METHOD USING BEHAVIORAL MODELING module Demulti(in, s, out); input in; input [2:0] s; output reg [7:0] out; always @(in) begin if (s==3'b000)

out[0]<=in; else if (s==3'b001) out[1]<=in; else if (s==3'b010) out[2]<=in; else if (s==3'b011) out[3]<=in; else if (s==3'b100) out[4]<=in; else if (s==3'b101) out[5]<=in; else if (s==3'b110) out[6]<=in; else out[7]<=in; end endmodule STRUCTURAL MODELING module demux_struct(s0, s1, i, y); input s0, s1, i; output [3:0] y; wire s2,s3; not n1(s2,s0); not n2(s3,s1); and a1(y[0],i,s2,s3); and a2(y[1],i,s2,s1); and a3(y[2],i,s0,s3); and a4(y[3],i,s0,s1); endmodule TESTBENCH PROGRAM SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF RESULT Thus the Outputs of Multiplexers and Demultiplexers were verified by synthesizing and simulating the VERILOG code.

EXPT NO: 04 DATES: FLIP FLOPS AIM To develop the source code for Flip Flops (SR, D, JK and T) by using VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. Step5: Write all possible combinations of input using the test bench. Step6: Obtain the place and route report. Step7: Obtain the design gate count, I/O configuration and Pin assignment Step8: Generate the configuration files (*.bit files for FPGA and *.mcs files for PROM) and download into the FPGA and check the result A) SR FLIPFLOP: LOGIC DIAGRAM Q(t)
S
1 2 3 1 2 3

TRUTH TABLE: S 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 R Q(t+1) 0 0 1 X 1 0 1 X

C P
1 1 2 3 2 3

0 0 0 0 1 1 1 1

VERILOG SOURCE CODE BEHAVIORAL MODELING: module srflipflop(s, r, clk, rst, q, qbar); input s, r, clk, rst; output q, qbar; reg q,qbar; always @ (posedge(clk) or posedge(rst)) begin

if(rst==1'b1) begin q= 1'b0; qbar= 1'b1; end else if (s==1'b0 && r==1'b0) begin q=q; qbar=qbar; end else if(s==1'b0 && r==1'b1) begin q= 1'b0; qbar= 1'b1; end else if(s==1'b1 && r==1'b0) begin q= 1'b1; qbar= 1'b0; end else begin q=1'bx; qbar=1'bx; end end endmodule TESTBENCH PROGRAM module srff_tb; wire q_out, qbar_out; reg j_in, k_in, clk_in, rst_in; srflipflop srff_test (s_in, r_in, clk_in, rst_in, q_out, qbar_out); initial #3 clk_in = 1'b0; always #5 clk_in = ~ clk_in; initial

fork s_in = 1'b1; r_in = 1'b1 #25 s_in = 1'b0; #25 r_in = 1'b0; #28 s_in = 1'b1; #55 s_in = 1'b1; #55 r_in = 1'b1; #57 s_in = 1'b0; #58 s_in = 1'b1; #59 s_in = 1'b0; #65 s_in = 1'b1; #67 s_in = 1'b0; #68 s_in = 1'b1; #70 s_in = 1'b0; #73 s_in = 1'b1; #78 s_in = 1'b0; #80 s_in = 1'b1; #80 r_in = 1'b0; #84 s_in = 1'b0; #84 r_in = 1'b1; rst_in = 1'b0; #7 rst_in = 1'b1; #27 rst_in = 1'b0; #66 rst_in = 1'b1; #69 rst_in = 1'b0; join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF B) JK FLIPFLOP: LOGIC DIAGRAM TABLE: TRUTH

Q(t) 0 0 0 0 1 1 1 1
K
1 2 8 9 1 2

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 1 1 0 1 0

C P
1 2 8 1 9 2 3

VERILOG SOURCE CODE BEHAVIORAL MODELING: module jkff(j, k, clk, rst, q, qbar); input j, k, clk, rst; output q, qbar; reg q, qbar; always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin q=1'b0; qbar=1'b1; end else if (j==1'b0 && k==1'b0) begin q=q; qbar=qbar; end

else if (j==1'b0 && k==1'b1) begin q=1'b0; qbar=1'b1; end else if (j==1'b1 && k==1'b0) begin q=1'b1; qbar=1'b0; end else begin q=~q; qbar=~qbar; end end endmodule TESTBENCH PROGRAM module jkff_tb; wire q_out, qbar_out; reg j_in, k_in, clk_in, rst_in; jkff jkff_test (j_in, k_in, clk_in, rst_in, q_out, qbar_out); initial #3 clk_in = 1'b0; always #5 clk_in = ~ clk_in; initial fork j_in = 1'b1; k_in = 1'b1 #25 j_in = 1'b0; #25 k_in = 1'b0; #28 j_in = 1'b1; #55 j_in = 1'b1; #55 k_in = 1'b1; #57 j_in = 1'b0; #58 j_in = 1'b1;

#59 j_in = 1'b0; #65 j_in = 1'b1; #67 j_in = 1'b0; #68 j_in = 1'b1; #70 j_in = 1'b0; #73 j_in = 1'b1; #78 j_in = 1'b0; #80 j_in = 1'b1; #80 k_in = 1'b0; #84 j_in = 1'b0; #84 k_in = 1'b1; rst_in = 1'b0; #7 rst_in = 1'b1; #27 rst_in = 1'b0; #66 rst_in = 1'b1; #69 rst_in = 1'b0; join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF C) D FLIP FLOP LOGIC DIAGRAM
D
1 2 1 2 3 1 2 3

TRUTH TABLE: Q(t) 0 0 1 1 D 0 1 0 1 Q(t+1) 0 1 0 1

C P
1 1 3 2 3 2 3

VERILOG SOURCE CODE module d_ff(clk, rst, d, q); input clk, rst, d; output reg q; always @(posedge clk)

begin if (rst == 1) q <= 0; else q <= d; end endmodule TESTBENCH FOR D FLIP FLOP module dff_tb; wire q_out; reg d_in, clk_in, rst_in; d_ff dff_test(clk_in, rst_in, d_in, q_out); initial clk_in = 1'b0; always #5 clk_in = ~ clk_in; initial fork d_in = 1'b1; #25 d_in = 1'b0; #28 d_in = 1'b1; #55 d_in = 1'b1; #57 d_in = 1'b0; #58 d_in = 1'b1; #59 d_in = 1'b0; #65 d_in = 1'b1; #67 d_in = 1'b0; #68 d_in = 1'b1; #70 d_in = 1'b0; #73 d_in = 1'b1; #78 d_in = 1'b0; #80 d_in = 1'b1; #84 d_in = 1'b0; rst_in = 1'b0; #7 rst_in = 1'b1; #27 rst_in = 1'b0; #66 rst_in = 1'b1;

#69 rst_in = 1'b0; join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF

D) T FLIP FLOP LOGIC DIAGRAM TRUTH TABLE: Q(t)

T 0 1 0 1

Q(t+1) 0 1 1 0

0 0 1 1

C P
1 2 8 1 9 2 3

VERILOG SOURCE CODE BEHAVIORAL MODELING: module tff(t, clk, rst, q, qbar); input t, clk, rst; output q, qbar; reg q, qbar; always @ (posedge(clk) or posedge(rst)) begin if(rst==1'b1)

begin q= 1'b0; qbar= 1'b1; end else if (t==1'b0) begin q=q; qbar=qbar; end else begin q=~q; qbar=~qbar; end end endmodule TESTBENCH PROGRAM module tff_tb; wire q_out, qbar_out; reg t_in, clk_in, rst_in; tff tff_test (t_in, clk_in, rst_in, q_out, qbar_out); initial #3 clk_in = 1'b0; always #5 clk_in = ~ clk_in; initial fork t_in = 1'b1; #25 t_in = 1'b0; #28 t_in = 1'b1; #55 t_in = 1'b1; #57 t_in = 1'b0; #58 t_in = 1'b1; #59 t_in = 1'b0; #65 t_in = 1'b1; #67 t_in = 1'b0; #68 t_in = 1'b1; #70 t_in = 1'b0; #73 t_in = 1'b1;

#78 t_in = 1'b0; #80 t_in = 1'b1; #84 t_in = 1'b0; rst_in = 1'b0; #7 rst_in = 1'b1; #27 rst_in = 1'b0; #66 rst_in = 1'b1; #69 rst_in = 1'b0; join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF E) MASTER-SLAVE SR FLIP-FLOP: LOGIC DIAGRAM

VERILOG SOURCE CODE STRUCTURAL MODELING module srff_ms(s, r, clk, rst, q, qbar); input s, r, clk, rst; output q, qbar; wire s1,r1; srflipflop sr1(s,r,clk,rst,s1,r1), srflipflop sr2(s1,r1,~clk,rst,q,qbar);

endmodule SRFLIPFLOP COMPONENT SOURCE CODE module srflipflop(s, r, clk, rst, q, qbar); input s, r, clk, rst; output q, qbar; reg q,qbar; always @ (posedge(clk) or posedge(rst)) begin if(rst==1'b1) begin q= 1'b0; qbar= 1'b1; end else if(s==1'b0 && r==1'b0) begin q=q; qbar=qbar; end else if(s==1'b0 && r==1'b1) begin q= 1'b0; qbar= 1'b1; end else if(s==1'b1 && r==1'b0) begin q= 1'b1; qbar= 1'b0; end else begin q=1'bx; qbar=1'bx; end end endmodule TESTBENCH PROGRAM SIMULATION WAVEFORM

RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF F) D LATCH module d_latch(d,en,reset,q); input d, en, reset; output q; reg q; always @(posedge reset or en or d) begin if (reset) q = 1'b0; else if(en) q = d; end endmodule TESTBENCH FOR D LATCH module dlatch_tb; wire q_out; reg d_in,en_in,reset_in; d_latch dlatch_test(d_in,en_in,reset_in,q_out); initial en_in = 1'b0; always #5 en_in = ~ en_in; initial fork d_in = 1'b1; #25 d_in = 1'b0; #28 d_in = 1'b1; #55 d_in = 1'b1;

#57 d_in = 1'b0; #58 d_in = 1'b1; #59 d_in = 1'b0; #65 d_in = 1'b1; #67 d_in = 1'b0; #68 d_in = 1'b1; #70 d_in = 1'b0; #73 d_in = 1'b1; #78 d_in = 1'b0; #80 d_in = 1'b1; #84 d_in = 1'b0; reset_in = 1'b0; #7 reset_in = 1'b1; #27 reset_in = 1'b0; #66 reset_in = 1'b1; #69 reset_in = 1'b0; join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF G) D FLIP FLOP WITH ASYNCHRONOUS PRESET module d_ffpreset(d,clk,reset,preset,q); input d, clk, reset, preset; output q; reg q; always @(posedge reset or posedge preset or negedge clk) begin if (reset) q = 1'b0; else if (preset) q = 1'b1; else q = d; end endmodule

TESTBENCH FOR D FLIP FLOP WITH ASYNCHRONOUS PRESET module dffpreset_tb; wire q_out; reg d_in, clk_in, reset_in, preset_in; d_ffpreset dffpreset_test(d_in, clk_in, reset_in, preset_in, q_out); initial #3 clk_in = 1'b0; always #5 clk_in = ~ clk_in; initial fork d_in = 1'b1; #25 d_in = 1'b0; #28 d_in = 1'b1; #55 d_in = 1'b1; #57 d_in = 1'b0; #58 d_in = 1'b1; #59 d_in = 1'b0; #65 d_in = 1'b1; #67 d_in = 1'b0; #68 d_in = 1'b1; #70 d_in = 1'b0; #73 d_in = 1'b1; #78 d_in = 1'b0; #80 d_in = 1'b1; #84 d_in = 1'b0; reset_in = 1'b0; #7 reset_in = 1'b1; #27 reset_in = 1'b0; #66 reset_in = 1'b1; #69 reset_in = 1'b0; preset_in = 1'b0; #6 preset_in = 1'b1; #24 preset_in = 1'b0; #30 preset_in = 1'b1; #55 preset_in = 1'b0; #66 preset_in = 1'b1; #69 preset_in = 1'b0;

join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF H) D LATCH USING ASYNCHRONOUS PRESET module dlatch_preset(d, en, reset, preset, q); input d, en, reset, preset; output q; reg q; always @(posedge reset or posedge preset or en or d) begin if (reset) q = 1'b0; else if (preset) q = 1'b1; else if(en) q = d; end endmodule TESTBENCH FOR D LATCH USING ASYNCHRONOUS PRESET module dlatchpreset_tb; wire q_out; reg d_in, en_in, reset_in, preset_in; dlatch_preset dlatchpreset_test(d_in, en_in, reset_in, preset_in, q_out); initial #3 en_in = 1'b0; always #5 en_in = ~ en_in;

initial fork d_in = 1'b1; #25 d_in = 1'b0; #28 d_in = 1'b1; #55 d_in = 1'b1; #57 d_in = 1'b0; #58 d_in = 1'b1; #59 d_in = 1'b0; #65 d_in = 1'b1; #67 d_in = 1'b0; #68 d_in = 1'b1; #70 d_in = 1'b0; #73 d_in = 1'b1; #78 d_in = 1'b0; #80 d_in = 1'b1; #84 d_in = 1'b0; reset_in = 1'b0; #7 reset_in = 1'b1; #27 reset_in = 1'b0; #66 reset_in = 1'b1; #69 reset_in = 1'b0; preset_in = 1'b0; #6 preset_in = 1'b1; #24 preset_in = 1'b0; #30 preset_in = 1'b1; #55 preset_in = 1'b0; #66 preset_in = 1'b1; #69 preset_in = 1'b0; join endmodule SIMULATION WAVEFORM RTL SCHEMATIC SYNTHESIS REPORT PIN ASSIGNMENT OR UCF

RESULT Thus the Outputs of Flip Flops were verified by synthesizing and simulating the VERILOG code.