(Approved by AICTE, New Delhi & Affiliated to VTU, Belegavi, Karnataka)

181/1, 182/1, Behind SAP Labs, Seetharam Palya, Basavanagar, Hoodi, Bangalore - 560 048
______________________________________________________________________
QUESTION BANK

Academic Year : 2023-24

Programme : Computer Science and Engineering
Year/Semester/Section : II/ III/ nil
Course Code/ Name : BCS302/ Digital Design and Computer Organization
Faculty Name : Vinay G

MODULE - 1: Title
Introduction to Digital Design: Binary Logic, Basic Theorems And Properties Of Boolean Algebra,
Boolean Functions, Digital Logic Gates, Introduction, The Map Method, Four-Variable Map, Don’t-Care
Conditions, NAND and NOR Implementation, Other Hardware Description Language – Verilog Model of a
simple circuit.
CO1 Apply the K–Map techniques to simplify various Boolean expressions.
**Revised Bloom’s Taxonomy (RBT) Levels
RBT Remember Understand Apply Analyze Evaluate Create
RBT Levels L1 L2 L3 L4 L5 L6

RBT**
Q. No. Questions Marks COs*
level
Define the following:i)Truth table ii)Logic Gate iii) Implicant iv) 10 CO 1 L1
1.
prime Implicant v) Essential Prime Implicant
List the steps for implementing a Boolean function with 2 level L3
2. NAND gate. Apply the same to implement the following 06 CO 1
Boolean function with NAND gate F(x,y,z)=m(1,2,3,4,5,7)
3. What is HDL? Write a Verilog code for implementation i) Full L3
10 CO 1
adder. ii) A=BC+B’D
4. Simplify the following expression to a minimum no of L3
10 CO 1
literals i) XY+X’Z+YZ
Define K –map. Simplify the following using K- map: L3
5. i)F(a,b,c,d)=m(4,5,6,7,12,13,14)+d(1,9,11,15) 08 CO 1
ii)F(a,b,c,d)= (1,2,3,8,9,11,14)
6. Define i)Implicant ii) Prime Implicant iii) Essential Prime 08 CO 1 L2
Implicant. Find all essential prime implicant for the expression:
F(a,b,c,d)=(0,2,3,5,7,8,9,10,11,13,15)
L3
7. What is Binary Logic. List Postulates and Theorems of Boolean 05 CO 1
Algebra. Prove that i) X+X=X
8. Explain the three basic logic operations. 06 CO 1 L1
9. Demonstrate Positive and negative logic. 06 CO 1 L1
L3
10. Find the POS expression for F(a,b,c,d) = Π(2,3,5,8,10,13,14) + 06 CO 1
d(1,6,7,11) and draw the circuit diagram for the simplified expression.
11. What is HDL? Explain the different types HDL Models used for L2
06 CO 1
designing Combinational Circuits using Verilog.
12. Simplify the following Boolean Expression using kmap: 08 CO1 L3
MODULE - 2: Title
Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary Adder- Subtractor,
Decoders, Encoders, Multiplexers. HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder.
Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-Flops.
CO 2 Design different types of combinational and sequential circuits along with Verilog programs.
**Revised Bloom’s Taxonomy (RBT) Levels
RBT Remember Understand Apply Analyze Evaluate Create
RBT Levels L1 L2 L3 L4 L5 L6

RBT**
Q. No. Questions Marks COs*
level
1. What is full adder? Design a full adder using two half adder 08 CO 2 L3
and OR gate?
2. Illustrate the operation of 4-bit adder/ subtrator with neat 08 CO 2 L1
diagram. Design full adder using 3 to 8 decoder
3. Define Combinational Circuit? Explain design procedure of 08 CO 2 L3
combinational logic. Design a combinational circuit for BCD to
Excess-3 code converter.

4. Define Decoder? Explain 3to 8 decoder? 06 CO 2 L2

5. Define Encoder. Explain 4-bit parity encoder. 08 CO 2 L2

6. Explain the working of SR latch and Edge triggered D flip-Flop. 08 CO 2 L2

7. Write Verilog code for 4-bit parallel adder using full adder as 08 CO 2 L3
component.(OR using continues signal assignment statement )
Note: Study lab program.
8. Write a Verilog code for implementing different types of 06 CO 2 L3
multiplexers.
9. Write a Verilog code for implementing half adder ,half 06 CO 2 L3
subtractor,full adder, full subtrator.
10. What is multiplexer? Explain 2:1 and 4:1 multiplexer. 10 CO 2 L3
11. Simplify the following function and implement it by using 8:1 Mux. 10 CO 2 L3
F(A,B,C,D)= Σm(0,1,2,4,5,6,9,10,12,13,14,15).
12. Explain how carry is generated and propagated in a carry look- 10 CO2 L2
ahead adder.
13. 10 CO2 L3
What are decoders? Implement the following Boolean functions with a
decoder:
F1(A,B,C) = Σm(1, 3,4,7),
F2(A,B,C) = Σm(0,2,3,6) and
F3(A,B,C) = Σm(2,3,6,7)

14. 10 CO2 L3
Explain the differences between Combinational and Sequential Circuits with
their block diagrams and examples.
MODULE - 3: Title
Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure, Performance –
Processor Clock, Basic Performance Equation, Clock Rate, Performance Measurement.Machine
Instructions and Programs: Memory Location and Addresses, Memory Operations, Instruction and
Instruction sequencing, Addressing Modes.
CO 3 Describe the fundamentals of machine instructions, addressing modes and Processor performance.
**Revised Bloom’s Taxonomy (RBT) Levels
RBT Remember Understand Apply Analyze Evaluate Create
RBT Levels L1 L2 L3 L4 L5 L6

RBT**
Q. No. Questions Marks COs*
level
1. With a neat diagram explain the basic Operational Concepts 08 CO3 L2
along with operational steps.
2. What is performance Measurement? Explain the overall SPEC 08 CO3 L1
rating for computer in a program suit?
3. Explain the following: 06 CO3 L1
1.Byte Addressability 2.Big Endian assignment 3.Little Endian
assignment
4. Show how the below expression will be executed in one address, two 06 CO3 L3
address, three address processors in an accumulator organization?

5. What is the effective address of the source operand in each of the 06 CO3 L3
following instruction
When register R1 and R2 of computer contains decimal value 1200 and
4600?
1) LOAD 20(R1),R5 2) MOVE #3000,R5 3) Store R5,30(R1,R2)
4)ADD –(R2),R5
4)SUB(R1)+,R5
6. Define addressing modes. Explain Different types of 10 CO3 L2
addressing with example for each.
7. Explain the basic performance equation and explain and define 06 CO3 L1
the terms involved in it.
8. What is adressing mode?Explain the following addressing modes 10 CO3 L2
with an example for each
i)absolute ii) Immediate iii) Indirect iv) Auto increment.
9. Explain Big endian and Little Endian assignment. Consider a 08 CO3 L3
computer that has a byte addressable memory organized in 32
words, according to Little Endian scheme. A program reads ASCII
characters entered at a keyboard and store them in successive byte
location starting at 2000.Show how the contents of three memory
words at location 2000, 2004 and 2008 after the string “ VTU
BELGAVI’ has been entered.(ASCII code: V=56H,T=54H,U=55H,
“ ”=20H, B=42H,E=45H,L=4CH,A=41H,G=47H,I=49H).

10. How to measure performance of computer? Explain. 06 CO3 L1

11. Explain SPEC rating of computer. 06 CO3 L1
12. Explain instruction execution using Straight-Line Sequencing. 08 CO3 L1
13. Explain the functional unit of computer with neat diagram 06 CO3 L1
MODULE - 4: Title
Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and Disabling
Interrupts, Handling Multiple Devices, Direct Memory Access: Bus Arbitration, Speed, size and Cost of
memory systems. Cache Memories – Mapping Functions.
CO 4 Explain the approaches involved in achieving communication between processor and I/O devices.
**Revised Bloom’s Taxonomy (RBT) Levels
RBT Remember Understand Apply Analyze Evaluate Create
RBT Levels L1 L2 L3 L4 L5 L6

RBT**
Q. No. Questions Marks COs*
level
1. Illustrate a program that reads one line from the keyboard and 08 CO4 L3
store it in memory buffer and echoes it back to display in an I/O?
2. What is an Interrupt? What are interrupt service routine and vectored 06 CO4 L1
interrupts? Explain with example
3. Demonstrate DMA and its implementation and show how data is 08 CO4 L1
transferred between memory and I/O device using DMA
controller?
4. With neat diagram , explain centralized bus arbitration and 08 CO4 L1
distributed bus arbitration.
5. Define Cache memory? List and Explain different cache 08 CO4 L2
mapping techniques.
6. What is DMA? Explain the registers in a DMA interface 06 CO4 L1
7. Define Interrupt.With example,explain the concept of 06 CO4 L1
interrupt.What are the overhead in handling interrupt.
8. With neat diagram explain memory hierachy with respect to 06 CO4 L1
speed size and cost.
9. Explain how the I/O devices should be organized in a priority 08 CO4 L2
structure
10. With neat sketch explain the various methods for handling 10 CO4 L2
multiple interrupts request raised by multiple devices.
11. What is interrupt. Explain the mechanism for enabling and 06 CO4 L1
disabling of interrupts?

Basic Processing Unit: Some Fundamental Concepts: Register Transfers, Performing ALU operations,
fetching a word from Memory, Storing a word in memory. Execution of a Complete Instruction. Pipelining:
Basic concepts, Role of Cache memory, Pipeline Performance.
CO 5 Analyze internal Organization of Memory and Impact of cache/Pipelining on Processor Performance.
**Revised Bloom’s Taxonomy (RBT) Levels
RBT Remember Understand Apply Analyze Evaluate Create
RBT Levels L1 L2 L3 L4 L5 L6

RBT**
Q. No. Questions Marks COs*
level
What is pipeline? Explain the 4 stages of pipeline with its 08 CO5 L2
1. instruction execution steps and hardware organization?
Analyze and write the sequence of operation required to execute 08 CO5 L3
2. the following instructions:-
i) ADD (R3), R1. ii) ADD (R3)+,R1
 3.
With neat diagram explain the single bus organization of data 10 CO5 L2
path inside a processor.
What is pipelining? Explain 5 stage pipelines with timing 08 CO5 L2
4.
diagram
Write and control sequence for the following: 10 CO5 L2
5.
i) Storing a word into memory
ii) Reading a word from memory
iii) Branch instruction
What is pipelining? Explain 2 stage pipelines with timing 06 CO5 L2
6.
diagram

Prepared by Approved by

(Name of Faculty / Designation / Dept.) (HOD – DEPT)

Note: Question which are in bold are frequently asked questions in previous
university question papers.