Input-output organization

CPU

Main Memory

Computer
CPU

Main Memory I/O Outside

World

Computer
I/O
Unit

I/O
devices Control Unit
Peripherals

S/W
For I/O operation
 I/O organization is
Function of (computer size, devices connected to this computer)

f (Comp.size, Device connected )

 Input-Output Interface

Computer
Peripheral (CPU)

Special communication for

interfacing with the CPU

Why we need this communication link?

In order to resolve the differences between the CPU & these peripherals
 Q// what are the major differences betn CPU & peripheral and how
It can be solved?

1. Peripherals are electromechanical & electromagnetic devices

(i.e. A/D needed).

2. Differences in data transfer rate (i.e. need synchronization).

3. Data code and format is different.

4. The O.S. of each peripheral is different from other peripheral so

Each one of these peripheral must be controlled.
However, to resolve these differences, a special H/W components
Between the CPU & peripherals is included to supervise &
Synchronize all I/P & O/P transfers which is called interface units
Each peripheral has its own controller which may be housed
Separately or may be integrated with peripheral.
 There are 4 types of commands that an interface may receive:
1. Control command.
2. Status command.
3. Data O/P command.
4. Data I/P command.

I/O Bus & Memory Bus

There are three ways in which the computer buses can be used
to communicate with memory & I/O:
1- use 2 separate buses (separate I/O processor).
2- use 1 common bus (Two separated Control lines).
3- use 1 common bus (one control line i.e. common control line).
 There are 2 types of I/O

Isolated I/O Memory-mapped I/O

Add.
space I/O I/O
Add.
bus
One
Add.
space
Add.
Add. M M bus
space
Add.
bus
Assignment// Compare betn I/O isolated & Memory mapped I/O?
 Data Transfer

serial parallel

Synchronous Asynchronous
 Data Transfer
Common clock
Digital System

CPU M.M.

Registers I/O
 Data Transfer

Synchronous Asynchronous

CPU ck CPU

registers registers ck1

I/O ck2 I/O

ck3

ck4

ck5
 1) Strobe pulse.
2) Handshaking control signal.

ck R1 P (control line)

R2

To indicate the time at which data is being transmitted.

1. Strobe control signal
What are the disadvantages of the strobe control signal????

WHAT is the solution?????

Handshaking

i.e. to acknowledge the data receiving

Handshaking has TOW-wire control

From source to destination

In order to inform the destination Whether there are valid data.

From destination to source

In order to inform the source that data is accepted.

Data valid
Therefore, the two handshaking lines are:

Data accepted
Note: Time out
error
 Serial Communication

Telephone line

modem
Digital signal  audio tones
 synch
This serial communication
Asynch

Note: parallel transmission is faster than serial

BUT…………..
Asynchronous serial transfer

Each character to be transmitted consists of 3 parts:

Asynchronous serial transmission

 Synchronous serial transfer

Doesn’t use start-stop bits

Synchronous transfer must send a continuous message in order to maintain synchronization

H.W.// what are the differences between synchronous and

asynchronous serial transfer of information?
 Modes of transfer

Computer
External devices

Memory
 Therefore, the transfer of data betn computer and external I/O device can be done through:

1) Programmed I/O (Data transfer under program control).

2) Interrupt-initiated I/O.
3) Direct memory access (DMA) transfer.
4) Transfer through an I/O processor (IOP).
1. Programmed I/O

Data transfer is initiated by an instruction in program.

Usually transfer is done betn CPU registers and peripherals.

Figure: Data transfer from I/O device to CPU

NOTE
(( In this method a constant monitoring of the peripheral by the CPU is required))
The transfer of data from I/O device to the interface is as follows:
1) When data is available, the device places it in the I/O bus and enables its
data valid line.
2) The interface accepts data place it in data register and enable the data accepted line.
3) The interface sets a bit in the status register.
4) The device disables the data valid line, but it will not transfer any data until data
accepted is disabled by the interface.
A flowchart of the program must be written for the CPU is shown below:
Therefore, the transfer of each byte require three instructions:
1) Read the status reg.
2) Check the status of the flag bit.
3) Read the data register.

DISADVANTAGES

Used in Slow computers, small monitoring system is required…..

Different in data rate make it inefficient……
2) Interrupt-initiated I/O

Device
Interface
 Interface

Device

Interface keeps monitoring the device & when device is ready it (interface)
will send Interrupt to CPU
WHAT is the difference betn interrupt initiated data & transfer under program control?

Release the CPU from continuous monitoring & allow it (CPU) to do another work.
 There are 2 interrupts method to chose the branch address

Vectored interrupt Non-vectored interrupt

(source (i.e. device) send the location) (assigned to a Fixed location in M.)
Priority Interrupt

Dev1

Computer Dev2
(CPU)

Dev3

Identify the source

of interrupt

Therefore, WE need interrupt system to

Decide which device
To serve first
 Priority Interrupt can be done in

H/W S/W
Polling ((TEST the devices in sequence
Serial From the high to low priority))
Parallel
(Daisy
chain)
 Polling Procedure (S/W)

INT 1 Service
Dev1 Routine 1

Service
INT 2 Routine
Dev2 Service
(check the Routine 2
INT Sources
in sequence)
INT 3
Service
Dev3 Routine 3
 H/W priority-interrupt unit

Dev1 Computer

H/W
determine INT Request Service
Dev2 which device Routine 1
has the highest
priority
Service
Routine 2
Dev3
Service
Routine 3
 Daisy-Chain priority

Highest priority Common for all devices

Internal Logic
 The second type in H/W is parallel priority interrupt

Priority is established according

To the position of bits in register

To control the status of each

interrupt request
Note: Interrupt register bits are set by external conditions & cleared
by program instructions
 CPU
3. DMA

Memory Magnetic Disk

 Memory Magnetic Disk

DMA

HERE:
•CPU is IDLE (i.e. has no control).
• while DMA controller takes over the buses to manage the transfer directly
Betn the I/O devices & memory.
 HOW we can make the CPU idle

Bus Request BR Dbus Data Bus

Abus Address Bus High impedance

(disable)
CPU when
Bus Grant BG RD BG is enable
Read
(i.e. BG = 1)

WR Write

CPU bus signals for DMA transfer mode

1. DMA send signal to CPU through activating BR.
2. The CPU send Ack. to DMA & release the control on buses to be under DMA
Control. Through sending BG signal.
3.

BG

idle
CPU

4. When the DMA finish the data transfer then the DMA disables the BR signal.
5. After that CPU disable BG & take the control.
 Transfer using DMA

(Cycle stealing)
Move entire block of Transfer one data word
Memory words At a time
(burst transfer) (CPU delay its operation
Therefore, need To allow the DMA to “steal”
Fast devices One memory cycle)
4- Input-output Processor (IOP)

interface keyboard

C
P interface printer
U
interface scanner
 CPU

PD PD PD PD
Memory Unit

IOP

Block diagram of a computer with I/O processor

 WHAT are the differences betn the DMA controller and the IOP?

DMA controller must be setup by the CPU while, IOP can fetch and execute
Its own instructions, and can perform another tasks such as arithmetic, logic
………..