0% found this document useful (0 votes)
38 views28 pagesLec3 Part2
Uploaded by
zkd9n8f6kfCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
38 views28 pagesLec3 Part2
Uploaded by
zkd9n8f6kfCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 28
‘Timing and Control
~ Timing forall revisters in basic computer is controlled by & master elock generator
~The clock pulses are applied to all ffs & cegisters in the system,
- The clock pulses don’t change the stute of a register unless the register is enabled by
a control signal.
= The control signals are generated in the CONTROL UNIT and provide control
‘npuls for the multiplexers in the common bus, control inputs in processor registers,
and microoperations for the aocumulator.
‘There are two major types of control organization:
Hardwired Control
> Mieroprugrammed Control
Hardwired Conrot Microprogrammed Conirol
The control logic is implemented with The control information is stored ma
gates, Hlip-flops, decoders, and other digital control memory (i. the control memory is
sitevits Programmed ‘to initiate the required
i, sequence of microoperations)
Tr hes the advantages that it can be Need to tad information from memory,
optimized to produce a fast mode of therefore, itis slower than hardwired.
_operation..
Required changes in the wiring among the Any required changes ean be done by
various components if the design has fo be updating the microprogrim in control
moditied or changed. memory Instruction rexbter
Other
aps
3x8
decoder
76543210
Control
Logie
ae
Increment (INR)
Clear CLD
eloek
bie
Sequence
Cooter (SC)
Figure (_)i control unit ef txisie computer,
Example:
DTy8C EO
Couns
‘gps
Sequenes counter (SC) responds to the positive sransition of the clock, Initially, the
CTR input of SC is setive, The First positive transition of the clock clears SC to 0,
which in urn activates the timing signal To, = The timing signals are generated only when
STOPS & the computer HALT,
~ SC increments every positive clock iminsition unless its CLR input is cetive
‘when $=0, the control sequence
Instruction Cycle
Figure ( ): Txample of contol timing sgeals
SC is cleered when DsT)= 1
When T, is active, the output of AND gate thet implements the comrol function DT,
becomes active, Example;
Te ARE PC
Dusing this time:
Bus © PC (
1 Sa) & LD input to AR
Ai the same positive clock SC SC 41
To$28) $) LD? AR € PC, SC © SC +1
Instruetion Cyele
A program residing in the memory unit of the computer coasists of a sequence of
instmetions. While the program is exceuted in the compuler by going throuah a cycle
Jor each instruction,
Fach jnstmction cycle subdivided into a seuuenee of subeyeles or phases:
1. FETCH an instruction trem memory.
2- DECODE the inscruction
3+ Readl the KERECTIVE address from the memory if the instruction hus indirect
address,
EXECUTE the ins:ruction,
Fetch and Decode
+ Initially, PC is Toadcd with the address of the fint instruction in the program,
Sequence counter is eleared to 0, providing a decoded timixg signal Ty
LD: PC © address of 1" instruction in the program, SC-€0
The microoperations for de FETCH and DECODE phases cen be specified by the
following register ceansfer statements
To AR © PC
TeiR © MIAR). PC} PC +1
Ta Da, ....Dy € Decode IR (12-14}, AR € TR (0-11, © IR (15) NOTE; since only AT is connected un te aubltess pubs oF rwerory, its aecessiny 9 “afer the aldeess
Sum PC to AR. While the insteustica saul fieem memory i then plac in IR
ee ee
Mery a
“aires
cn,
a a
a
Figure (_ ): Register iransfor tor the Petch phese.
+ to provide the data path for the transfer of PC to AR we must apply liming signal T;,
to achieve the following connection
“1. Place the content of PC on bus by making 38:8 010
2. Transfer the content. of bus to AR by enabling LT input of AR
aT
1. Enable the road input of momory. 2. Place the content of memory on bus Dy making S28)S9 = 11
3. ‘Transfer the content of bus to IR by ensbling LD input cf IR.
4. Increment PC by enabling INR input ot PC.
Determine the type of instruction
During Ts, the control unit determines the type of instruction.
The flowchart below shows how she control detesmines the instruction type aller the
decoding:
san
eM lan, PEEP
‘Dovode operlcn coee in/K (1213)
ARE RO-11), 18405)
(Regis eV) é 0. (Nemory reference)
£0 oyster) need) =1 A #0 (ree)
U
2» rs ta z
Frente we [ae ar Nai
ingore une tenes u we
Ceo Stet {
enor tte
‘ston
seed
Figure (_}; Mowchart for instnction eycle {initiel configuration), ~ TD; =O and I= 1, we have @ memory reference instruction with indirect address, I
i necessary then to read tne effective addiess from memory
~ The microoperation for the indirect ecldress cordition can be symbolized by the
register transfer siatement.
AR € MIAR]
- The three instruction types are subdivided into four separate paths, ‘lhe selected
operation is activated with the clock transition associated with timing signal ‘Ts, this
can be symbolized as follows:
Dil Ts: AR € M[AR]
‘Dil Ts: Nothing
DAT,
ecute a register reference iastruction
1D U5 | Execute an input-output instruction,
Register Reference Instructions
= ‘These instructions use bit O through 11 of tae instcuction code fo specify one of 12
register reference instructions
~ All these instructions are executed with the clock t
variable Ts,
ition associated with timing
~ Each control finetion needs Boolean relation DsT Ty =r.
~ By assigning the symbol Bj to bit i of IR,
able}: exee
ion of register-rolucence instructions
[cormmen to
Te (i) = Bi) [bitin TR (O-11) thar specifies the operation)
[Symbol | Microoperstion Desert
[r:sC€0 ~ [Glew SC
A [By AC EO - ec |
Bick © 0 “Clear —
1By; AC € AC Complement AC
Bike a Complement =
| By! AC € sir AC. ACUI) EEE ACO) Grout rahe]
1B: AG © shl AG Cis
CO EER EAC ING [iB AC EAC +I Tenement AC
SPA ry /IF (AC(U5) =0) THEN (PC © PC + I Ski pouive |
YTHEN (PC € PC +1) Skip i negate
0) THEN (&C & PC 1) [SEB ITAC zero |
THEN PC € PC = 1) Skip f= zero
BLT | rBy:S €0 Gis a start-stop fit) [Hat earopater
= The ELT insiruction clears a stert-stop flip/flop $ and stops the sequence counter
from counting. To restore the operation of the competes, the starl-sLop lil’ must be set
mannally
Memory-Reference Instructions
+ ‘The effective address is stored in AR.
= The execution of the memory-reference instructions starts with timing signal Ty,
Table ( ): Memory-r
Symbol | Operation Symbolic description
a decoder
[AND [ns AC © AGA MART
[app [ ACE AC + MIAR] ES
LDA [Ds “ACE MAR]
STA_[Ds MAR] € AC
BUN Dy Poe AR -
BSA [Ds MIAR] © PC,PO © AR+L
182 Ds MAR] © MIAR}+1
IF (MAR) +1) =0) THENPC € PC+1
Notes
1. The actual execution of the Memory Reference Instruction in the bus system will
require &
not be pro
quence of
microoperations. This is because data stored in memory can
essed dineily,
2 Data must be read from memory to a register where they can be operated on
with logic cirenits AND w AC
‘The microoperations that execute (bis instruction ares
DyTa: DR € MAR]
TyTs: AC © AC ADR, SC € 0
ADD oAC
DiTy: DR € M[AR]
DiTs: AC © AC+ DR,B© Com SCE O
LDA: load to AC
This instrvctio
‘anisfers the memory werd specifies by the effective address to AC,
DrT,: DR € M[AR]
D:Ts: AC © DR, SCO
Note that
1+ There is NO DIRECT path from tae BUS to AC.
2- Tue reason for not connecting the bus t9 the inputs of AC is the delay encountered
in the adder & logic circuit. 11s assumed thal the time it takes to read from memory
& nimsfer the word through the bus a6 well as the adder & logic cirouit is move thaw
the time of one clock cycle,
‘+ By not connecting the bus to AC we can maintain one clock cycle per
microoperation,
This instruction stores the content of AC into memory word specivied by
address,
effective
Dsl MIAR] © AC, SC € 0
BUN: Rranch Unconditignally
This insteuction transfers the program to the instruction specified by the effective
address, The BUN instruction allows the pmgrammer 10 specify an instruction out of sequence,
DT FOE ARSC EO
BSA: Branch and Saye return address
‘This instruction is useful for branching to # portion of the program ealled a subroutine or
procedure
This operation was specified with reuister transfer; MIAR] © PC, PC & AR 41
Example that demonstrates how this instruction is used with subroutine is shown below:
Memery Memory
oBSA 35, 0[-o Bsa iss
‘Neztinsiretion a Net instnstion
an 135 155 2
136 Subroutine PC a136 Subrouine
|
1 BUN as 1 BUN BS
(a) Memory, PC. and AR atime Ty (0) Memory and PC aftr execution
NOTE that
The BSA instruction must be executed with a sequence of two microoperations
D314: MIAR] € PC, AR € AR +L
Dts PC © AR, SC EO 182: Increment and Skip
The programmer usually stores @ negative numbers in the fom of (2's complement) in
the memory word. As this negative no, is repeatedly incremented by one, it eventually
reaches 10 Zero,
DjTy: DR © MAR]
DjTs DR € DR +1
DsTe MLAR] € DR, IF (DR=0) THEN (PC EPC 41, SC € 0
ISZ instruction inerements the word specified hy the effective adéress,
Control Mowehart,
NOTES:
1+ We need ONLY seven timing signals to execute the longest instruction i.e, 18Z),
‘Therefore, the computer can be designed with a 3-bic sequence counter (SC).
2- The reason for using at 4-bit eoumter for SC ts (o provide additional timing signals for
‘over iustruetions, DiTy DTs | Dy
Biitin| [Tonewiwns | [Corcae | [ava
ce
[on on Lon
sent | aac
meg | ER
seo
vat
er
igure (__); Flowchart for Memory Rek
IoK=0,
thes POE Be 4)
sceo
rence Instructions Input-Output Interrupt
~ A computer can serve no useful purpose unless :t communicates: with external
environment,
- Instructions and data stored in memory must come fiom some input device (i.
keyboard).
= Com:
fiqnal_resulis must be transmitted to the user through some outpat devices
(ie, monitor, printer),
Input-Output Configuration
~The terminal sends & receives serial information. Bach quantity of information has
eight bite of am alphanumeric code
~ The serial infonnation from the keyboard is shifted into the inpul register INPR.
‘The sesial information for the printer iy stored Ie the output register OLR,
~ These TWO registers (NPR, OUTR) communicate with a communic
ly ual with the AC in parallel
Inpet— sunyur seca Sonpuue
ened omuaieaon sayeth
notes Tiptore
esebee
Pier a our
Hignre (_); Input-Ontput Configuration + _INPR register consists of eight bits and hold:
- The |
lable in the input device and is cleared to 0
aiphanumeris input information,
flag FGI is a control ff the flag bit és
to 1 whoa new information is
en the in
vnation is accepted by
the computer.
‘he flag is needed to synchronize the timing rate differeace between the input
device and the vomputer,
The process of information transfer is as follows
INPR register
+ Initially, FGLis cleared (00 © (GLE 0)
~ When a key is struck in die Keyboard, an 8-bit elphanumenic code is shifted into INPR
and the FGT sel to |
INPRESbit, FGLEI
As long os FGLis set, the information can noi be changed hy strucking anorher key.
~The computer checks the flag bit, tf itis 1, the information from INPR is transferred
inpwallel into AC & FG is cleared to 0
IF (PGI=1) THEN AC EINPR, FGI 0
NOLE: onee the flag f cleared, new tnformation can be shifted to INPR.
OUTR register
+ Initially, FGO is set to 1
= The computer checks the flag bi
parallel to OU'TR & FGO is cleared 10,
IP GO = 1) THENOUTR © AC, FGO € 0
if itis 1, the information ‘rom AC is transfered in ~The outpu devive accepts the coded information prints the corresponding character
nd when the operation is complet, it sat FGO jo |
+ ‘The computer does not load a new chsracter into OTR when KGO is 0 because this
condition indicates that the output device is in the process of printing the character:
Input-Output Instruction
YO instructions are needed for
{- Transferring information tofand from AC register,
2 Cheelsing the Mlag bits.
3+ Controlling the interrupt facility.
= HO inscructions have an operation code 1111 & recognized by the control when D> =
le
D:ITs = p (common to all input-ontput instructions)
IR(i) = B, [bit in IR(6-11) that specifies the instruction]
pi SCH-0 Clear SC
INP pBn: AC(0-7)-INPR, FGI<0 Input character
QUT pB»o: OUTR+AC(0-7), FGO—0 Output character
SKI pBs:_ If (FGI = 1) then(PC—PC +1) — Skip on input flag
SKO — pBsi_If(FGO = 1) then (PC—PC +1) Skip on output flag
ION pBy; IEN<1 Interrupt enable on
IOF —pBe:_ EN Interrupt enable off
NOTR: tho above lust:
ss are exeented vith the stock ransition aasuciated with timing signal Program Interrupt
+ Programmed control transfer process: the computer keeps chockinur the flag bit, and
‘when il finds it set, it initiates an information transt
+ ‘The difference of information flow rate between the compurer & that o° VO device
makes this type of transfer inefficient,
~ An altemative to the pregtammed control prececture is to let the extemal device
inform the computer when it is ready for che transfer in meantime the compuler cam
be busy with other tasks. This type of transfer uses the intercupl facility
Interrupt Facility
~ While the computer is runaing a program, it does not check the flags.
- However. when a fla is sel, the computer ig momentarily imerrupted [rom
proceeding with current program,
TED
Interrupt Enable flip/flop
= When IEN is cleured to 0 (with IOF instcuction). The ‘lags canet interrupt the
‘computer
~ When IEN is set to 1 (vith ION instruction), The computer ean be interrupted
- GON & TOP) instuctions provice the programmer with the capability of meking a
decision as to whether or roto use (ke interrupe facility
~ An interrupt ilip-tlop R is included in the computer, etd aa donde peer
inn Leas
I
so tion
igure (_): Flowchart of Internupt Cyele.
Interrupt Cycle
~ IC isa hardware implementation of a branch and save rea address uperation.
An example that shows what happens during che interrupt eyele is shown below,
Suppose that an interrupt occur anxl R is scl (0 1 while the ecintrol is executing the
instruction al addeess 255
Memes Memory
° o 256
BUN a0 rei [aus nize
g a)
program progam
L0 1110
v0. 40
pogrim pena
1 SW O 1 aun 0
(2) Before interop (t Aterinterupt eyele
Figure (): Demorstralion of the Interrupt Cycle ~The interrupt eyele is initiated after the last execute phase IF the interrupt fF R is,
equal to 1
- The R tif is set to 1 IF TEN = 1 and Bither FGT or FGO are equal to 1, This can
happen with any clock trensition except when timing signals Tp, T).or To are active,
= The condition for setting #7 R to 1 can be expressed with the following register
transfer statement:
ToT. Tp (LEN) (FGI + FGO): R € 1
Modified Fetch Cycle
= inatend of using only timing signals Ty, Ty, and Ta, we will AND tho thrse timing
signals with R so that the fetch & decoée pheses will be recognized from the control
functions:
RT) RT, RTs
the reason for this is that afler the instruction is exveuler SC cleared to 0, the control
‘will go through a fetch phase only if R = 0.
= Otherwise, if R = 1, the control goos through interrupt eyele.
RTo: AR € 0, TR © PC
RT: M[AR] © TR, PC &0
RT PC © PCH 1 TEN € 0, REO,
Note: the R [// may be sel at any time during the inchreot or exeoule phases (Le, duri
or Ty ...ee Flowchart of page 16), Complete Computer Description
Design of Basic Computer
~ the basic computer consists of the followirg hardware components:
Nevrns:
MOWAYNE
A memory unit with 4096 words of [6 biteach.
Nine registers: AR, PC, DR, AC, (R, TR, OUTR, INPR, SC.
Seven fifs: 1. $, E,R, IEN, PGI, EGO.
‘Two decoders: 4 3x8 operation decoder & 4x6 timing decoder
A 16-bit common bus.
Contrel logic gates,
Adder and logie ci
it connected lo the inpat of AC,
1. The ffs ean he cither a D or JK type.
2. ‘The coninion bus ca be constructed with sinteen Me multiplexers.
Control Logic Gates
- the inpets to this efreuit come from:
1
2
=
4,
5,
6
Two decoders,
Lt,
Bit O through 11 of IR.
Other ilps arc AC bi: 0 through 15 to check if AC = 0 und to detect the
sign bitin AC (15),
DR bits 0 through 15 to cheek if DR = 0.
The value of the seven fits
= the outputs of the control logie eiretit ate
bapre
Signals to control the ilps of the nine registers.
Signals to contol the read & waite inputs oF memory.
Signals to set, clear, or complement the f/f
Signals for $2, §,, and Spto select a register for the common bus.
Signals to control the AC aukder and Logie circuit Control of Registers and Memory
‘The control ips of the register are LD (load), INR (increment), and CLR (cleus)
Example: derive the gete structure assaciated with the control inputs of AR:
«t) Find all the statements that change the content of AR:
Ri: AREPC
Ri: ARC IROL)
‘DIT: AR € MTAR]
RTy AR €O
DsTy AR © AR=1
b) The control functions can be combined imo 3 Roclesn expressions.
LD(ARJER y+ R 1 4D
CLR (AR) = RT,
INR (AR) =Ds Ty
ATs
©) Draw the block diagram.
2 2
From bis | Tobe
tock
Figure ( ); Control gates associated with AR, Example: The memory read operation is recognized fiom the Symbol © M[AR]
a) Find all che statements that initiste a read from memory:
RT: IR © MAR]
DBylTs: AR €MIAR]
Dit: AR © M[AR]
Diy: DR MAR]
DT): DR € MAR)
DyTs: DR € M[AR]
b) The control fanctions can be combined into one Boolean expression.
Read RT) +1 11+ (Dy +D, Ds 4 D9) Ta
¢) Draw the block diagram,
Memory Unit
4096 x 16,
ie Control of single Flip-flops
‘The control gates for the seven flip-flops can be determined in similar mana
Example: derive the gate structure associated to the IEN fl ip-Hop..
a) Find all the statements that change the value o7 LEN f/f
PBs: LEN © 1
PBe: IEN€ 0
RT2:EN€0
Where P=Dy TT)
>) The control funetions can be separated into SET & RESET to the TEN iit
PB; : wo! the IEN 1/f
PR, + Rp: eeset the IEN PF
6) Draw the block diagram
Dy
i
t
Control of the Common Bus
The binary number thut specifies S28; Sp is associnted with a Boolean variable x)
through x7, comesponding to the gate structure that must be active in order to select
register or memory for the bus ‘Table (_): Bneoder for Bus selection citeut
eee EEE
Tapuss Ourpus Register
selected
A eS Se for bus
‘None
AR
PC
DR
AC
IR
TR
Memory
eooconce
coorocc]
gsorecose
Hooooose
HoHOoHOHO
So= 1 + x3 +45 +m
St =X + ty + x5 + x,
Sz = xq + x5 + x + 27
‘To determine the logie for each encoder Jp, it neecssary t find the control fianctions that
places the conesponding register onto the commen bus,
To find the logic structure that makes xy = 1, extract the iransfer statement that have AR
DeTy:PC CAR
DsT3: PCE AR
Therefore, the Boolean furetion forx, is x)= Ds'Ty + Ds Ts Fxample: the data ofp from memory are selected whon x7 = 1, (de. 2 $1 So = 110
RT: IR MAR)
DIT: AR € M[AR}
DiTy: AR © MLAR]
DT: DR& MAR}
DT; DR € MAR]
DT: DR © MAR]
Therefor Ti+ Dr1 Ts 4On 4D + Ds 4D) Ts
In similar mariner we can determine the gate logic for the other registers
4} s:
g, Multiplexer bus
select inpats
Encoder Design of Accumulator
‘The circuit associated with AC register is shown in figure below:
1% Adler and Accumlter if
Fomor] ge FH egiser =I
4 eet acy Tob
Fron ver ee |
Jn order to design the logic associated with AC, il is novessary to extract all the statement
that change the content of AC.
Dit; AC-ACA DR
Dt ACAAC + DR
DiTs AC—DR
pBn: — AC(@7)-INPR
By AC AT
rBx AC app
a bE
n=
ine
[as
Figure ( ): Gate structure for controlling the LD, INR. and CTR of AC,
Bu
Adder and Logic Circuit
The aller and logic oireuit cam be subdivided into 16 stages, with each stage
corresponciing to oe bit of AC.
= one stage of the aukler and logic circuit consis off
1. Seven AND gates.
2. One OR gate
3. Full-alder (FA) Rw) _ Aco
i
(Oupur ofOR gate in Fig. 9-20)
LD
i
ig
weet js 9
| x =o Lol {|
ie
ao
Fom ——f
INR.
bie
Clock
in
acd) =e
{ )}—
ACti-1)
Figure ( ¥: One stage of adler & logic circuit. ‘Table ( ): Control functions ané Microoperations for the basic computer
es
Fetch RT akepe
RT IRAUAR, PCP +1
Decode RIT Dy sn, Die Decode IR(2-14),
ARCIRO1), FiR(5)
Inaieect DYTy ARMIAR]
Tnterugt
TARTMEN)RC! + GO) R—-1
2Ts ARWO, TRAPC
RT; MARTE, PCXO
Rl PC@PC#), IEN~0, RED, SCHOO
Memory-eterence
‘AND DiTy DR MIAR)
Die ACHACADR, sCHo
ADD. DiTe DReMAR)
Di: ACHAC+DR, EnCu, SCHO
LDA DT DRM(AR|
Die ACKDR, SCHO
sta. Die MlAR| HAC, SCH
BUN Dik PCwAR, 5C-0
BSA Die MAR|=PC, ARO AR 4:
Die PCHAR. 5C-0
sz Die DR-MIAR)
Die DRADR+1
Dae MIAR|
