Jeu d’instructions

LACC Load data memory value/long immediate, with left shift, to ACC
*Affecté par SXM
Direct: LACC dma [,shift ]
Indirect: LACC {ind} [,shift [,ARn ]
]
Long immediate: LACC #lk [,shift]

LACL Load data memory value/short immediate to ACCL; zero ACCH

*Non affecté par SXM
Direct: LACL dma
Indirect: LACL {ind} [,ARn]
Short immediate: LACL #k
LACT Load data memory value, with left shift specified by (4LSB)
TREG1, to ACC *Affecté par SXM (pour dénormaliser un nombre
Direct: LACT dma
Indirect: LACT {ind} [,ARn]
en virgule flottante)
SACL Store ACCL (low), with left shift, in data memory location *Non Direct: SACL dma [,shift2 ]
affecté par SXM Indirect: SACL {ind}
[,shift2[,ARn ] ]
SACH Store ACCH (hight), with left shift, in data memory location *Non Direct: SACH dma [,shift2 ]
affecté par SXM Indirect: SACH {ind}
[,shift2[,ARn ] ]
SATH Affecté par SXM, et n’affecte pas C (ACC) right-shifted by16 SATH ; pas d’opérande
(TREG1(4))
SATL Affecté par SXM, et n’affecte pas C (ACC) right-shifted by
TREG1(3-0)
SATL ;pas d’opérande

LACB The contents of the accumulator buffer (ACCB) are loaded into
the accumulator (ACC).
LACB ;pas d’opérande

SACB Store ACC in ACCB SACB ; pas d’opérande

EXAR Exchange ACCB with ACC EXAR ; pas d’opérande

CRGT Store ACC in ACCB if ACC > ACCB CRGT ; pas d’opérande

CRLT Store ACC in ACCB if ACC < ACCB CRLT ; pas d’opérande

LAMM Load contents of mem register to ACCL; zero ACCH, allows any
memory location on data memory page 0 to be loaded into the
Direct: LAMM dma
Indirect: LAMM {ind} [,ARn ]
ACC without modifying the DP bits.
SAMM The contents of the accumulator low byte (ACCL) are copied to
the addressed memory-mapped register.like LAMM
Direct: SAMM dma
Indirect: SAMM {ind} [,ARn ]

ZALR The contents of (dma) are loaded into (ACCH).with rounding;

(ACCL) are cleared, ACCL bit 15 is set.
Direct: ZALR dma
Indirect: ZALR {ind} [,ARn ]
ZAP Zero ACC and PREG ZAP ;pas d’opérande

ABS Absolute value of ACC;zero carry bit affected by OVM (affectsC ABS ;pas d’opérande
and OV)
CMPL 1s complement ACC CMPL ;pas d’opérande

NEG Negate (2s complement) ACC affected by OVM (affectsC and NEG ;pas d’opérande
OV)
NORM ACC bit 31 is exclusive-ORed (XOR) with ACC bit 30 to
determine if bit 30 is part of the magnitude or part of the sign
NORM{ind}

extension. If the bits are the same, then they are both sign bits,
and the ACC is shifted left to eliminate the extra sign bit. If the
result of the XOR operation is true, the TC bit is set; otherwise,
the TC bit is cleared. Affects: TC
ADD Add data memory value, with leftshift/Add short immediate/Add
long immediate, with left shift, to ACC,Affecté par OVM et SXM
Direct: ADD dma [,shift ]
Indirect: ADD {ind} [,shift ] [,ARn ]
(Direct, indirect ou Long immediate addressing),Affecté par Short immediate: ADD #k
Long immediate: ADD #lk [,shift]
OVM (Short immediate addressing),Affecte C et OV
ADDT Add data memory value, with left shift specified by the 4 LSBs
TREG1, to ACC Affected by: OVM, SXM, and TRM Affects: C
Direct: ADDT dma
Indirect: ADDT {ind} [,ARn ]
and OV
ADDS Add data memory value to ACC with sign extension suppressed
Affected by: OVM Affects: C and OV
Direct: ADDS dma
Indirect: ADDS {ind} [,ARn ]
ADDC Add data memory value and carry bit to ACC with sign extension
suppressed Affected by: OVM Affects: C and OV
Direct: ADDC dma
Indirect: ADDC {ind} [,ARn ]
ADDB Add ACCB to ACC Sans opérande

ADCB Add ACCB and carry bit to ACC Affecté par OVM; Affecte C et
OV
Sans opérande

SUB Subtract data memory value, with left shift/Subtract short

immediate/ Subtract long immediate, with left shift, from ACC
Direct: SUB dma [,shift ]
Indirect: SUB {ind} [,shift [,ARn ] ]
Short immediate: SUB #k
Long immediate: SUB #lk [,shift ]
SBB Subtract ACCB from ACC Sans opérande

SBBB Subtract ACCB and logical inversion of carry bit from ACC Sans opérande

SUBT Subtract data memory value, with left shift specified by TREG1,
from ACC c=1 si r=0 et c=0 sinon
Direct: SUBT dma
Indirect: SUBT {ind} [,ARn ]
SUBB Subtract data memory value and logical inversion of carry bit
from ACC with sign extension suppressed,same case for c as
Direct: SUBB dma
Indirect: SUBB {ind} [,ARn ]
before
SUBS Subtract data memory value from ACC with sign extension
suppressed
Direct: SUBS dma
Indirect: SUBS {ind} [,ARn ]
SUBC If (ACC) – ((dma) x2^15 )>= 0: (ALU output) x2 + 1->ACC
Else: (ACC) x2 -> ACC
Direct: SUBC dma
Indirect: SUBC {ind} [,ARn ]
AND AND data memory value withACCL; zero ACCH/AND long
immediate, with left shift, with ACC
Direct:AND dma
Indirect: AND {ind} [,ARn ]
Long immediate: AND #lk [,shift]
ANDB AND ACCB with ACC Sans opérande

OR OR data memory value with ACCL/OR long immediate, with left

shift, with ACC
Direct:OR dma
Indirect: OR {ind} [,ARn ]
Long immediate: OR #lk [,shift]
ORB OR ACCB with ACC Sans opérande

XOR Exclusive-OR data memoryvalue with ACCL/Exclusive-OR long

immediate, with left shift, with ACC
Direct: XOR dma
Indirect: XOR {ind} [,ARn ]
Long immediate: XOR #lk, [,shift ]
XORB Exclusive-OR ACCB with ACC Sans opérande

BSAR Barrel-shift ACC right BSAR shift

ROL Rotate ACC left 1 bit *pay attention to c Sans opérande

ROLB Rotate ACCB and ACC left 1 bit Sans opérande

ROR Rotate ACC right 1 bit Sans opérande

RORB Rotate ACCB and ACC right 1 bit Sans opérande

SFL Shift ACC left 1 bit Sans opérande

SFLB Shift ACCB and ACC left 1 bit Sans opérande

SFR Shift ACC right 1 bit Affecté par OVM Sans opérande

SFRB Shift ACCB and ACC right 1 bit 1 Sans opérande

MAR Indirect addressing:Modify current AR and ARP as specified

Direct addressing:Executes as a NOP
Direct: MAR dma
Indirect: MAR {ind} [,ARn ]
LAR Load data memory value/short immediate/long immediate to ARx Direct: LAR ARx, dma
Indirect: LAR ARx, {ind} [,ARn ]
Short immediate: LAR ARx, #k
Long immediate: LAR ARx, #lk
SAR Store ARx in data memory location Direct: SAR ARx, dma
Indirect: SAR ARx,{ind} [,ARn ]

LPH Load data memory value to PREG high byte Direct: LPH dma
Indirect: LPH {ind} [,ARn ]
SPM Set product shift mode (PM) bits SPM cte; avec cte entre 0 et 3

SPH Store PREG high byte, with shift specified by PM bits, in data
memory location
Direct: SPH dma
Indirect: SPH {ind} [,ARn ]
SPL Store PREG low byte, with shift specified by PM bits, in data
memory location
Direct: SPH dma
Indirect: SPH {ind} [,ARn ]
ZPR Zero PREG Sans opérande

PAC Load PREG, with shift specified by PM bits, to ACC Sans opérande

APAC Add PREG, with shift specified by PM bits, to ACC Sans opérande

SPAC Subtract PREG, with shift specified by PM bits, from ACC Sans opérande

DMOV Move data in data memory, The contents of the data memory
address (dma) are copied to the next higher dma.
Direct: DMOV dma
Indirect: DMOV {ind} [,ARn ]
LT Load data memory value to TREG0 Direct: LT dma
Indirect: LT {ind} [,ARn ]
LTP Load data memory value to TREG0; store PREG, with shift
specified by PM bits, in ACC *Affecte par PM&TRM
Direct: LTP dma
Indirect: LTP {ind} [,ARn ]
LTA Load data memory value to TREG0; add PREG, with shift
specified by PM bits, to ACC *Affected by: Affects:OVM, PM, and
Direct: LTA dma
Indirect: LTA {ind} [,ARn ]
TRM
LTS Load data memory value to TREG0; subtract PREG, with shift
specified by PM bits, from ACC
Direct: LTS dma
Indirect: LTS {ind} [,ARn ]
LTD Load data memory value to TREG0; add PREG, with shift
specified by PM bits, to ACC; and move data
Direct: LTD dma
Indirect: LTD {ind} [,ARn ]
MPY Multiply data memory value/ short immediate/ long immediate by
TREG0 and store result in PREG
Direct: MPY dma
Indirect: MPY {ind} [,ARn ]
Short immediate: MPY #k
Long immediate: MPY #lk
MPYU Multiply unsigned data memory value by TREG0 and store result
in PREG
Direct: MPYU dma
Indirect: MPYU {ind} [,ARn ]
MPYA Add PREG, with shift specified by PM bits, to ACC; multiply data
memory value by TREG0 and store result in PREG
Direct: MPYA dma
Indirect: MPYA {ind} [,ARn ]
MPYS Subtract PREG, with shift specified by PM bits, from ACC;
multiply data memory value by TREG0 and store result in PREG
Direct: MPYS dma
Indirect: MPYS {ind} [,ARn ]
SQRA Add PREG, with shift specified by PM bits, to ACC; load data
memory value to TREG0; square value and store result in PREG
Direct: SQRA dma
Indirect: SQRA {ind} [,ARn ]
SQRS Subtract PREG, with shift specified by PM bits, from ACC; load
data memory value to TREG0; square value and store result in
Direct: SQRS dma
Indirect: SQRS {ind} [,ARn ]
PREG

RPT Repeat next instruction specified by data memory value/short

immediate/long immediate; (dma) loaded into the repeat counter
Direct: RPT dma
Indirect: RPT {ind} [,ARn ]
register(RPTC) the NEXT instr is repeated n time n=RPTC+1 Short immediate: RPT #k
Long immediate: RPT #lk
RPTZ Clear ACC and PREG; repeat next instruction specified by long
immediate
RPTZ #lk

RPTB Repeat block of instructions specified by BRCR ;contrôlée par

registres (PASR, PAER, et BRCR) et un bit drapeau BRAF dans
RPTB pma

PMST.
MAC Add PREG, with shift specified by PM bits, to ACC; Load data Direct: MAC pma, dma
 memory value to TREG0;Multiply data memory value by program Indirect: MAC pma, {ind} [,ARn ]
memory value and store result in PREG

MACD Add PREG, with shift specified by PM bits, to ACC; Load data
memory value to TREG0; Multiply data memory value by
Direct: MACD pma, dma
Indirect: MACD pma, {ind} [,ARn ]
program memory value and store result in PREG;Move data for
on-chip RAM blocks only.
MADS Add PREG, with shift specified by PM bits, to ACC;Load data
memory value to TREG0; Multiply data memory value by value
Direct: MADS dma
Indirect: MADS {ind} [,ARn ]
specified in BMAR and Store result in PREG

MADD Add PREG, with shift specified by PM bits, to ACC; Load data
memory value to TREG0;Multiply data memory value by value
Direct: MADD dma
Indirect: MADD {ind} [,ARn ]
specified in BMAR and store result in PREG; and move data

BLDD block move from data to data(mem;mem with D @ long

imee;source in BMAR;dest in BMAR)
General syntax: BLDD src, dst

BLDP Block move from program to data memory with source address in
BMAR ;Block move from program to data memory with source
Direct: BLDP dma
Indirect: BLDP {ind} [,ARn ]
address long immediate

BLPD Block move from data to program memory with destination

address in BMAR
General syntax: BLPD src, dst

BANZ registre auxiliaire courant est un décrément de 1 BANZ pma [, {ind} [,ARn ] ]

BCND BCND pma, cond [,cond1 ] [,...]

DIRECTIVES
. set Permet de définir (initialiser) une constante.

.global déclare qu’un symbole est défini comme global,

.word défini une table de données en mémoire.

.copy/.includ lire les instructions à partir d’un autre fichier source avant de
continuer.
e

*During shifting, the low-order bits of the ACC are zero-filled. If the SXM bit is cleared, the
high-order bits of the ACC are zero-filled; if the SXM bit is set, the high-order bits of the ACC
are sign-extended.