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Unit-3Microprogram Sequencing

The document discusses micro-program sequencing and addressing. It describes how microinstructions are stored in control memory and executed to perform computer instructions. It outlines the components and functions of a microprogram sequencer, including a control address register, subroutine register, and multiplexers to select the next address.

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Tripti Gupta
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10 views

Unit-3Microprogram Sequencing

The document discusses micro-program sequencing and addressing. It describes how microinstructions are stored in control memory and executed to perform computer instructions. It outlines the components and functions of a microprogram sequencer, including a control address register, subroutine register, and multiplexers to select the next address.

Uploaded by

Tripti Gupta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Micro-programme Sequencing

Address Sequencing:
Microinstructions are stored in control memory in groups, with
each group specifying a routine.
Each computer instruction has its own microprogram routine in
control memory to generate the microoperations that execute the
instruction.
Steps that the control must undergo during the execution of a
single computer instruction:
 An initial address is loaded into the control address register
(CAR) when power is turned on in the computer.
 The address is usually the address of the first
microinstruction that activates the instruction fetch routine.
 The control unit must go through the routine that determines
the effective address of the operand.
 The next step is to generate the microinstructions that
execute the instruction fetched from the memory.
Transformation from the instruction code bits to an address in the
control memory where the routine is located is referred to as
mapping process.

Address sequencing capabilities required in a control memory are:


 Incrementing the CAR
 Unconditional branch or conditional branch, depending on
the status bit conditions.
 Mapping process from the bits of the instruction to an
address for control memory
 A facility for subroutine call or return

Microprogram Sequencer:
The next address generator is sometimes called a microprogram
sequencer, as it determines the address sequence that is read from
control memory.
The basic components of a microprogrammed control unit are:
 The control memory
 The circuits that select the next address called microprogram
sequencer
The purpose of a microprogram sequencer is to present an address
to the control memory so that a microinstruction may be read and
executed. The next-address logic of sequencer determines the
specific source to be loaded into the control address register
(CAR).
The choice of address source is guided by the next-address
information bits that the sequencer receives from the present
microinstruction.
A microinstruction contains:
 A set of bits to initiate micro-operations in control registers
 Other bits to specify the method by which the next address is
obtained.
Typical functions of a microprogram sequencer are:
 Incrementing the Control Address Register (CAR) by one
 Loading an address from the control memory into the Control
Address Register (CAR)
 Transferring an external address
 Loading an initial address to start the control operations
Block Diagram of microprogram sequencer:
The block diagram of the microprogram sequencer has shown in
the following figure.

Components of Microprogram Sequencer:


• MUX1
• MUX2
• Input Logic
• CAR
• SBR
Multiplexer1: (MUX1)
The first multiplexer selects address from one of the following four
sources and routes it into CAR.
 Incremented
 External
 from microinstruction
 SBR (SubRoutine Register)
The following table shows the selection of address source:
S1 S0 Selection
0 0 CARCAR+1
0 1 CARAD
1 0 CARSBR (return from
Subroutine)
1 1 CAR(2-5)DR(11-14),
CAR(0,1,6)0

The second multiplexer tests the value of a selected status bit and
the result of test is applied to input logic. CD field of
microinstruction selects one of the status bit in the second
multiplexer. The condition status bits are given in the following
table:
CD Condition Symbol
00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC=0 Z Zero value in AC

The output from the CAR provides the address for the control
memory.
Input logic design: The input logic block has three inputs I0, I1 and
T, and three outputs S0, S1, and L. Variable S0 and S1 select one of
the source addresses for CAR. Variable L enables the load input in
SBR.
Input Logic equations:
S1= I1
S0= I1.I0+I1’ T
L= I1’I0T

The truth table for input logic has been shown below. The values of
BR field will provide the input to input logic block. Now the values
of I0, I1 and T will be calculated according to three equations:
BR input MUX 1 Load Function
Field SBR
I1 I0 T S1 S0 L
0 0 JMP 0 0 0 0 0 0 CARCAR+1
0 0 JMP 0 0 1 0 1 0 CARAD
0 1 CALL 0 1 0 0 0 0 CARCAR+1
0 1 CALL 0 1 1 0 1 1 CARAD,
SBRCAR+1
1 0 RET 1 0 X 1 0 0 CARSBR
(return from
Subroutine)
1 1 MAP 1 1 x 1 1 0 CAR(2-
5)DR(11-14),
CAR(0,1,6)0

The values of S0, S1 will decide “From which address source the
content of CAR will be updated”.

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