EEE1036 : Digital Logic Design

Trimester 3 2022/2023

Chapter 3

Algebraic Methods for the

Analysis and Synthesis of
Logic Circuits
 Scopes

● Form the Boolean expression from logic circuit.

● Draw the logic circuit from Boolean expression.
● Construct the truth table from Boolean expression or
logic circuit.
● Form the Boolean expression from truth table using
minterm or maxterm.
● Evaluate the output using Boolean expression or truth
table.
● Simplify the Boolean expression using Boolean Algebra.
● Convert the logic circuit using NAND/NOR logic gates.
Boolean Constants and Variables

● Boolean variable is a quantity that may be equal to either 0 or 1 at

different times.
● Boolean variables represents the voltage level on a wire or at the
input/output terminals of a circuit (in terms of either 0 or 1)
● For example, in a certain digital system the Boolean value of 0 might be
assigned to any voltage in the range from 0 to 0.8 V while the Boolean
value of 1 might be assigned to any voltage in the range from 2 to 5 V
(Note, voltages between the 0.8 and 2 V are undefined).
● Boolean variables represent only the state of a voltage variable in terms
of 0 and 1, called the logic level.
 Boolean Constants and Variables

● Different terms used to represent logic 0 and logic 1

Truth Tables

● Truth table is a logical description of a logic circuit's operation (i.e.,

resultant output for different input combination).

Truth table of
three different
circuit …..
Truth Tables

● Truth tables list all possible input combinations and the corresponding
output level.
● The number of input combination depends on the number of inputs.
● The no. of input combinations will be equal to 2N for an N-input truth
table. For instance, for a 5-input truth table, the input combinations will
be 25 = 32.

No. of output = 2N
Logic Operation : OR

● OR operation truth table and circuit symbol:

● The Boolean expression for the OR operation is “ + ”

● Note :
Output f is at logic 1 when at least one of the inputs (of the input
combination) is at logic 1.
The output f is 0 when both the inputs are 0.
 OR Operation

3-input OR Operation Example (Tocci, pp. 63)

Logic Operation : AND

● AND operation truth table and circuit symbol:

● The Boolean expression for the AND operation is “∙ ”

AND operation
f = A∙ B symbol

● Note :
Output f is at logic 1 ONLY when all the inputs (of the input combination) is
at logic 1.
The output f is 0 for other input combinations.
 AND Operation

3-input AND Operation Example (Tocci, pp. 66)

a
f
b
c
Logic Operation : NOT

● NOT operation truth table and circuit symbol:

Presence of small circle denotes

inversion
NOT Operation

NOT Operation Example (Tocci, pp. 68)

Logic Operation : NOR

● NOR operation truth table:

● NOR circuit symbol:

NOR Operation

NOR Operation Example (Tocci, pp. 76)

a
f
b
Logic Operation : NAND

● NAND operation truth table :

● NAND circuit symbol -

NAND Operation

NAND Operation Example (Tocci, pp. 77)

a f
b
Logic Operation : XOR (Exclusive OR)

● XOR operation truth table and circuit symbol:

● The Boolean expression for the XOR operation is “ ⊕ ”

XOR Operation

XOR Operation Example

a
f
b
Logic Operation : XNOR (Exclusive NOR)

● XNOR operation truth table and circuit symbol:

A B
A
0 0 1

0 1 0
f
B
1 0 0

1 1 1 XNOR gate
Truth table Circuit symbol

● The Boolean expression for the XNOR operation is -

XNOR Operation

XNOR Operation Example

a
f
b
Waveforms for XOR gate and XNOR gate operation.
Drawing Logic Circuit

● When a Boolean expression is provided, we can

easily draw the logic circuit.
● Examples:
(i) F1 = xyz' (note the use of a 3-input AND gate)
x
y F1

z z'
Analysing Logic Circuit

● When a logic circuit is provided, we can analyse the

circuit to obtain the logic expression.
● Example: What is the Boolean expression of F4?

A' A'B'
B' A'B'+C (A'B'+C)'
F4
C

F4 = (A'B'+C)'
Analysing Logic Circuit

● Example: What is Boolean expression of F5?

x x.y
y F5 =(x.y+y.z)

z y.z
Analysing Logic Circuit

● Example: What is Boolean expression of x?

A
B x
C

D
Evaluating Logic Circuit output

From the Boolean expression:

● Consider we have a Boolean expression, we can evaluate the output
logic for different input variables. For example:
Boolean expression: Variable conditions:
A=0, B=1, C=1, D=1
Evaluating Logic Circuit output

From the logic circuit:

● We can evaluate the output logic for different input variables from
the logic circuit as well. For example:

1
A=0 1
B=1 x=
C= 0
1

D=1 1 0
Boolean expression:
Switching Algebra

● Basic “language” for combinational and sequential switching circuits

History:
● Boole (1854) developed “the science of logic” to “give expression . . . to
the fundamental laws of reasoning in the symbolic language of a
Calculus.”
● Huntington (1904) formally introduced an axiomatic definition (one of
several) of Boolean algebras. His axioms became known as the
Huntington postulates.
● Birkhoff (1940’s) discussed Boolean algebras in the context of lattice
theory
● Shannon (1938) developed the 2-valued algebra of switching (relay)
circuits and showed its relation to Boolean algebra
Boolean Algebra : Basic Postulates
(formulated by Huntington (1904))

Postulate # 1 : Formal Definition

● Boolean Algebra : An algebraic structure defined with a set of elements
B={0,1}, together with two binary operations {+} and {•} and a unary
operation {'}, and a number of unproved axioms.
● Symbolic variables such as X, Y, Z represent the elements. A variable can
take the value “0” or “1” which corresponds to the condition of a logic
signal.
● Base set B2 = {0, 1}
● Two binary operations: AND (•), OR (+)
● One unary operation: NOT or COMPLEMENT (’, ¯)

Postulate # 2 : Existence of 1 and 0 elements

● There exist unique elements 1 (one) and 0 (zero) in set B such that for
every a in B
(i) a + 0 = a (ii) a . 1 = a
Boolean Algebra : Basic Postulates

Postulate # 3 : Commutative laws

● The inputs of AND and OR gates can be interchanged
For every a and b in B
(i) a + b = b + a
(ii) a • b = b • a

Postulate # 4 : Associative laws

● The order of the input variables could be rearranged
For every a, b, c in B,
(i) a + (b + c) = (a + b) + c
(ii) a • (b • c) = (a • b) • c
Boolean Algebra : Basic Postulates

Postulate # 5 : Distributive law

● Multiplication distributes over addition
● Addition distributes over multiplication !!!
For every a, b, c in B
(i) a + (b • c) = (a + b) • (a + c)
(ii) a • (b + c) = (a • b) + (a • c)

Postulate # 6 : Complement
● For each a in B, there exists an element a’ in B (the complement of a)
such that
(i) a + a’ =1
(ii) a • a’ =0
Fundamental Theorems of Boolean Algebra
Duality Principle
● If a Boolean expression is valid in Boolean algebra, the dual of the
expression is also valid.
● Dual expression is derived from the original by replacing AND ( •)
operations by OR (+) operations and vice versa, and replacing constant
logic 0’s by logic 1’s and vice versa, while leaving the literals unchanged.

Example
1. Valid expression : a + (b • c) = (a + b) • (a + c)
Dual expression : a • (b + c) = (a • b) + (a • c)

2. Valid expression :X+0=X

Dual expression :X•1=X
Fundamental Theorems of Boolean Algebra
Theorem # 1 : Idempotency
(i) a + a = a
(ii) a . a = a

Proof
(i) a + a = (a + a) . 1 by postulate: P2(ii) a . 1 = a
= (a + a) . (a + a') P6(i) a +a’ =1
= (a + aa') P5(i) a + (b • c) = (a + b) • (a + c)
= (a + 0) P6(ii) a • a’ =0
=a P2(i) a + 0 = a
(ii) a . a = a . a + 0 by postulate: P2(i)
= a . a + a . a' P6(ii)
= a (a + a') P5(ii)
=a.1 P6(i)
=a P2(ii)
Fundamental Theorems of Boolean Algebra

Theorem # 2 : Null Elements

(i) a + 1 = 1
(ii) a . 0 = 0

Proof
(i) a + 1 = (a + 1) . 1 by postulate: P2(ii)
= 1 . (a + 1) P3(ii)
= (a + a') (a + 1) P6(i)
= a + a’ . 1 P5(i)
= a + a’ P2(ii)
=1 P6(i)

(ii) a . 0 = 0
as a + 1 = 1 is a valid expression, it’s dual that is, a . 0 = 0 is also valid
Fundamental Theorems of Boolean Algebra

Theorem # 3 : Involution

Proof
From postulate 6, a + a’=1 and a.a’=0, which defines the complements of a.
The complement of a’ is a and is also (a’)’. Since the complement is unique,
therefore (a’)’ = a.
Fundamental Theorems of Boolean Algebra
Theorem # 4 : Absorption
(i) a + (a.b) = a
(ii) a . (a + b) = a

Proof
(i) a + a.b = a . 1 + ab by postulate: P2(ii)
= a(1 + b) P5(ii)
= a(b + 1) P3(i)
=a.1 by theorem: P2(i)
=a P2(ii)
(ii) a.(a+b) = a + ab by duality principle
= a.1 + ab P2(ii)
= a(1 + b) P5(ii)
=a.1 T2(i)
=a P2(ii)
Fundamental Theorems of Boolean Algebra

Theorem # 5
(i) a + a’b = a + b
(ii) a(a’ + b) = ab

Proof
(i) a + a’b = (a + a’) (a + b) P5(i)
= 1 . (a + b) P6(i)
= (a + b) . 1 P3(ii)
= (a + b) P2(ii)

(ii) a(a’ + b) = a.a’ + ab P5(ii)

= 0 + ab P6(ii)
= ab + 0 P3(i)
= ab P2(i)
Fundamental Theorems of Boolean Algebra

Theorem # 6
(i) ab + ab’ = a
(ii) (a + b)(a + b’) = a

Proof
(i) ab + ab’ = a (b + b’) P5(ii)
=a.1 P6(i)
=a P2(ii)

(ii) (a + b)(a + b’) = a. + bb’ P5(i)

=a+0 P6(ii)
=a P2(i)
Fundamental Theorems of Boolean Algebra

Theorem # 7
(i) ab + ab’c = ab + ac
(ii) (a+b)(a+b’+c) = (a+b)(a+c)

Proof
(i) ab + ab’c = a(b + b’c) P5(ii)
= a(b + c) T5(i)
= ab+ac P5(ii)
Fundamental Theorems of Boolean Algebra

Let’s try some questions

Q: Simplify the following expression
Fundamental Theorems of Boolean Algebra

Answer

Apply P6(ii)

Apply T2(ii)

Apply P2(i)
Fundamental Theorems of Boolean Algebra

Answer

Apply T1(ii)

Apply P6(i)

Apply P2(ii)
Fundamental Theorems of Boolean Algebra

Theorem # 8 : DeMorgan’s Theorem

Proof
(i) Let x = a+b and x’ = (a+b)’. By postulate 6, x.x’=0 and x+x’=1. If we can
prove that x.y = 0 and x+y = 1, then y = x’ because the complement of x is
unique. Therefore, we let y=a’b’ and test x . y and x + y.
x.y = (a+b) (a’b’) x+y = (a+b) + (a’b’)
= (a’b’) (a + b) P3(ii) = (b + a) + (a’b’) P3(i)
= (a’b’)a + (a’b’)b P5(i) = b + (a + a’b’) P4(i)
= (aa’)b’ + a’(b’b) P4(ii) = b + (a + b’) T5(i)
= 0.b’ + a’(b.b’) P6(ii), P3(ii) = (a + b’) + b P3(i)
= b’.0 + a’.0 P3(ii), P6(ii) = a + (b’ + b) P4(i)
=0+0 T2(ii) = a + (b + b’) P3(i)
=0 T2(i) =a+1 P6(i)
=1 T2(i)
Therefore, by the uniqueness of x’, y = x’, and therefore a’b’ = (a+b)’
Induction proof of DeMorgan’s Theorems

● Using perfect induction (complete truth table):

(X + Y)' = X' • Y' (X • Y)' = X' + Y'

NOR is equivalent to AND NAND is equivalent to OR
with inputs complemented with inputs complemented

X Y X' Y' (X + Y)' X' • Y' X Y X' Y' (X • Y)' X' + Y'
0 0 1 1 1 1 0 0 1 1 1 1
0 1 1 0 0 0 0 1 1 0 1 1
1 0 0 1 0 0 1 0 0 1 1 1
1 1 0 0 0 0 1 1 0 0 0 0
Fundamental Theorems of Boolean Algebra

Generalized form of DeMorgan’s theorem:

DeMorgan’s theorem establishes relationship between AND (•) and OR (+)

Fundamental Theorems of Boolean Algebra

Theorem # 9 : Consencus
(i) ab + bc + a’c = ab + a’c
(ii) (a+b)(b+c)(a’+c) = (a+b)(a’+c)

Proof
(i) ab + a’c + bc = ab + a’c + 1.bc P2(ii)
= ab + a’c + (a+a’)bc T6(i)
= ab + a’c + abc + a’bc P5(ii)
= (ab + abc) + (a’c + a’bc)
= ab + a’c T4(i)
Universal Gates: NAND and NOR

● AND/OR/NOT gates are sufficient for building any Boolean

functions.
● However, other gates are also used because:
(i) usefulness
(ii) economical on transistors
(iii) self-sufficient

NAND/NOR: economical, self-sufficient

XOR: useful (e.g. parity bit generation)
NAND Gate

● NAND gate is self-sufficient (can build any logic circuit with it).
● Can be used to implement AND/OR/NOT.
● Implementing an inverter (NOT) using NAND gate:

x x'

(x.x)' = x' (T1: idempotency)

NAND Gate

● Implementing AND using NAND gates:

(x.y)'
x
x.y ((xy)'(xy)')' = ((xy)')' idempotency
y = (xy) involution

● Implementing OR using NAND gates:

x'
x
x+y

y ((xx)'(yy)')' = (x'y')' idempotency

y' = x''+y'' DeMorgan
= x+y involution
NOR Gate

● NOR gate is also self-sufficient.

● Can be used to implement AND/OR/NOT.
● Implementing an inverter using NOR gate:

x x'

(x+x)' = x' (T1: idempotency)

NOR Gate

● Implementing AND using NOR gates:

x'
x ((x+x)'+(y+y)')'=(x'+y')' idempotency
x.y = x''.y'' DeMorgan
= x.y involution
y
y'

● Implementing OR using NOR gates:

(x+y)'
x
x+y
y
((x+y)'+(x+y)')' = ((x+y)')' idempotency
= (x+y) involution
Implementation using NAND gates

● Possible to implement any Boolean expression using NAND gates.

Procedure:
(i) Obtain Boolean expression:
e.g. F3 = xy'+x'z

(ii) Use DeMorgan theorem to obtain expression

using 2-level NAND gates

e.g. F3 = xy'+x'z
= (xy'+x'z) ' ' by involution
= ((xy')' . (x'z)')' DeMorgan
Implementation using NAND gates

F3 = ((xy')'.(x'z)') ' = xy' + x'z

x (xy')'
y'
F3 = ((xy')'.(x'z)')'
= xy' + x'z
x'
z (x'z)'
Implementation using NOR gates

((x’+y)’ + (x+z’)’)’
x' (x’+y)'
y
F6
(x’+y)’ + (x+z’)’
x
=xy’+x’z
z' (x+z’)'

F6 = xy'+x'z
= (x’+y)’ + (x+z’)’ DeMorgan
Positive & Negative Logic

● In logic gates, usually:

∙ H (high voltage, 5V) = 1
∙ L (low voltage, 0V) = 0
● This convention – positive logic.
● However, the reverse convention, negative logic possible:
∙ H (high voltage) = 0
∙ L (low voltage) = 1
● Depending on convention, same gate may denote different Boolean
function.
Positive & Negative Logic

● A signal that is set to logic 1 is said to be asserted, or active, or true.

● A signal that is set to logic 0 is said to be deasserted, or negated, or
false.
● Active-high signal names are usually written in uncomplemented form.

Active High:
Enable 0: Disabled
1: Enabled
● Active-low signal names are usually written in complemented form.

Active Low:
0: Enabled
Enable
1: Disabled
Positive & Negative Logic
Positive & Negative Logic
Positive & Negative Logic
Switching Functions

● Let the function f(x1, x2, x3…xn); where x1, x2, x3…xn are the Boolean
variables, each of which represents either the element 0 or 1.
● Therefore, the function f represents the value 0 or value 1 depending on
the set of values assigned to x1, x2, x3…xn.
● As there are n variables and each variable has two possible values (0, 1),
2n combinations are possible. Furthermore, there are two possible values
for the function f(x1, x2, x3…xn), which results different switching
functions of n variables.

x y 16 possible functions (F0–F15)

0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
1
1 00 0 0 X1 1 Y0 0 1 1 0 0 1 1 Y 0 not0 X 1
not
1
1X and Y X xor Y X=Y X nand Y
1 1 0 1 0 1 0 1 X 0or Y 1 0X nor1 Y 0 1 0 1 not0(X and Y)
1 not (X or Y)
Representation of Logic Functions

● Truth table is the unique signature of a Boolean function

● Many alternative gate realizations may have the same truth table
● Truth table has 2n rows, n is the number of variables
● Definitions :
- Literal : a variable or its complement
Example : x , y’
- n- variable minterm : product term with n literals
Example : x’.y.z

- n- variable maxterm : sum term with n literals

Example : x+y’+z
Algebraic Forms of Switching Functions

Minterms
● For a function of n variables, a product term in which each of the n
variables appears once is called a minterm.
Algebraic Forms of Switching Functions

Maxterms
● A maxterm is defined as an ORed sum of literals in which each variable
appears exactly once in either true or complemented form, but not both.
Algebraic Forms of Switching Functions:
Canonical Representation

●
Canonical Representation

(A) Sum-of-products (SOP) canonical forms

● Also known as disjunctive normal form
● Also known as minterm expansion
F = 001 011 101 110 111
F = A'B'C + A'BC + AB'C + ABC' +
ABC
A B C F F'
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
F' = A'B'C' + A'BC' + AB'C'
1 1 0 1 0
1 1 1 1 0
Canonical Representation

Sum-of-products (SOP) canonical form (cont’d)

● ANDed product of literals – input combination for which output is true
● Each variable appears exactly once, in true or inverted form (but not
both)

A B C minterms
F in canonical form:
0 0 0 A'B'C' m0
F(A, B, C) = Σm(1,3,5,6,7)
0 0 1 A'B'C m1
= m1 + m3 + m5 + m6 + m7
0 1 0 A'BC' m2
= A'B'C + A'BC + AB'C + ABC' + ABC
0 1 1 A'BCm3
1 0 0 AB'C' m4
canonical form ≠ minimal form
1 0 1 AB'Cm5
F(A, B, C) = A'B'C + A'BC + AB'C + ABC' + ABC
1 1 0 ABC'm6
= (A'B' + A'B + AB' + AB)C + ABC'
1 1 1 ABC m7
= ((A' + A)(B' + B))C + ABC'
short-hand notation for = C + ABC'
minterms of 3 variables = ABC' + C
= AB + C
Canonical Representation

(B) Product-of-sums (POS) canonical form

● Also known as conjunctive normal form
● Also known as maxterm expansion
F= 000 010 100
F = (A + B + C) (A + B' + C) (A' + B + C)

A B C F F'
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 0
F' = (A + B + C') (A + B' + C') (A' + B + C') (A' + B' + C) (A' + B' + C')
Canonical Representation

Product-of-sums (POS) canonical form (cont’d)

● ORed sum of literals – input combination for which output is false
● each variable appears exactly once, in true or inverted form (but not
both)
A B C maxterms F in canonical form:
0 0 0 A+B+C M0 F(A, B, C) = ΠM(0,2,4)
0 0 1 A+B+C' M1 = M0 • M2 • M4
0 1 0 A+B'+C M2 = (A + B + C) (A + B' + C) (A' + B + C)
0 1 1 A+B'+C' M3
1 0 0 A'+B+C M4 canonical form ≠ minimal form
1 0 1 A'+B+C' M5 F(A, B, C) = (A + B + C) (A + B' + C) (A' + B + C)
1 1 0 A'+B'+C M6 = (A + B + C) (A + B' + C)
1 1 1 A'+B'+C' M7 (A + B + C) (A' + B + C)
short-hand notation for = (A + C) (B + C)
maxterms of 3 variables
 Mapping between canonical forms

● Minterm to maxterm conversion

● Use maxterms whose indices do not appear in minterm expansion
● e.g., F(A,B,C) = Σm(1,3,5,6,7) = ΠM(0,2,4)
● Maxterm to minterm conversion
● Use minterms whose indices do not appear in maxterm expansion
● e.g., F(A,B,C) = ΠM(0,2,4) = Σm(1,3,5,6,7)
● Minterm expansion of F to minterm expansion of F‘ (complement of a
minterm)
● Use minterms whose indices do not appear e.g., F(A,B,C) =
Σm(1,3,5,6,7) F'(A,B,C) = Σm(0,2,4)
● Maxterm expansion of F to maxterm expansion of F‘(complement of a
minterm)
● Use maxterms whose indices do not appear
● e.g., F(A,B,C) = ΠM(0,2,4) F'(A,B,C) = ΠM(1,3,5,6,7)
Canonical Sum Implementation

● f = x’.y’.z + x’.y.z + x.y.z’

(x’.y’.z)

x
(x’.y.z)
y f

z
(x.y.z’)
Canonical Product Implementation

● f =(x+y+z).(x+y’+z).(x’+y+z).(x’+y+z’).(x’+y’+z’)

(x+y+z)

x (x+y’+z)

y
(x’+y’+z) f
z

(x’+y+z’)

(x’+y+z’)
Logic Function Simplification

● f = x’.y’.z + x’.y.z + x.y.z’

= x’(y’.z+y.z) + x.y.z’
= x’((y’+y).z) + x.y.z’
= x’(1.z) +x.y.z’
=x’.z+x.y.z’

(x’.z)
x

f
y (x.y.z’)

z
Derivation of Canonical Forms

Theorem # 10 : Shanon’s expansion theorem

(i) f(x1, x2, …. xn) = x1 . f(1, x2, …. xn) + x’1 . f(0, x2, …. xn)
(ii) f(x1, x2, …. xn) = [x1 + f(0, x2, …. xn)] [ x’1 + f(1, x2, …. xn)]

● Canonical SOP and POS forms of a function can be translated directly to

truth tables, and vice versa.
● A function expressed in non-canonical form can be converted to directly
its canonical SOP or POS form without deriving its truth table - can be
done simply by using the Shanon’s expansion theorem.
● Example:
Converting to Canonical Forms

Q: Convert the following into canonical SOP form

Converting to Canonical Forms
Converting to Canonical Forms
Incompletely Specified Functions

● A function may be required to contain certain minterms and omit others

(remaining minterms are optional).
● Optional minterms may be included in the logic design to simplify the
logic circuit.
● Optional minterms called don’t care minterms
● Optional maxterms called don’t care maxterms

Applications will be given in

later chapters…..
Analysis of Combinational Circuits

● Analysis process ⇒ Determination of the function performed by the

network.
● Options:
● Algebraic method
● Truth table method
● Timing diagram
Analysis of Combinational Circuits
Algebraic Method
● Switching algebra is used to manipulate the switching function.
Example : What is the simplified expression of the logic network?

a P1
b
P4

a' P2
c
f(a,b,c)
P3

b
c' Functionally
equivalent b
f(a,b,
c
c)
Analysis of Combinational Circuits

Example- Logic Function Simplification

● F = (A+C).((A.B)+C)
=A.(A.B+C)+C.(A.B+C)
= A.A.B+A.C+C.A.B+C.C
=A.B+A.C+A.B.C+C
= (A.B+A.B.C)+(A.C+C)
=(A.B.(1+C)+((A+1).C)
= A.B+C
● Equivalent implementation of the logic function F :

A (A.B)
F = A.B+C
B
C
Analysis of Combinational Circuits
Truth Table Method
● Switching expression is evaluated from the truth table.
● Example :

A B C (A.B) (A.B)+C (A+C) F

0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 0 0 0 0
0 1 1 0 1 1 1
1 0 0 0 0 1 0
1 0 1 0 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
Analysis of Combinational Circuits
Timing Diagram Analysis
● A sequence of values is applied to the inputs of logic circuit over a
period of time.
● Corresponding input-output relation and Propagation Delay can be
observed.
Example: Timing simulation for the function,
Combinational Logic Circuits

The relationship between Boolean expression, truth table and

logic circuit is as shown below:

• Boolean expression can be derived as minterm or

maxterm Boolean expression from truth table and
vice-versa
• Logic circuit can be drawn from Boolean expression and
vice versa
Drawing Logic Circuit from Boolean
expression

• If a logic function is defined by a Boolean expression, its

circuit diagram can be implemented directly from the
expression

• In general, there are three type of Boolean expression

i. Sum-of-products (SOP) expression
ii. Product-of-sums (POS) expression
iii. Miscellaneous (a mixture of basic logic functions)
AND-OR Networks

• These networks are directly drawn from sum-of-products

(SOP) expressions
• Consider the example below:

① Variables are inverted

② Variables are ANDed together to form product terms
③ Product terms are ORed together
 OR-AND Networks
• They are drawn directly from POS expressions
• Consider the following example

① Variables are inverted

② Variables are ORed together to form sum terms
③ Sum terms are ANDed together
 Other Types of Networks
• Consist of a mixture of various logic gates, such as
NOT, AND, OR, NAND, NOR, XOR, XNOR
• Example:
 Other Types of Networks
• Consider another example:
 Describing Logic Circuit Algebraically
• Similarly, if a logic circuit is given, we can derive its Boolean expression by
observing and combining the outputs of each logic gates
• Consider the AND-OR network below:
 Describing Logic Circuit Algebraically
Consider the
following
OR-AND network:

Consider the
following
logic circuit:
Describing Logic Circuit Algebraically

• Consider yet another circuit:

From Truth Table to Logic Circuit
• We can construct the logic circuit from its truth table
• This can be done by first obtaining the minterm/maxterm
Boolean expression from truth table
• Consider the following example:
From Truth Table to Logic Circuit

• Consider obtaining the maxterm Boolean expression

from the truth table below:
 Evaluating Logic Circuit Output
• We can determine the output of a particular logic circuit if its
Boolean expression is known
• This can be done by first obtaining the Boolean expression of
the logic circuit and convert it to SOP form
 Evaluating Logic Circuit Output

• Consider another logic circuit as shown below:

Evaluating Logic Circuit Output

• Consider yet another logic circuit as shown below:

Universality of NAND & NOR Gates

• All Boolean expressions consists of various combinations

of OR, AND and NOT
• Both NAND and NOR gates can be used to perform OR,
AND and NOT
• Thus, it is possible to implement any logic circuit by
using only NAND or NOR gates
Implementing AND-OR network with NAND
gates only

• AND-OR network can be directly implemented using

only NAND gates
• The procedures to convert AND-OR network to pure
NAND gates is based on DeMorgan’s Theorem
• Consider implementing the AND-OR network below by
using NAND gates only
Implementing AND-OR network with NAND
gates only

① Implement inverter using NAND gates

② Place a bubble at the output of each AND gates
③ Place a bubble at the input of the OR gate
④ If an input to OR gate is directly connected to input line,
place an inverter between them
⑤ Redraw the logic circuit by using NAND gates only
Implementing AND-OR network with NAND
gates only

• Alternative method:

1. Derive the Y output

2. Use De-Morgan to convert SOP to a form of all product
3. Redraw the logic circuit by using NAND gates only
based on the derived equation
Implementing OR-AND network with NOR
gates only

• Similarly, OR-AND networks can be implemented by

using NOR gates only
• Consider implementing the OR-AND network below by
using NOR gates only
Implementing OR-AND network with NOR
gates only

① Implement inverter using NOR gates

② Place a bubble at the output of each OR gates
③ Place a bubble at the input of the AND gate
④ If an input to AND gate is directly connected to input
line, place an inverter between them
⑤ Redraw the logic circuit by using NOR gates only
Implementing OR-AND network with NOR
gates only

• Alternative method:

1. Derive the Y output

2. Use De-Morgan to convert POS to a form of all sum
3. Redraw the logic circuit by using NOR gates only based
on the derived equation
Universality of NAND & NOR Gates

• The preceding 2 methods can only be applied to

AND-OR networks and OR-AND networks, respectively
• It is advisable to construct logic circuit using NAND or
NOR gates only by properly manipulating the Boolean
expression of the original logic circuit and application of
DeMorgan’s theorems
• Consider implement the following logic circuit using
NAND gates only:
Universality of NAND & NOR Gates

• Consider implement the following logic circuit by using

NOR gates only:
Universality of NAND & NOR Gates

• Example:
i. Implement the following Boolean expression by using
NAND gates only:

Solution:
Universality of NAND & NOR Gates

ii. Implement the following logic function by using

NOR gates only:

Solution:
Input and Output Waveforms

• We can plot the output waveform of a logic circuit with

respect to its inputs by referring to the truth table
• The procedures to derive the output waveform are:
i. Obtain the Boolean expression for the logic circuit
ii. Convert the Boolean expression to SOP form
iii. Based on the SOP expression, construct the truth table
iv. Referring to the truth table, draw the output waveform
corresponds to each input condition
Input and Output Waveforms

• Example:
Determine the output waveform if the inputs are varying
according to the timing diagram below:
Input and Output Waveforms
• Solution:
Input and Output Waveforms
• Example:
Determine the output waveform if the inputs are varying
according to the timing diagram below:
Input and Output Waveforms
Input and Output Waveforms
Appendix
Electronic Gates
Faults

Internal
• shorted inputs or outputs to ground or supply
• open circuited
• short between pins
External
• open signal lines
• shorted signal lines
• faulty power supply
• output loading
Propagation Delay

• Various physical phenomena, such as resistance and

capacitance, substantially reduce the speed at which signal
can travel in physical circuit
• If there is a change at the inputs, the output of a logic gate
will not change instantaneously.
• All the delays occur in a logic gate can be grouped into a
single average or nominal value, known as the
propagation delay
• Propagation delay is denoted as tpd
Propagation Delay

• Consider the NAND gate below:

• For ideal case, there is no propagation delay and the

output responds instantly to the changes of inputs
Propagation Delay

• If there is a propagation delay, the waveforms will become:

• The changes in output with respond to the change of

input is delayed, by tpd
• The output waveforms for both cases are the same, but
shifted to the right by tpd
Propagation Delay

• The propagation delay of various gates will introduce

glitches in the output waveform
• Consider the following example:
Postulates and Theorems of Boolean
Algebra

CHAPTER 3
Postulates/ Theorems OR Form (Addition) AND Form (Product)
Identity a+0=a a.1=a
Null/ dominance a+1=1 a.0=0
Idempotent a+a=a a.a=a
Complement/ inverse a + a’ = 1 a . a’ = 0
Involution/ double
complement
Commutative a+b=b+a a.b=b.a
Associative (a+b+c) = a + (b+c) = (a+b) + c (a.b.c) = a . (b.c) = (a.b) . c
Distributive a(b+c) = (ab) + (ac) a + (bc) = (a+b)(a+c)
Absorption/ covering a(a + b) = a a + (ab) = a
(Simplify)
Adsorption (Simplify) a(a’+b) = ab a + a’b = a + b
Combining/ uniting (Simplify) (a+b)(a+b’) = a ab + ab’ = a

ab + ab’c = ab + ac (a+b)(a+b’+c) = (a+b)(a+c)

Consensus (a+b)(b+c)(a’+c) = (a+b)(a’+c) ab + bc + a’c = ab + a’c
Multiplying and factoring (ab) + (a’c) = (a+c)(a’+b) (a+b)(a’+c) = (ac) + (a’b)

DeMorgan’s

Shanon’s expansion f(x1, x2, … xn) = x1 . f(1, x2, . xn) + x’1 . f(0, x2, … f(x1, x2, … xn) = [x1 + f(0, x2, … xn)] [ x’1 + f(1, x2,
xn) … xn)]
Other a ⊕ b = (ab’) + (a’b)