LTC4306

4-Channel,
2-Wire Bus Multiplexer with
Capacitance Buffering
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FEATURES DESCRIPTIO
■ 1:4 2-Wire Multiplexer/Switch The LTC®4306 is a 4-channel, 2-wire bus multiplexer with
■ Connect SDA and SCL Lines with 2-Wire Bus bus buffers to provide capacitive isolation between the
Commands upstream bus and downstream buses. Through software
■ Supply Independent Bidirectional Buffer for SDA control, the LTC4306 connects the upstream 2-wire bus to
and SCL Lines Increases Fan-Out any desired combination of downstream buses. Each
■ Programmable Disconnect from Stuck Bus channel can be pulled up to a supply voltage ranging from
■ Compatible with I2C and SMBus Standards 2.2V to 5.5V, independent of the LTC4306 supply voltage.
■ Rise Time Accelerator Circuitry The downstream channels are also provided with
■ SMBus Compatible ALERT Response Protocol ALERT1-ALERT4 inputs for fault reporting.
■ Two General Purpose Inputs-Outputs
Programmable timeout circuitry disconnects the down-
■ Prevents SDA and SCL Corruption During Live Board
stream buses if the bus is stuck low. When activated, rise
Insertion and Removal from Backplane
time accelerators source currents into the 2-wire bus pins
■ ±10kV Human Body Model ESD Ruggedness
to reduce rise time. Driving the ENABLE pin low restores
■ 24-Lead QFN (4mm × 5mm) and SSOP Packages
all features to their default states. Three address pins
U provide 27 distinct addresses.
APPLICATIO S
The LTC4306 is available in 24-lead QFN (4mm × 5mm)
■ Nested Addressing and SSOP packages.
■ 5V/3.3V Level Translator , LTC and LT are registered trademarks of Linear Technology Corporation.
■ Capacitance Buffer/Bus Extender All other trademarks are the property of their respective owners. Patent pending.

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TYPICAL APPLICATIO
A Level Shifting and Nested Addressing Application

2.5V 3.3V
I2C Bus Waveforms
0.01µF VCC = 3.3V
10k 10k 10k 10k 10k 10k
VCC VBACK = 2.5V
SCLIN
SCLIN SCL1 2V/DIV
MICRO- SFP
SDAIN SDA1
CONTROLLER MODULE 1
ALERT ALERT1
VCARD1 = 3.3V
ADDRESS = 1111 000 SCL1
2V/DIV
5V
LTC4306 •
•
• 10k 10k 10k
VCARD4 = 5V
ADR2 SCL4 SCL4
SFP
ADR1 SDA4 2V/DIV
MODULE 4
ADR0 ALERT4
GND ADDRESS = 1111 000 4306 TA01b
4306 TA01a 500ns/DIV
ADDRESS = 1000 100

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LTC4306
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ABSOLUTE AXI U RATI GS (Note 1)

Supply Voltage (VCC) ................................... –0.3V to 7V Operating Temperature Range

Input Voltages (ADR0, ADR1, ADR2, LTC4306C ............................................... 0°C to 70°C
ENABLE, ALERT1, ALERT2, ALERT3, LTC4306I ............................................. –40°C to 85°C
ALERT4) .................................................. –0.3V to 7V Storage Temperature Range
Output Voltages (ALERT, READY) ............... –0.3V to 7V SSOP ................................................. –65°C to 150°C
Input/Output Voltages (SDAIN, SCLIN, QFN ................................................... –65°C to 125°C
SCL1, SDA1, SCL2, SDA2, SCL3, Lead Temperature (Soldering, 10 sec)
SDA3, SCL4, SDA4, GPIO1, GPIO2) ........ –0.3V to 7V SSOP ................................................................ 300°C
Output Sink Currents (SDAIN, SCLIN, SCL1-4, SDA1-4,
GPI01-2, ALERT, READY) ..................................... 10mA

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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART TOP VIEW
ORDER PART
ALERT2

NUMBER NUMBER
SDA3

SDA2
SCL3

SCL2

SCL3 1 24 ALERT2
SDA3 2 23 SCL2
24 23 22 21 20 LTC4306CUFD ALERT 3 22 SDA2
LTC4306CGN
ALERT 1 19 ALERT3
SDAIN 2 18 ALERT1
LTC4306IUFD SDAIN 4 21 ALERT3
LTC4306IGN
GND 3 17 SDA1 GND 5 20 ALERT1
SCLIN 4 25 16 SCL1 SCLIN 6 19 SDA1
ENABLE 5 15 SCL4 ENABLE 7 18 SCL1
VCC 6 14 SDA4 VCC 8 17 SCL4
ALERT4 7 13 READY UF PART MARKING* ALERT4 9 16 SDA4
8 9 10 11 12
GPI01 10 15 READY
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GPIO1
GPI02
ADR0
ADR1
ADR2

GPI02 11 14 ADR2
UFD PACKAGE ADR0 12 13 ADR1
24-LEAD (4mm × 5mm) PLASTIC QFN
EXPOSED PAD (PIN 25), PCB CONNECTION OPTIONAL GN PACKAGE
MUST BE CONNECTED TO THE PCB TO OBTAIN 24-LEAD PLASTIC SSOP
θJA = 43°C/W OTHERWISE θJA = 140°C/W. TJMAX = 125°C TJMAX = 125°C, θJA = 85°C/W

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply/Start-Up
VCC Input Supply Range ● 2.7 5.5 V
ICC Input Supply Current Downstream Connected, SCL Bus Low, ● 5.2 8 mA
SDA Bus High, VCC = 5.5V
ICC ENABLE = 0V Input Supply Current VENABLE = 0V, VCC = 5.5V ● 1.25 2.5 mA
VUVLOU UVLO Upper Threshold Voltage ● 2.3 2.5 2.7 V

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 LTC4306
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VUVLOHYST UVLO Threshold Hysteresis Voltage ● 100 175 250 mV
VTH EN ENABLE Falling Threshold Voltage ● 0.8 1.0 1.2 V
VENHYST ENABLE Threshold Hysteresis Voltage 60 mV
tPHLEN ENABLE Delay, On-Off 60 ns
tPLHEN ENABLE Delay, Off-On 20 ns
IINEN ENABLE Input Leakage Current VENABLE = 0V, 5.5V, VCC = 5.5V ● 0 ±1 µA
VLOWREADY READY Pin Logic Low Output Voltage IPULL-UP = 3mA, VCC = 2.7V ● 0.18 0.4 V
IOFFREADY READY Off State Input Leakage Current VREADY = 0V, 5.5V, VCC = 5.5V ● 0 ±1 µA
Upstream-Downstream Buffers
VOS,BUF Buffer Offset Voltage RBUS = 10k, VCC = 2.7V, 5.5V (Note 4) ● 25 60 100 mV
VOS,UP-BUF Upstream Buffer Offset Voltage VCC = 2.7V, RBUS = 2.7k (Note 4) ● 40 80 120 mV
VIN, BUFFER = 0V VCC = 5.5V, RBUS = 2.7k (Note 4) ● 70 110 150 mV
VOS,DOWN-BUF Downstream Buffer Offset Voltage VCC = 2.7V, RBUS = 2.7k (Note 4) ● 60 110 160 mV
VIN, BUFFER = 0V VCC = 5.5V, RBUS = 2.7k (Note 4) ● 80 140 200 mV
VOL Output Low Voltage, VIN,BUFFER = 0V SDA, SCL Pins; ISINK = 4mA, ● 400 mV
VCC = 3V, 5.5V
Output Low Voltage, VIN,BUFFER = 0.2V SDA, SCL Pins; ISINK = 500µA, ● 320 mV
VCC = 2.7V, 5.5V
VIL,MAX Buffer Input Logic Low Voltage VCC = 2.7V, 5.5V ● 0.4 0.52 0.64 V
VTHSDA,SCL Downstream SDA, SCL Logic Threshold Voltage ● 0.8 1.0 1.2 V
ILEAK Input Leakage Current SDA, SCL Pins; VCC = 0V to 5.5V; ● 0 ±5 µA
Buffers Inactive
Rise Time Accelerators
VSDA,SCL slew Minimum Slew Requirement to Activate SDAIN, SCLIN, SDA1-4, SCL1-4 Pins ● 0.4 0.8 V/µs
Rise Time Accelerator Currents
VRISE,DC Rise Time Accelerator DC Threshold Voltage SDAIN, SCLIN, SDA1-4, SCL1-4 Pins ● 0.7 0.8 1 V
IBOOST Rise Time Accelerator Pull-Up Current SDAIN, SCLIN, SDA1-4, SCL1-4 Pins 4 5.5 mA
(Note 3)
GPIOs
VGPIO(TH) GPIO Pin Input Threshold ● 0.8 1 1.2 V
VGPIO(OL) GPIO Pin Output Low Voltage IGPIO = 5mA, VCC = 2.7V ● 0.2 0.4 V
VGPIO(OH) GPIO Pin Output High Voltage IGPIO = –200µA, VCC = 2.7V ● VCC – 0.3 V
IGPIO(IN) GPIO Pin Input Leakage Current VGPIO = 0V, 5.5V, VCC = 5.5V ● 0 ±1 µA
Stuck Low Timeout Circuitry
VTIMER(L) Stuck Low Falling Threshold Voltage VCC = 2.7V, 5.5V ● 0.4 0.52 0.64 V
VTIMER(HYST) Stuck Low Threshold Hysteresis Voltage 80 mV
TTIMER1 Timeout Time #1 TIMSET1,0 = 01 ● 25 30 35 ms
TTIMER2 Timeout Time #2 TIMSET1,0 = 10 ● 12.5 15 17.5 ms
TTIMER3 Timeout Time #3 TIMSET1,0 = 11 ● 6.25 7.5 8.75 ms
ALERT
VALERT(OL) ALERT Output Low Voltage IALERT = 3mA, VCC = 2.7V ● 0.2 0.4 V
IOFF,ALERT ALERT Off State Input Leakage Current VALERT = 0V, 5.5V ● 0 ±1 µA
IIN,ALERT1-4 ALERT1-ALERT4 Input Current VALERT1-4 = 0V, 5.5V ● 0 ±1 µA
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LTC4306
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VALERT1-4(IN) ALERT1-ALERT4 Pin Input Falling ● 0.8 1.0 1.2 V
Threshold Voltages
VALERT1-4(HY) ALERT1-ALERT4 Pin Input Threshold 80 mV
Hysteresis Voltages
I2C Interface
VADR(H) ADR0-2 Input High Voltage ● 0.75 • VCC 0.9 • VCC V
VADR(L) ADR0-2 Input Low Voltage ● 0.1 • VCC 0.25 • VCC V
IADR(IN, L) ADR0-2 Logic Low Input Current ADR0-2 = 0V, VCC = 5.5V ● –30 –60 –80 µA

IADR(FLOAT) ADRO-2 Allowed Input Current VCC = 2.7V, 5.5V (Note 5) ● ±5 ±13 µA
IADR(IN, H) ADR0-2 Logic High Input Current ADR0-2 = VCC = 5.5V ● 30 60 80 µA
VSDAIN,SCLIN(TH) SDAIN, SCLIN Input Falling Threshold VCC = 5.5V ● 1.4 1.6 1.8 V
Voltages
VSDAIN,SCLIN(HY) SDAIN, SCLIN Hysteresis 30 mV
ISDAIN,SCLIN(OH) SDAIN, SCLIN Input Current SCL, SDA = VCC ● 0 ±5 µA
CIN SDA, SCL Input Capacitance (Note 2) 6 pF
VSDAIN(OL) SDAIN Output Low Voltage ISDA = 4mA, VCC = 2.7V ● 0.2 0.4 V
I2C Interface Timing
fSCL Maximum SCL Clock Frequency (Note 2) 400 kHz
tBUF Bus Free Time Between Stop/Start Condition (Note 2) 0.75 1.3 µs
tHD,STA Hold Time After (Repeated) Start Condition (Note 2) 45 100 ns
tSU,STA Repeated Start Condition Set-up Time (Note 2) –30 0 ns
tSU,STO Stop Condition Set-up Time (Note 2) –30 0 ns
tHD,DATI Data Hold Time Input (Note 2) –25 0 ns
tHD,DATO Data Hold Time Output (Note 2) 300 600 900 ns
tSU,DAT Data Set-up Time (Note 2) 50 100 ns
tf SCL, SDA Fall Times (Note 2) 20 + 0.1 • 300 ns
CBUS
tSP Pulse Width of Spikes Suppressed by the (Note 2) 50 150 250 ns
Input Filter

Note 1: Absolute Maximum Ratings are those values beyond which the life to a voltage VLOW2 = VLOW + VOS, where VOS is a positive offset voltage.
of a device may be impaired. VOS,UP-BUF is the offset voltage when the LTC4306 is driving the upstream
Note 2: Guaranteed by design and not subject to test. pin (e.g., SDAIN) and VOS,DOWN-BUF is the offset voltage when the
Note 3: The boosted pull-up currents are regulated to prevent excessively LTC4306 is driving the downstream pin (e.g., SDA1). See the Typical
fast edges for light loads. See the Typical Performance Characteristics for Performance Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a
rise time as a function of VCC and parasitic bus capacitance CBUS and for function of VCC and bus pull-up current.
IBOOST as a function of VCC and temperature. Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage
Note 4: When a logic low voltage, VLOW, is forced on one side of the currents up to IADR(FLOAT) and still convert the address correctly.
Upstream-Downstream Buffers, the voltage on the other side is regulated

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 LTC4306
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TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise indicated)

Buffer Circuitry tPHL

vs Temperature Rise Time vs CBUS vs VCC ICC vs Temperature
120 250 6
dV = 0.3V • VCC TO 0.7V • VCC VCC = 5V
RBUS = 10k
100 5
200
VCC = 3.3V
VCC = 3.3V VCC = 3.3V
80 4

CURRENT (mA)
VCC = 5V

RISE TIME (ns)

VCC = 5V 150
tPHL (ns)

60 3

100
40 2

20 50 1
UPSTREAM CONNECTED TO CHANNEL 1,
SCL BUS LOW, SDA BUS HIGH
0 0 0
–50 –25 0 25 50 75 100 125 0 200 400 600 800 1000 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) CAPACITANCE, CBUS (pF) TEMPERATURE (°C)
4306 G01 4306 G02 4306 G03

VOS,DOWN-BUF
VOS,UP-BUF vs Bus Pull-Up Current vs Bus Pull-Up Current
180 300

160
250
140

120 200
VCC = 3.3V
VOS (mV)

VOS (mV)

100 VCC = 3.3V

VCC = 5V 150
80 VCC = 5V

60 100

40
50
20

0 0
0 1 2 3 4 0 1 2 3 4
BUS PULL-UP CURRENT (mA) BUS PULL-UP CURRENT (mA)
4306 G04 4306 G05

Downstream RFET On Resistance

vs VCC and Temperature IBOOST vs Temperature
45 14
40
12
35
10
30 VCC = 5V
VCC = 3.3V
IBOOST (mA)
RON (Ω)

25 8
VCC = 5V
20 6
VCC = 3.3V
15
4
10

5 2

0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
4306 G06 4306 G07

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LTC4306
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PI FU CTIO S (GN24 Package/UFD24 Package)
ALERT (Pin 3/Pin 1): Fault Alert Output. An open-drain ADR0-ADR2 (Pins 12, 13, 14/Pins 10, 11, 12): Three-
output that is pulled low when a fault occurs to alert the State Serial Bus Address Inputs. Each pin may be floated,
host controller. The LTC4306 pulls ALERT low when any tied to ground or tied to VCC. There are therefore 27
of the ALERT1-ALERT4 pins is low, when the 2-wire bus possible addresses. See Table 1 in applications informa-
is stuck low, or when the Connection Requirement bit of tion. When the pins are floated, they can tolerate ±5µA of
Register 2 is low and a master tries to connect to a leakage current and still convert the address correctly.
downstream channel that is low. See Operation section for
READY (Pin 15/Pin 13): Connection Ready Digital Output.
the details of how ALERT is set and cleared. The LTC4306
An N-channel MOSFET open-drain output transistor that
is compatible with the SMBus Alert Response Address
pulls down when none of the downstream channels is
protocol. Connect a 10k resistor to a power supply voltage
connected to the upstream bus and turns off when one or
to provide the pull-up. Tie to ground if unused.
more downstream channels is connected to the upstream
SDAIN (Pin 4/Pin 2): Serial Bus Data Input and Output. bus. Connect a 10k resistor to a power supply voltage to
Connect this pin to the SDA line on the master side. An provide the pull-up. Tie to ground if unused.
external pull-up resistor or current source is required.
SCL1-SCL4 (Pins 18, 23, 1, 17/Pins 16, 21, 23, 15):
GND (Pin 5/Pin 3): Device Ground. Serial Bus Clock Outputs Channels 1-4. Connect pins
SCLIN (Pin 6/Pin 4): Serial Bus Clock Input. Connect this SCL1-SCL4 to the SCL lines on the downstream
pin to the SCL line on the master side. An external pull-up channels 1-4, respectively. It is acceptable to float any pin
resistor or current source is required. that will never be connected to the upstream bus. Other-
wise, an external pull-up resistor or current source is
ENABLE (Pin 7/Pin 5): Digital Interface Enable and Regis- required on each pin.
ter Reset. Driving ENABLE high enables I2C communica-
tion to the LTC4306. Driving this pin low disables I2C SDA1-SDA4 (Pins 19, 22, 2, 16/Pins 17, 20, 24, 14):
communication to the LTC4306 and resets the registers to Serial Bus Data Output Channels 1-4. Connect pins
their default state as shown in the Operation section. SDA1-SDA4 to the SDA lines on downstream channels
When ENABLE returns high, masters can read and write 1-4, respectively. It is acceptable to float any pin that will
the LTC4306 again. If unused, tie ENABLE to VCC. never be connected to the upstream bus. Otherwise, an
external pull-up resistor or current source is required on
VCC (Pin 8/Pin 6): Power Supply Voltage. Connect a each pin.
bypass capacitor of at least 0.01µF directly between VCC
and GND for best results. ALERT1-ALERT4 (Pins 20, 24, 21, 9/Pins 18, 22,
19, 7): Fault Alert Inputs, Channels 1-4. Devices on each
GPIO1-GPIO2 (Pins 10, 11/Pins 8, 9): General Purpose of the four output channels can pull their respective pin
Input/Output. These two pins can be used as logic inputs, low to indicate that a fault has occurred. The LTC4306 then
open-drain outputs or push-pull outputs. The N-channel pulls the ALERT low to pass the fault indication on to the
MOSFET pull-down devices are capable of driving LEDs. host. See Operation section below for the details of how
When used in input or open-drain output mode, the GPIOs ALERT is set and cleared. Connect unused fault alert
can be pulled up to a supply voltage ranging from 1.5V to inputs to VCC.
5.5V independent of the VCC voltage. GPIOs default to a
high impedance open-drain output mode. There are GPIO Exposed Pad (Pin 25, UFD Package Only): Power Ground.
configuration and status bits in Register 1 and Register 2. Exposed Pad may be left open or connected to device
Float if unused. ground.

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 INACC UPSTREAM OUTACC
DOWNSTREAM
SLEW RATE SLEW RATE
BUFFERS
DETECTOR DETECTOR

SDAIN SDA1

SDA2

SDA3

SDA4
BLOCK DIAGRA
W

DOWNSTREAM
INACC UPSTREAM OUTACC 1V THRESHOLD
4 COMPARATORS
DOWNSTREAM
SLEW RATE SLEW RATE
BUFFERS
DETECTOR DETECTOR

SCLIN SCL1

STUCK LOW 0.52V SCL2

COMPARATORS

SCL3
READY
SCL4
FET1 FET2 FET3
FET4 ALERT1
SCLIN + 100ns CONN
GLITCH FILTER ALERT ALERT2
1.6V/1.52V – 1V THRESHOLD
COMPARATORS ALERT3
FET1-FET4
SDAIN + 100ns 4
GLITCH FILTER ALERT4
– 4
AL1-AL4
VCC TIMSET1 STUCK LOW
TIMEOUT ALERT
TIMSET0
50k CIRCUITRY 4 FET1-FET4
2pF
TIMEOUT_REAL ALERT LOGIC
TIMEOUT_LATCH

4 CH1CONN-CH4CONN UVLO
CONNECTION
VCC + UVLO CONN_REQ CIRCUITRY
1µs PORB
2.5V/2.35V – FILTER GND
FAILCONN_ATTEMPT
ENABLE + 2-WIRE BUS1_LOG-BUS4_LOG
4
1.1V/1V – DIGITAL
INTERFACE
+ AND 4
VCC REGISTERS AL1-AL4
1V –

ADDRESS
FIXED BITS
“10” ADR2
GPIO2
5 I2C ADDR 5
1 OF 27 ADR1

ADR0
+
VCC INACC
1V – OUTACC

GPIO1

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LTC4306
LTC4306
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OPERATIO
Control Register Bit Definitions
Register 0 (00h) Register 1 (01h)
BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 Downstream R Indicates if upstream bus is connected d7 Upstream R/W Activates upstream rise time
Connected to any downstream buses Accelerators accelerator currents
0 = upstream bus disconnected from Enable 0 = upstream rise time accelerator
all downstream buses currents inactive (default)
1 = upstream bus connected to one or 1 = upstream rise time accelerator
more downstream buses currents active
d6 ALERT1 Logic State R Logic state of ALERT1 pin, noninverting d6 Downstream R/W Activates downstream rise time
d5 ALERT2 Logic State R Logic state of ALERT2 pin, noninverting Accelerators accelerator currents
Enable 0 = downstream rise time accelerator
d4 ALERT3 Logic State R Logic state of ALERT3 pin, noninverting currents inactive (default)
d3 ALERT4 Logic State R Logic state of ALERT4 pin, noninverting 1 = downstream rise time accelerator
d2 Failed Connection R Indicates if an attempt to connect to a currents active
Attempt downstream bus failed because the d5 GPIO1 Output R/W GPIO1 output driver state,
“Connection Requirement” bit in Driver State noninverting, default = 1
Register 2 was low and the d4 GPIO2 Output R/W GPIO2 output driver state,
downstream bus was low Driver State noninverting, default = 1
0 = Failed connection attempt occurred
1 = No failed attempts at connection d3-d2 Reserved R Not Used
occurred d1 GPIO1 Logic R Logic state of GPIO1 pin,
d1 Latched Timeout R Latched bit indicating if a timeout has State noninverting
occurred and has not yet been cleared. d0 GPIO2 Logic R Logic state of GPIO2 pin,
0 = no latched timeout State noninverting
1 = latched timeout * For Type, “R/W” = Read Write, “R” = Read Only
d0 Timeout Real Time R Indicates real-time status of Stuck Low
Timeout Circuitry
0 = no timeout is occurring
1 = timeout is occurring
Note: Masters write to Register 0 to reset the fault circuitry after a fault
has occurred and been resolved. Because Register 0 is Read-Only, no
other functionality is affected.
* For Type, “R/W” = Read Write, “R” = Read Only

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 LTC4306
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OPERATIO
Register 2 (02h) Register 3 (03h)
BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 GPIO1 Mode R/W Configures Input/Output mode of d7 Bus 1 FET State R/W Sets and indicates state of FET
Configure GPIO1 switches connected to downstream
0 = output mode (default) bus 1
1 = input mode 0 = switch open (default)
d6 GPIO2 Mode R/W Configures Input/Output Mode of 1 = switch closed
Configure GPIO2 d6 Bus 2 FET State R/W Sets and indicates state of FET
0 = output mode (default) switches connected to downstream
1 = input mode bus 2
d5 Connection R/W Sets logic requirements for 0 = switch open (default)
Requirement downstream buses to be connected 1 = switch closed
to upstream bus d5 Bus 3 FET State R/W Sets and indicates state of FET
0 = Bus Logic State bits (see register switches connected to downstream
3) of buses to be connected must be bus 3
high for connection to occur (default) 0 = switch open (default)
1 = Connect regardless of 1 = switch closed
downstream logic state d4 Bus 4 FET State R/W Sets and indicates state of FET
d4 GPIO1 Output R/W Configures GPIO1 Output Mode switches connected to downstream
Mode Configure 0 = open-drain pull-down (default) bus 4
1 = push-pull 0 = switch open (default)
d3 GPIO2 Output R/W Configures GPIO2 Output Mode 1 = switch closed
Mode Configure 0 = open-drain pull-down (default) d3 Bus 1 Logic State R Indicates logic state of downstream
1 = push-pull bus 1; only valid when disconnected
d2 Mass Write Enable R/W Enable Mass Write Address using from upstream bus†
address (1011 101)b 0 = SDA1, SCL1 or both are below 1V
0 = Disable Mass Write 1 = SDA1 and SCL1 are both above
1 = Enable Mass Write (default) 1V
d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1** d2 Bus 2 Logic State R Indicates logic state of downstream
bus 2; only valid when disconnected
d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0** from upstream bus†
* For Type, “R/W” = Read Write, “R” = Read Only 0 = SDA2, SCL2 or both are below 1V
**Stuck bus program table 1 = SDA2 and SCL2 are both above
TIMSET1 TIMSET0 TIMEOUT MODE 1V
0 0 Timeout Disabled (Default) d1 Bus 3 Logic State R Indicates logic state of downstream
bus 3; only valid when disconnected
0 1 Timeout After 30ms from upstream bus†
1 0 Timeout After 15ms 0 = SDA3, SCL3 or both are below 1V
1 1 Timeout After 7.5ms 1 = SDA3 and SCL3 are both above
1V
d0 Bus 4 Logic State R Indicates logic state of downstream
bus 4; only valid when disconnected
from upstream bus†
0 = SDA4, SCL4 or both are below 1V
1 = SDA4 and SCL4 are both above
1V
* For Type, “R/W” = Read Write, “R” = Read Only
† These bits give the logic state of disconnected downstream buses to
the master, so that the master can choose not to connect to a low
downstream bus. A given bit is a “don’t care” if its associated
downstream bus is already connected to the upstream bus.

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LTC4306
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OPERATIO
The LTC4306 is a 4-channel, 2-wire bus multiplexer/ commanding connection to one or more downstream
switch with bus buffers to provide capacitive isolation channels, and second, there must be no stuck low
between the upstream bus and downstream buses. Mas- condition (see Stuck Low Timeout Fault discussion). If
ters on the upstream 2-wire bus (SDAIN and SCLIN) can the connection command is successful, the Upstream-
command the LTC4306 to any combination of the 4 Downstream Buffers pass signals between the upstream
downstream buses. Masters can also program the LTC4306 bus and the connected downstream buses. The LTC4306
to disconnect the upstream bus from the downstream also turns off its N-channel MOSFET open-drain pull-
buses if the bus is stuck low. down on the READY pin, so that READY can be pulled
high by its external pull-up resistor.
Undervoltage Lockout (UVLO) and ENABLE
Functionality Upstream-Downstream Buffers

The LTC4306 contains undervoltage lockout circuitry that Once the Upstream-Downstream Buffers are activated,
maintains all of its SDA, SCL, GPIO and ALERT pins in high the functionality of the SDAIN and any connected down-
impedance states until the device has sufficient VCC supply stream SDA pins is identical. A low forced on any con-
voltage to function properly. It also ignores any attempts nected SDA pin at any time results in all pins being low.
to communicate with it via the 2-wire buses in this condi- External devices must pull the pin voltages below 0.4V
tion. When the ENABLE pin voltage is low (below 0.8V), all worst-case with respect to the LTC4306’s ground pin to
control bits are reset to their default high impedance ensure proper operation. The SDA pins enter a logic high
states, and the LTC4306 ignores 2-wire bus commands. state only when all devices on all connected SDA pins force
However, with ENABLE low, the LTC4306 still monitors a high. The same is true for SCLIN and the connected
the ALERT1-ALERT4 pin voltages and pulls the ALERT pin downstream SCL pins. This important feature ensures
low if any of ALERT1-ALERT4 is low. When ENABLE is that clock stretching, clock arbitration and the acknowl-
high, devices can read from and write to the LTC4306. edge protocol always work, regardless of how the devices
in the system are connected to the LTC4306.
Connection Circuitry The Upstream-Downstream Buffers provide capacitive
Masters on the upstream SDAIN/SCLIN bus can write to isolation between SDAIN/SCLIN and the downstream con-
the Bus 1 FET State through Bus 4 FET State bits of register nected buses. Note that there is no capacitive isolation
3 to connect to any combination of downstream channels between connected downstream buses; they are only
1 to 4. By default, the Connection Circuitry shown in the separated by the series combination of their switches’ on
Block Diagram will only connect to downstream channels resistances.
whose corresponding Bus Logic State bits in register 3 are While any combination of downstream buses may be
high at the moment that it receives the connection com- connected at the same time, logic high levels are corrupted
mand. If the LTC4306 is commanded to connect to mul- if multiple downstream buses are active and both the VCC
tiple channels at once, it will only connect to the channels voltage and one or more downstream bus pull-up voltages
that are high. Masters can override this feature by setting are larger than the pull-up supply voltage for another
the Connection Requirement bit of register 2 high. With downsteam bus. An example of this issue is shown in
this bit high, the LTC4306 executes connection com- Figure 1. During logic highs, DC current flows from VBUS1
mands without regard to the logic states of the down- through the series combination of R1, N1, N2 and R2 and
stream channels. into VBUS2, causing the SDA1 voltage to drop and current
Upon receiving the connection command, the Connec- to be sourced into VBUS2. To avoid this problem, do not
tion Circuitry will activate the Upstream-Downstream activate bus 1 or any other downstream bus whose pull-
Buffers under two conditions: first, the master must be up voltage is above 2.5V when bus 2 is active.

4306f

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 LTC4306
U
OPERATIO
VCC = VBUS1 = 5V channel. Note that users can write a high to the Connection
Requirement bit of register 2 high to program the LTC4306
R1
SDA1 10k
to connect to downstream channels regardless of their
logic state at the moment of connection. In this case, the
N1 VBUS2 = 2.5V
downstream channel connection fault never occurs.
R2
SDA2
10k
4306 F01
Stuck Low Timeout Fault
N2
The stuck low timeout circuitry monitors the two common
Figure 1. Example of Unacceptable Level Shifting internal nodes of the downstream SDA and SCL switches
and runs a timer whenever either of the internal node
Rise Time Accelerators voltages is below 0.52V. The timer is reset whenever both
The Upstream Accelerators Enable and Downstream Ac- internal node voltages are above 0.6V. If the timer ever
celerators Enable bits of register 1 activate the upstream reaches the time programmed by Timeout Mode Bits 1 and
and downstream rise time accelerators, respectively. 0 of register 2, the LTC4306 pulls ALERT low and discon-
When activated, the accelerators turn on in a controlled nects the downstream bus(es) from the upstream bus by
manner and source current into the pins during positive de-biasing the Upstream-Downstream Buffers. Note that
bus transitions. the downstream switches remain in their existing state.
The Timeout Real-Time bit of register 0 indicates the real-
When no downstream buses are connected, an upstream time status of the stuck low situation. The Latched Timeout
accelerator turns on when its pin voltage exceeds 0.8V Bit of register 0 is a latched bit that is set high when a
and is rising at a minimum slew rate of 0.8V/µs. When one timeout occurs.
or more downstream buses are connected, the accelera-
tor on a given pin turns on when these conditions are met: External Faults on the Downstream Channels
first, the pin’s voltage is rising at a minimum slew rate of
When a slave on downstream bus 1 pulls the ALERT1 pin
0.8V/µs; second, the voltages on both the upstream bus
below 1V, the LTC4306 passes this information to the
and the connected downstream buses exceed 0.8V.
master on the upstream bus by pulling the ALERT pin low.
Note that a downstream bus’s switch must be closed in The same is true for the other three downstream buses.
order for its rise time accelerator current to be active. See Each bus has its own dedicated fault bit in Register 0, so
the Applications Section for choosing a bus pull-up resis- that masters can read Register 0 to determine which buses
tor value to ensure that the rise time accelerator switches have faults.
turn on. Do not activate boost currents on a bus whose
pull-up supply voltage VBUS is less than VCC. Doing so ALERT Functionality and Fault Resolution
would cause the boost currents to source current from When a fault occurs, the LTC4306 pulls the ALERT pin low,
VCC into the VBUS supply during rising edges. as described previously. The procedure for resolving
faults depends on the type of fault. If a master on the
Downstream Bus Connection Fault
upstream bus is communicating with devices on a down-
By default, the LTC4306 will only connect to downstream stream bus via the Upstream-Downstream Buffer cir-
channels whose SDA and SCL pins are both high (above cuitry—channel 1, for example—and a device on this bus
1V) at the moment that it receives the connection com- pulls the ALERT1 pin low, the LTC4306 acts transparently,
mand. In this case, the LTC4306 sets the Failed Connec- and the master communicates directly with the device that
tion Attempt bit of register 0 low and pulls the ALERT pin caused the fault via the upstream-downstream buffer
low when the master tries to connect to a low downstream circuitry to resolve the fault.

4306f

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LTC4306
U
OPERATIO
In all other cases, the LTC4306 communicates with the connect to bus 2, so that it can communicate with the
master to resolve the fault. After the master broadcasts the source of the fault. At this point, the master writes to
Alert Response Address (ARA), the LTC4306 will respond register 0 to clear the LTC4306 fault register.
with its address on the SDAIN line and release the ALERT
pin. The ALERT line will also be released if the LTC4306 is I2C Device Addressing
addressed by the master. Twenty-seven distinct bus addresses are configurable
The ALERT signal will not be pulled low again until a using the three state ADR0, ADR1 and ADR2 pins. Table 1
different type of fault has occurred or the original fault is shows the correspondence between pin states and ad-
cleared and it occurs again. Figure 2 shows the details of dresses. Note that address bits a6 and a5 are internally
how the ALERT pin is set and reset. The downstream bus configured to 1 and 0 respectively. In addition, the LTC4306
connection fault and faults that occur on unconnected responds to two special addresses. Address (1011 101) is
downstream buses are grouped together and generate a a mass write used to write all LTC4306’s, regardless of
single signal to drive ALERT. The stuck low timeout fault their individual address settings. The mass write can be
has its own dedicated pathway to ALERT; however, once masked by setting the Mass Write Enable bit of register 2
a stuck low occurs, another one will not occur until the first to zero. Address (0001 100) is the SMBus Alert Response
one is cleared. For these reasons, once the master has Address. Figure 3 shows data transfer over a 2-wire bus.
established the LTC4306 as the source of the fault, it
should read register 0 to determine the specific problem, Supported Commands
take action to solve the problem, and clear the fault Users must write to the LTC4306 using the SMBus Write
promptly. All faults are cleared by writing a dummy data Byte protocol and read from it using the Read Byte
byte to register 0, which is a read-only register. protocol. During fault resolution, the LTC4306 also
For example, assume that a fault occurs, the master sends supports the Alert Response Address protocol. The
out the ARA, and the LTC4306 successfully writes formats for these protocols are shown in Figure 4. Users
its address onto SDAIN and releases its ALERT pin. The must follow the Write Byte protocol exactly to write to the
master reads register 0 and learns that the ALERT2 logic LTC4306; if a Repeated Start Condition is issued before a
state bit is low. The master now knows that a device on Stop Condition, the LTC4306 ignores the attempted write,
downstream bus 2 has a fault and writes to register 3 to and its control bits remain in their preexisting state. When
ALERT
FAULT ON DISCONNECTED
DOWNSTREAM BUS
DOWNSTREAM BUS VCC
CONNECTION FAULT
D Q FAULT ON CONNECTED
DOWNSTREAM BUS
WRITE
REGISTER 0 RD

ADDRESS LTC4306

LTC4306 RESPONDS
TO ARA
STUCK BUS
VCC

D Q

WRITE
REGISTER 0 RD
4306 F02

Figure 2. Setting and Resetting the ALERT Pin

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 LTC4306
U
OPERATIO
Table 1. LTC4306 I2C Device Addressing
HEX DEVICE LTC4306
DESCRIPTION ADDRESS BINARY DEVICE ADDRESS ADDRESS PINS
h a6 a5 a4 a3 a2 a1 a0 R/W ADR2 ADR1 ADR0
Mass Write BA 1 0 1 1 1 0 1 0 X X X
Alert Response 19 0 0 0 1 1 0 0 1 X X X
0 80 1 0 0 0 0 0 0 X L NC L
1 82 1 0 0 0 0 0 1 X L H NC
2 84 1 0 0 0 0 1 0 X L NC NC
3 86 1 0 0 0 0 1 1 X L NC H
4 88 1 0 0 0 1 0 0 X L L L
5 8A 1 0 0 0 1 0 1 X L H H
6 8C 1 0 0 0 1 1 0 X L L NC
7 8E 1 0 0 0 1 1 1 X L L H
8 90 1 0 0 1 0 0 0 X NC NC L
9 92 1 0 0 1 0 0 1 X NC H NC
10 94 1 0 0 1 0 1 0 X NC NC NC
11 96 1 0 0 1 0 1 1 X NC NC H
12 98 1 0 0 1 1 0 0 X NC L L
13 9A 1 0 0 1 1 0 1 X NC H H
14 9C 1 0 0 1 1 1 0 X NC L NC
15 9E 1 0 0 1 1 1 1 X NC L H
16 A0 1 0 1 0 0 0 0 X H NC L
17 A2 1 0 1 0 0 0 1 X H H NC
18 A4 1 0 1 0 0 1 0 X H NC NC
19 A6 1 0 1 0 0 1 1 X H NC H
20 A8 1 0 1 0 1 0 0 X H L L
21 AA 1 0 1 0 1 0 1 X H H H
22 AC 1 0 1 0 1 1 0 X H L NC
23 AE 1 0 1 0 1 1 1 X H L H
24 B0 1 0 1 1 0 0 0 X H H L
25 B2 1 0 1 1 0 0 1 X L H L
26 B4 1 0 1 1 0 1 0 X NC H L

users follow the Write Byte protocol exactly, the new data Mode Configure bits in register 2 determine whether the
contained in the Data Byte is written into the register GPIOs are used as inputs or outputs. When the GPIOs are
selected by bits r1 and r0 on the Stop Bit. used as outputs, the GPIO1 and GPIO2 Output Mode
Configure bits of register 2 configure the GPIO outputs
General Purpose Input/Outputs (GPIOs) either as open-drain N-channel MOSFET pull-downs or
The LTC4306 provides two general purpose input/output push-pull stages.
pins (GPIOs) that can be configured as logic inputs, open- In push-pull mode, at VCC = 3.3V, the typical pull-up
drain outputs or push-pull outputs. The GPIO1 and GPIO2 impedance is 670Ω and the typical pull-down impedance
4306f

13
LTC4306
U
OPERATIO
SDA a6-a0 d7-d0 d7-d0

SCL 1-7 8 9 1-7 8 9 1-7 8 9

S P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

CONDITION CONDITION
4306 F03

Figure 3. Data Transfer Over I2C or SMBus

1 7 1 1 8 1 8 1 1
START 10 a4-a0 WR ACK XXXXXX r1r0 ACK d7-d0 ACK STOP
SLAVE S REGISTER S DATA S
ADDRESS 0 0 0 BYTE 0
WRITE BYTE PROTOCOL

1 7 1 1 8 1 1 7 1 1 8 1 1
START 10 a4-a0 WR ACK XXXXXX r1r0 ACK START 10 a4-a0 RD ACK d7-d0 ACK STOP
SLAVE S REGISTER S SLAVE S DATA M
ADDRESS 0 0 0 ADDRESS 1 0 BYTE 1
READ BYTE PROTOCOL

1 7 1 1 8 1 1
S 0001 100 RD ACK DEVICE ADDRESS ACK P
4306 F04
S M
1 0 1
ALERT RESPONSE ADDRESS PROTOCOL

Figure 4. Protocols Accepted by LTC4306

is 35Ω, making the GPIO pull-downs capable of driving in open-drain output mode and one or more external
LEDs. At VCC = 5V, the typical pull-up impedance is 320Ω devices are connected to the GPIOs. If the LTC4306 is
and the typical pull-down impedance is 20Ω. In open- trying to write a high to a GPIO pin, but the pin’s actual
drain output mode, the user provides the logic high by logic state is low, then the LTC4306 knows that the low is
connecting a pull-up resistor between the GPIO pin and an being forced by an external device.
external supply voltage. The external supply voltage can
range from 1.5V to 5.5V independent of the VCC voltage. Glitch Filters
In input mode, the GPIO input threshold voltage is 1V. The LTC4306 provides glitch filters on the SDAIN and
The GPIO1 and GPIO2 Logic State bits in register 1 SCLIN pins as required by the I2C Fast Mode (400kHz)
indicate the logic state of the two GPIO pins. The logic- Specification. The filters prevent signals of up to 50ns
level threshold voltage for each pin is 1V. The GPIO1 and (minimum) time duration and rail-to-rail voltage
GPIO2 Output Driver State bits in register 1 indicate the magnitude from passing into the two-wire bus digital
logic state that the LTC4306 is attempting to write to the interface circuitry.
GPIO pins. This is useful when the GPIOs are being used

4306f

14
 LTC4306
U
OPERATIO
Fall Time Control where tf is the fall time in ns and CB is the equivalent bus
capacitance in pF. Whenever the Upstream-Downstream
Per the I2C Fast Mode (400kHz) Specification, the two-
wire bus digital interface circuitry provides fall time con- Buffer Circuitry is active, its output signal will meet the fall
trol when forcing logic lows onto the SDAIN bus. The fall time requirements, provided that its input signal meets the
time always meets the limits: fall time requirements.

(20 + 0.1 • CB) < tf < 300ns

U U W U
APPLICATIO S I FOR ATIO
Design Example the required minimum strength of the pull-up resistors is
A typical LTC4306 application circuit is shown in Figure 5. determined by the minimum slew requirement to guaran-
The circuit illustrates the level-shifting, multiplexer/switch tee that the LTC4306’s rise time accelerators are activated
and capacitance buffering features of the LTC4306. In this during rising edges. At the same time, the pull-up value
application, the LTC4306 VCC voltage and downstream should be kept low to maximize the logic low noise margin
bus 1 are powered from a 3.3V supply voltage; down- and minimize the offset voltage of the Upstream-Down-
stream bus 4 is powered from 5V, and the upstream bus stream Buffer circuitry. The LTC4306 is designed to func-
is powered from 2.5V. Channels 2 and 3 are omitted for tion for a maximum DC pull-up current of 4mA. If multiple
simplicity. The following sections describe a methodology downstream channels are active at the same time, this
for choosing the external components in Figure 5. means that the sum total of the pull-up currents from these
channels must be less than 4mA. At supply voltages of
SDA, SCL Pull-Up Resistor Selection 2.7V and 5.5V, pull-up resistor values of 10k work well for
capacitive loads up to 215pF and 420pF, respectively. For
The pull-up resistors on the SDA and SCL pins must be larger bus capacitances, refer to equation (1) below. The
strong enough to provide a minimum of 100µA pull-up LTC4306 works with capacitive loads up to 2nF.
current, per the SMBus Specification. In most systems,

VBACK = 2.5V VCC = VBUS1 = 3.3V

C1
R1 R2 R3 0.01µF R4 R5 R6
6
10k 10k 10k 10k 10k 10k
VCC
4 16
SCLIN SCL1
2 17 SFP
MICROCONTROLLER SDA1N SDA1
1 18 MODULE 1
ALERT ALERT1
ADDRESS = 1111 000

LTC4306UFD VBUS4 = 5V
R10
1k D1 8
VCC GPIO1 R7 R8 R9
10k 10k 10k
12 15
ADR2 SCL4
11 14 SFP
ADR1 SDA4
10 7 MODULE 4
ADR0 ALERT4
3
GND ADDRESS = 1111 001
4306 F05

ADDRESS = 1000 100

Figure 5. A Level Shifting Circuit

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LTC4306
U U W U
APPLICATIO S I FOR ATIO
Assume in Figure 5 that the total parasitic bus capacitance having device address 1001 000. If the four I/O cards were
on SDA1 due to trace and device capacitance is 100pF. To plugged directly into the backplane, the four sensors
ensure that the boost currents are active during rising would require four unique addresses. However, if masters
edges, the pull-up resistor must be strong enough to use the LTC4306 in multiplexer mode, where only one
cause the SDA1 pin voltage to rise at a rate of 0.8V/µs as downstream channel is connected at a time, then each
the pin voltage is rising above 0.8V. The equation is: I/O card can have a device with address 1001 000 and no
problems will occur.
⎧ ⎡ ns ⎤ ⎫
⎨( VBUSMIN – 0 . 8 V) • 1250 ⎢ ⎥ ⎬ Figures 7 and 8 show two different methods for hot-
⎣ V ⎦ ⎭ (1)
RPULL −UP,MAX [kΩ ] = ⎩ swapping I/O cards onto a live two-wire bus using the
CBUS [pF ] LTC4306. The circuitry of Figure 7 consists of an LTC4306
residing on the edge of an I/O card having four separate
where VBUSMIN is the minimum operating pull-up supply downstream buses. Connect a 200k resistor to ground
voltage, and CBUS is the bus parasitic capacitance. In our from the ENABLE pin and make the ENABLE pin the
example, VBUS1 = VCC = 3.3V, and assuming ±10% supply shortest pin on the connector, so that the ENABLE pin
tolerance, VBUS1MIN = 2.97V. With CBUS = 100pF, remains at a constant logic low while all other pins are
RPULL-UP,MAX = 27.1k. Therefore, we must choose a pull- connecting. This ensures that the LTC4306 remains in its
up resistor smaller (i.e., stronger pull-up) than 27.1k, so default high impedance state and ignores connection
a 10k resistor works fine. transients on its SDAIN and SCLIN pins until they have
established solid contact with the backplane 2-wire bus. In
ALERT, READY and GPIO Component Selection
addition, make sure that the ALERT connector pin is
The pull-up resistors on the ALERT and READY pins must shorter than the VCC pin, so that VCC establishes solid
provide a maximum pull-up current of 3mA, so that the contact with the I/O card pull-up supply pin and powers
LTC4306 is capable of holding the pin at logic low voltages the pull-up resistors on ALERT1–ALERT4 before ALERT
below 0.4V. When choosing LEDs to be driven by the makes contact.
LTC4306’s GPIO pins, make sure that the required LED
Figure 8 illustrates an alternate SDA and SCL hot-swap-
sinking current is less than 5mA, and add a current-
ping technique, where the LTC4306 is located on the
limiting resistor in series with the LED.
backplane and an I/O card plugs into downstream channel
Level Shifting Considerations 4. Before plugging and unplugging the I/O card, make sure
that channel 4’s downstream switch is open, so that it does
In the design example of Figure 5, the LTC4306 VCC not disturb any 2-wire transaction that may be occurring
voltage is less than or equal to both of the downstream bus at the moment of connection/disconnection. Note that
pull-up voltages, so buses 1 and 4 can be active at the pull-up resistor, R17, on ALERT4 should be located on the
same time. Likewise, the rise time accelerators can be backplane and not the I/O card to ensure proper operation
turned on for the downstream buses, but must never be of the LTC4306 when the I/O card is not present. The pull-
activated on SCLIN and SDAIN, because doing so would up resistors on SCL4 and SDA4, R15 and R16 respec-
result in significant current flow from VCC to VBACK during tively, may be located on the I/O card, provided that
rising edges. downstream bus 4 is never activated when the I/O card is
not present. Otherwise, locate R15 and R16 on the
Other Application Circuits backplane.
Figure 6 illustrates how the LTC4306 can be used to
expand the number of devices in a system by using nested
addressing. Each I/O card contains a temperature sensor

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 LTC4306
U U W U
APPLICATIO S I FOR ATIO
VCC

C1
R2 R3 R4 R5 R6 R7 R8
0.01µF
10k 10k 10k 10k 10k 10k 10k
6
VCC 16
SCL1
4 17 TEMPERATURE
SCLIN SDA1
18 SENSOR
µP ALERT1
2
SDAIN ADDRESS = 1001 000

5
ENABLE
R9 R10 R11
1 21 10k 10k 10k
ALERT SCL2
20 TEMPERATURE
SDA2
13 22 SENSOR
READY ALERT2
R1
LTC4306UFD ADDRESS = 1001 000
1k LED 8
GPI01

9 R12 R13 R14

GPI02 10k 10k 10k
23
SCL3
24 TEMPERATURE
SDA3
19 SENSOR
ALERT3
12
VCC ADR2 ADDRESS = 1001 000

11
OPEN ADR1
R15 R16 R17
15 10k 10k 10k
10
ADR0 SCL4
14 TEMPERATURE
SDA4
3 7 SENSOR
GND ALERT4
ADDRESS = 1001 000
4306 F06
ADDRESS = 1010 000

Figure 6. Nested Addressing Application

4306f

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LTC4306
U U W U
APPLICATIO S I FOR ATIO
VCC

C1
0.01µF
R4 R5 R6 R7 R8
6
10k 10k 10k 10k 10k
VCC 16
SCL1 CARD_SCL1
4 17
SCLIN SDA1 CARD_SDA1
18
µP ALERT1 CARD_ALERT1
2
SDAIN

5 VBUS2
VCC ENABLE
R9 R10 R11
R18
VCC 10k 10k 10k
200k 21
SCL2 CARD_SCL2
R3 20
SDA2 CARD_SDA2
10k 1 22
ALERT ALERT2 CARD_ALERT2

LTC4306UFD
R12 R13 R14
10k 10k 10k
23
SCL3 CARD_SCL3
24
SDA3 CARD_SDA3
19
ALERT3 CARD_ALERT3
12
VCC ADR2

11
OPEN ADR1
R15 R16 R17
10k 10k 10k
10 15
ADR0 SCL4 CARD_SCL4
14
SDA4 CARD_SDA4
3 7
GND ALERT4 CARD_ALERT4

R2
10k LED
13 R1
READY 1k
8
GPI01
9
GPI02
4306 F07

BACKPLANE CARD ADDRESS = 1010 000

CONNECTOR CONNECTOR

Figure 7. Hot-Swapping Application

4306f

18
 LTC4306
U
PACKAGE DESCRIPTIO
UFD Package
24-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1696)

2.65 ± 0.10
(2 SIDES) PIN 1 NOTCH
R = 0.30 TYP
R = 0.115
4.00 ± 0.10 0.75 ± 0.05
TYP
(2 SIDES) 23 24

0.40 ± 0.05
0.70 ±0.05 PIN 1
TOP MARK
(NOTE 6) 1

4.50 ± 0.05 2
3.10 ± 0.05
2.65 ± 0.05
(2 SIDES) 5.00 ± 0.10 3.65 ± 0.10
(2 SIDES) (2 SIDES)

PACKAGE
OUTLINE

0.25 ±0.05 (UFD24) QFN 0505

0.50 BSC
3.65 ± 0.05 0.200 REF 0.25 ± 0.05
(2 SIDES) 0.00 – 0.05 0.50 BSC
4.10 ± 0.05
BOTTOM VIEW—EXPOSED PAD
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 5. EXPOSED PAD SHALL BE SOLDER PLATED
2. DRAWING NOT TO SCALE 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
3. ALL DIMENSIONS ARE IN MILLIMETERS ON THE TOP AND BOTTOM OF PACKAGE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

GN Package
24-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)

.337 – .344*
(8.560 – 8.738) .033
.045 ±.005 (0.838)
24 23 22 21 20 19 18 17 16 15 1413
REF

.229 – .244 .150 – .157**

.254 MIN .150 – .165
(5.817 – 6.198) (3.810 – 3.988)

.0165 ± .0015 .0250 BSC 1 2 3 4 5 6 7 8 9 10 11 12

RECOMMENDED SOLDER PAD LAYOUT

.015 ± .004
× 45° .0532 – .0688 .004 – .0098
(0.38 ± 0.10)
(1.35 – 1.75) (0.102 – 0.249)
.0075 – .0098 0° – 8° TYP
(0.19 – 0.25)

.016 – .050 .008 – .012 .0250 GN24 (SSOP) 0204

(0.406 – 1.270) (0.203 – 0.305) (0.635)
TYP BSC
NOTE:
1. CONTROLLING DIMENSION: INCHES *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
INCHES SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
2. DIMENSIONS ARE IN
(MILLIMETERS) **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
3. DRAWING NOT TO SCALE FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

4306f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4306
U U W U
APPLICATIO S I FOR ATIO
VCC = 3.3V

C1
R2 R3 R4 R5 0.01µF R6 R7 R8
10k 10k 10k 10k 10k 10k 10k

VCC SCL1
TEMPERATURE
SCLIN SDA1
SENSOR
MICRO- ALERT1
CONTROLLER
SDAIN VCC2 = 5V

ENABLE
R9 R10 R11
10k 10k 10k
ALERT SCL2
VOLTAGE
SDA2
MONITOR
READY ALERT2
VCC LTC4306UFD VCC3 = 2.5V
GPI01
R1 LED
1k R12 R13 R14
GPI02 10k 10k 10k
SCL3
TEMPERATURE
SDA3
SENSOR
ALERT3
ADR2 VCC4 = 3.3V

OPEN ADR1
R15 R16 R17
10k 10k 10k
ADR0 SCL4
VOLTAGE
SDA4
MONITOR
GND ALERT4
4306 F08
I/O CARD
ADDRESS = 1010 000

Figure 8. Downstream Side Hot-Swapping Application

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1380/LTC1393 Single-Ended 8-Channel/Diffierential 4-Channel Analog Low RON: 35Ω Single-Ended/70Ω Differential, Expandable to
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LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer Isolates Backplane and Card Capacitances
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Level Translation
LTC4303/LTC4304 How Swappable Bus Buffers with Stuck Bus Recovery Recover Stuck Buses with Automatic Clocking
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Buffering Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance
ThinSOT is a trademark of Linear Technology Corporation.
4306f

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