MEMORY BASICS

The DRAM controller is a complex synchronous sequential circuit with the exter-
nal CPU clock providing synchronization of its operation.

8 CHAPTER SUMMARY
Memory is of two types: random-access memory (RAM) and read-only memory
(ROM). For both types, we apply an address to read from or write into a data
word. Read and write operations have specific steps and associated timing parame-
ters, including access time and write cycle time. Memory can be static or dynamic
and volatile or nonvolatile. Internally, a RAM chip consists of an array of RAM
cells, decoders, write circuits, read circuits, and output circuits. A combination of a
write circuit, read circuit, and the associated RAM cells can be logically modeled
as a RAM bit slice. RAM bit slices, in turn, can be combined to form two-dimen-
sional RAM cell arrays, which, with decoders and output circuits added, form the
basis for a RAM chip. Output circuits use three-state buffers in order to facilitate
connecting together an array of RAM chips without significant additional logic.
Due to the need for refresh, additional circuitry is required within DRAMs, as well
as in arrays of DRAM chips. In a quest for faster memory access, a number of new
DRAM types have been developed. The most recent forms of these high-speed
DRAMs employ a synchronous interface that uses a clock to control memory
accesses.
Error-detection and correction codes, often based on Hamming codes, are used to
detect or correct errors in stored RAM data. Material from Edition 1 covering
these codes is available on the Companion Website for the text.

REFERENCES
1. WESTE, N. H. E. AND K. ESHRAGHIAN. Principles of CMOS VLSI Design: A
Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993.
2. Micron Technology, Inc. Micron 256Mb: ×4, ×8, ×16 SDRAM.
www.micron.com, 2002.
3. Micron Technology, Inc. Micron 64Mb: ×32 DDR SDRAM. www.micron.com,
2001.
4. SOBELMAN, M. “Rambus Technology Basics,” Rambus Developer Forum.
Rambus, Inc., October 2001.
5. Rambus, Inc. Rambus Direct RDRAM 128/144-Mbit (256×16/18×32s)—
Preliminary Information, Document DL0059 Version 1.11.

PROBLEMS
The plus (+) indicates a more advanced problem and the asterisk (*) indicates that
a solution is available on the Companion Website for the text.
1. *The following memories are specified by the number of words times the
number of bits per word. How many address lines and input–output data


 MEMORY BASICS

lines are needed in each case? (a) 48K × 8, (b) 512K × 32, (c) 64M × 64, and
(d) 2G × 1.
2. Word number (835)10 in the memory shown in Figure 2 contains the binary
equivalent of (15,103)10 . List the 10-bit address and the 16-bit memory
contents of the word.
3. *A 64K × 16 RAM chip uses coincident decoding by splitting the internal
decoder into row select and column select. (a) Assuming that the RAM cell
array is square, what is the size of each decoder, and how many AND gates
are required for decoding an address? (b) Determine the row and column
selection lines that are enabled when the input address is the binary
equivalent of (32000)10 .
4. Assume that the largest decoder that can be used in an m × 1 RAM chip has
14 address inputs and that coincident decoding is employed. In order to
construct RAM chips that contain more one-bit words than m, multiple
RAM cell arrays, each with decoders and read/write circuits, are included in
the chip.
(a) With the decoder restrictions given, how many RAM cell arrays are
required to construct a 2G × 1 RAM chip?
(b) Show the decoder required to select from among the different RAM
arrays in the chip and its connections to address bits and cell array select
(CS) bits.
5. A DRAM has 15 address pins and its row address is 1 bit longer than its
column address. How many addresses, total, does the DRAM have?
6. A 1 Gb DRAM uses 4-bit data and has equal-length row and column
addresses. How many address pins does the DRAM have?
7. A DRAM has a refresh interval of 128 ms and has 4096 rows. What is the
interval between refreshes for distributed refresh? What is the total time
required out of the 128 ms for a refresh of the entire DRAM? What is the
minimum number of address pins on the DRAM?
8. *(a) How many 128K × 16 RAM chips are needed to provide a memory
capacity of 2 MB?
(b) How many address lines are required to access 2 MB? How many of
these lines are connected to the address inputs of all chips?
(c) How many lines must be decoded to produce the chip select inputs?
Specify the size of the decoder.
9. Using the 64K × 8 RAM chip in Figure 9 plus a decoder, construct the block
diagram for a 512K × 16 RAM.
10. Explain how SDRAM takes advantage of the two-dimensional storage array
to provide a high data access rate.
11. Explain how a DDRAM achieves a data rate that is a factor of two higher
than a comparable SDRAM.