MCP23009/MCP23S09

8-Bit I/O Expander with Open-Drain Outputs

Features: • Configurable Interrupt Source:
- Interrupt-on-Change from configured defaults
• 8-Bit Remote Bidirectional I/O Port:
or pin change
- I/O Pins Default to Input
• Polarity inversion register to configure the polarity
• Open-Drain Outputs: of the input port data
- 5.5V Tolerant • External Reset Input
- 25 mA Sink Capable (per Pin) • Low Standby Current:
- 200 mA Total - 1 µA (-40°C  TA  +85°C)
• High-Speed I2C™ Interface (MCP23009): - 6 µA (+85°C  TA  +125°C)
- 100 kHz • Operating Voltage:
- 400 kHz - 1.8V to 5.5V
- 3.4 MHz • Available Packages:
• High-Speed SPI Interface (MCP23S09): - 16-Lead QFN (3x3x0.9 mm)
- 10 MHz - 18-Lead PDIP (300 mil)
• Single Hardware Address Pin (MCP23009): - 18-Lead SOIC (7.50 mm)
- Voltage input to allow up to eight devices on - 20-Lead SSOP (5.30 mm)
the bus
• Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or
open-drain

Block Diagram

MCP23S09
CS
SCK
SI
SPI
SO

MCP23009

SCL Serializer/
I2C™ Deserializer GP0
SDA
GP1
RESET GP2
8
GPIO GP3
INT GP4
Control
GP5
Multi-Bit
ADDR GP6
Decode
GP7
8

Configuration/
Control
Registers

 2009-2014 Microchip Technology Inc. DS20002121C-page 1

MCP23009/MCP23S09
Package Types

MCP23009 MCP23009 MCP23009

PDIP, SOIC 3 x 3 QFN* SSOP

GP7
GP6
GP5
GP4
VDD 1 18 VSS VDD 1 20 VSS
NC 2 17 NC NC 2 19 NC
16 15 14 13
SCL NC SCL 3 18 NC
3 16 VSS 1 12 GP3
SDA 4 17 GP7
SDA 4 15 GP7 NC 2 EP 11 GP2 ADDR 5 GP6
16
ADDR 5 14 GP6 17
VDD 3 10 GP1 RESET 6 15 GP5
RESET 6 13 GP5
SCL 4 9 GP0 INT 7 14 GP4
INT 7 12 GP4 GP0
5 6 7 8 8 13 GP3
GP0 8 11 GP3 GP1 9 GP2

ADDR
RESET
INT
SDA
12
GP1 9 10 GP2 NC 10 11 NC

MCP23S09 MCP23S09
PDIP/SOIC 3 x 3 QFN*

GP7
GP6
GP5
GP4
VDD 1 18 VSS
NC 2 17 NC 16 15 14 13
CS 3 16 GP7 VSS 1 12 GP3
SCK 4 15 GP6 SCK 2 11 GP2
EP
SI 5 14 GP5 17
VDD 3 10 GP1
SO 6 13 GP4
CS 4 9 GP0
RESET 7 12 GP3
5 6 7 8
INT 8 11 GP2

SI
SO
RESET
INT
GP0 9 10 GP1

* Includes Exposed Thermal Pad (EP); see Tables 1-1 and 1-2.

DS20002121C-page 2  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
1.0 DEVICE OVERVIEW
The MCP23X09 device provides 8-bit, general purpose
parallel I/O expansion for I2C bus or SPI applications.
The two devices differ only in the serial interface.
• MCP23009 – I2C interface
• MCP23S09 – SPI interface
The MCP23X09 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
input or output register. The polarity of the input port
register can be inverted with the polarity inversion
register. All registers can be read by the system master.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding input port register state. This is
used to indicate to the system master that an
input state has changed.
2. When an input state differs from a
pre-configured register value (DEFVAL
register).
The Interrupt Capture register captures port values at
the time of the Interrupt, thereby saving the condition
that caused the Interrupt.
The Power-On Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pin is used to determine the
device address.

 2009-2014 Microchip Technology Inc. DS20002121C-page 3

MCP23009/MCP23S09
1.1 Pin Descriptions

TABLE 1-1: I2C™ PINOUT DESCRIPTION (MCP23009)

Pin Number
Pin Pin
16-lead 18-lead 20-lead Standard Function
Name Type
QFN PDIP/SOIC SSOP
VDD 3 1 1 P Power
NC 2 2, 16-17 2, 10-11, — Not connected
18-19
SCL 4 3 3 I Serial clock input
SDA 5 4 4 I/O Serial data I/O
ADDR 6 5 5 I Hardware address pin allows up to eight slave devices on the
bus
RESET 7 6 6 I Hardware reset
INT 8 7 7 O Interrupt output for port. Can be configured as active-high,
active-low or open-drain.
GP0 9 8 8 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP1 10 9 9 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP2 11 10 12 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP3 12 11 13 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP4 13 12 14 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP5 14 13 15 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP6 15 14 16 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP7 16 15 17 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
VSS 1 18 20 P Ground
EP 17 — — — Exposed Thermal Pad (EP). Can be left floating or connected
to VSS.

DS20002121C-page 4  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S09)
Pin Number
Pin Pin
16-lead 18-lead Standard Function
Name Type
QFN PDIP/SOIC
VDD 3 1 P Power (high-current capable)
NC — 2, 17 — Not connected
CS 4 3 I Chip select
SCK 2 4 I Serial clock input
SI 5 5 I Serial data input
SO 6 6 O Serial data out
RESET 7 7 I Hardware reset (must be externally biased)
INT 8 8 O Interrupt output for port. Can be configured as active-high, active-low or
open-drain.
GP0 9 9 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP1 10 10 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP2 11 11 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP3 12 12 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP4 13 13 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP5 14 14 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP6 15 15 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP7 16 16 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
VSS 1 18 P Ground (high-current capable)
EP 17 — — Exposed Thermal Pad (EP). Can be left floating or connected to VSS.

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MCP23009/MCP23S09
1.2 Power-On Reset (POR) • Sequential mode enables automatic address
pointer incrementing. When operating in
The on-chip POR circuit holds the device in reset until Sequential mode, the MCP23X09 increments its
VDD has reached a high enough voltage to deactivate address counter after each byte during the data
the POR circuit (i.e., release the device from reset). transfer. The address pointer automatically rolls
The maximum VDD rise time is specified in the over to address 00h after accessing the last
electrical specification section. register.
When the device exits the POR condition (releases These two modes are not to be confused with single
reset), the device operating parameters (i.e., voltage, writes/reads and continuous writes/reads, which are
temperature, serial bus frequency, etc.) must be met to serial protocol sequences. For example, the device
ensure proper operation. may be configured for Byte mode and the master may
perform a continuous read. In this case, the
1.3 Serial Interface MCP23X09 would not increment the address pointer
and would repeatedly drive data from the same
This block handles the functionality of the I2C
location.
(MCP23009) or SPI (MCP23S09) interface protocol.
The MCP23X09 contains eleven (11) individual 1.3.2 I2C INTERFACE
registers which can be addressed through the Serial
Interface block (Table 1-3). 1.3.2.1 I2C Write Operation
The I2C write operation includes the control byte and
TABLE 1-3: REGISTER ADDRESSES
the register address sequence, as shown in the bottom
Address Access to of Figure 1-1. This sequence is followed by eight bits of
00h IODIR data from the master and an Acknowledge (ACK) from
the MCP23009. The operation is ended with a Stop (P)
01h IPOL
or Restart (SR) condition being generated by the
02h GPINTEN master.
03h DEFVAL
Data is written to the MCP23009 after every byte
04h INTCON transfer. If a Stop or Restart condition is generated
05h IOCON during a data transfer, the data will not be written to the
06h GPPU MCP23009.
07h INTF Both Byte mode and Sequential mode are supported
08h INTCAP (read-only) by the MCP23009. If Sequential mode is enabled
09h GPIO (default), the MCP23009 increments its address
0Ah OLAT counter after each ACK during the data transfer.

1.3.2.2 I2C Read Operation

1.3.1 BYTE MODE AND SEQUENTIAL
I2C read operations include the control byte sequence,
MODE as shown in the bottom of Figure 1-1. This sequence is
The MCP23X09 has the ability to operate in Byte mode followed by another control byte (including the Start
or Sequential mode (IOCON.SEQOP). Byte mode and condition and ACK) with the R/W bit equal to a logic
Sequential mode are not to be confused with I2C byte one (R/W = 1). The MCP23009 then transmits the data
operations and sequential operations. The modes contained in the addressed register. The sequence is
explained here relate to the device’s internal address ended with the master generating a Stop or Restart
pointer and whether or not it is incremented after each condition.
byte is clocked on the serial interface.
1.3.2.3 I2C Sequential Write/Read
• Byte mode disables automatic address pointer
incrementing. When operating in Byte mode, the For sequential operations (Write or Read), instead of
MCP23X09 does not increment its internal transmitting a Stop or Restart condition after the data
address counter after each byte during the data transfer, the master clocks the next byte pointed to by
transfer. This gives the ability to continually the address pointer (see Section 1.3.1 “Byte Mode
access the same address by providing extra and Sequential Mode” for details regarding sequential
clocks (without additional control bytes). This is operation control).
useful for polling the GPIO register for data The sequence ends with the master sending a Stop or
changes or for continually writing to the output Restart condition.
latches.
The MCP23009 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.

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 MCP23009/MCP23S09
1.3.3 SPI INTERFACE 1.3.3.2 SPI Read Operation
The MCP23S09 operates in Mode 0,0 and Mode 1,1. The SPI read operation is started by lowering CS. The
The difference between the two modes is the idle state SPI read command (slave address with R/W bit set) is
of the clock. then clocked into the device. The opcode is followed by
• Mode 0,0: The idle state of the clock is low. Input an address, with at least one data byte being clocked
data is latched on the rising edge of the clock; out- out of the device.
put data is driven on the falling edge of the clock.
1.3.3.3 SPI Sequential Write/Read
• Mode 1,1: The idle state of the clock is high. Input
data is latched on the rising edge of the clock; out- For sequential operations, instead of deselecting the
put data is driven on the falling edge of the clock. device by raising CS, the master clocks the next byte
pointed to by the address pointer (see Section 1.3.1
1.3.3.1 SPI Write Operation “Byte Mode and Sequential Mode” for details
regarding sequential operation control).
The SPI write operation is started by lowering CS. The
write command (slave address with R/W bit cleared) is The sequence ends by the raising of CS.
then clocked into the device. The opcode is followed by The MCP23S09 address pointer will roll over to
an address and at least one data byte. address zero after reaching the last register address.

 2009-2014 Microchip Technology Inc. DS20002121C-page 7

MCP23009/MCP23S09
FIGURE 1-1: MCP23009 I2C™ DEVICE PROTOCOL

S OP W ADDR DIN .... DIN P

SR OP R DOUT .... DOUT P

SR OP W ADDR .... DIN P

S OP R DOUT .... DOUT P

SR OP R DOUT .... DOUT P

SR OP W ADDR DIN .... DIN P

Byte and Sequential Write

Byte S OP W ADDR DIN P

Sequential S OP W ADDR DIN .... DIN P

Byte and Sequential Read

Byte S OP W ADDR SR OP R DOUT P

Sequential S OP W ADDR SR OP R DOUT .... DOUT P

Legend:

S - Start
OP - Device opcode
SR - Restart
ADDR - Device address
P - Stop
DOUT - Data out from MCP23009
W - Write
DIN - Data in to MCP23009
R - Read

DS20002121C-page 8  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
1.4 Multi-Bit Address Decoder 1.4.1 CALCULATING VOLTAGE ON ADDR
The ADDR pin is used to set the slave address of the When calculating the required voltage on the ADDR pin
MCP23009 (I2C only) to allow up to eight devices on (V2), the set point should be the mid point of the LSb of
the bus using only a single pin. Typically, this would the ADC.
require three pins. The examples in Figures 1-2 and 1-3 show how to
The multi-bit Address Decoder employs a basic FLASH determine the mid-point voltage (V2) and the range of
ADC architecture (Figure 1-4). The seven comparators voltages based on a voltage divider circuit. The
generate eight unique values based on the analog maximum tolerance is 20%, however, it is
input. This value is converted to a 3-bit code which recommended to use 5% tolerance worst-case (10%
corresponds to the address bits (A2, A1, A0) in the total tolerance).
serial OPCODE.
Sequence of operation (see Figure 1-5 for
timings):
1. Upon power-up (after VDD stabilizes), the
module becomes active after time tADEN. Note
that the analog value on the ADDR pin must be
stable before this point to ensure accurate
address assignment.
2. The 3-bit address is latched after tADDRLAT.
3. The module powers down after the first rising
edge of the serial clock is detected (tADDIS).
Once the address bits are latched, the device will keep
the slave address until a POR or Reset condition
occurs.

FIGURE 1-2: VOLTAGE DIVIDER EXAMPLE

VDD VDD
ADDR MCP23009 Only

A0
R1 A1
A2

V2

R2

VSS

VSS

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MCP23009/MCP23S09
FIGURE 1-3: VOLTAGE AND CODE EXAMPLE

Assume:
n = A2, A1, A0 in opcode
ratio = R2/(R1+R2)
V2 = voltage on ADDR pin
V2(min) = V2 – (VDD/8) x %tolerance
V2(max) = V2 + (VDD/8) x %tolerance

VDD = 1.8 10% Tolerance (total)

n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.113 0.00 0.14
1 3 13 0.1875 0.338 0.32 0.36
2 5 11 0.3125 0.563 0.54 0.59
3 7 9 0.4375 0.788 0.77 0.81
4 9 7 0.5625 1.013 0.99 1.04
5 11 5 0.6875 1.238 1.22 1.26
6 13 3 0.8125 1.463 1.44 1.49
7 15 1 0.9375 1.688 1.67 1.80

VDD = 2.7 10% Tolerance (total)

n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.169 0.00 0.19
1 3 13 0.1875 0.506 0.48 0.53
2 5 11 0.3125 0.844 0.82 0.87
3 7 9 0.4375 1.181 1.16 1.20
4 9 7 0.5625 1.519 1.50 1.54
5 11 5 0.6875 1.856 1.83 1.88
6 13 3 0.8125 2.194 2.17 2.22
7 15 1 0.9375 2.531 2.51 2.70

VDD = 3.3 10% Tolerance (total)

n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.206 0.00 0.23
1 3 13 0.1875 0.619 0.60 0.64
2 5 11 0.3125 1.031 1.01 1.05
3 7 9 0.4375 1.444 1.42 1.47
4 9 7 0.5625 1.856 1.83 1.88
5 11 5 0.6875 2.269 2.25 2.29
6 13 3 0.8125 2.681 2.66 2.70
7 15 1 0.9375 3.094 3.07 3.30

VDD = 5.5 10% Tolerance (total)

n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.344 0.00 0.37
1 3 13 0.1875 1.031 1.01 1.05
2 5 11 0.3125 1.719 1.70 1.74
3 7 9 0.4375 2.406 2.38 2.43
4 9 7 0.5625 3.094 3.07 3.12
5 11 5 0.6875 3.781 3.76 3.80
6 13 3 0.8125 4.469 4.45 4.49
7 15 1 0.9375 5.156 5.13 5.50

DS20002121C-page 10  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
FIGURE 1-4: FLASH ADC BLOCK DIAGRAM

VDD

ADDR

+ addr_out 6 addr<6:0> i2c_addr<2:0>

d q
-
adc_en adc_en
en
+ addr_out 5
-
adc_en reset
+ addr_out 4 set adc_en
'0' d q
-
adc_en
i2c_clk
+ addr_out 3
-
adc_en
+ addr_out 2
-
adc_en
+ addr_out 1
-
adc_en
+ addr_out 0
-
adc_en

adc_en

VSS

 2009-2014 Microchip Technology Inc. DS20002121C-page 11

MCP23009/MCP23S09
FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING

tADEN
VDD

tADDRLAT
adc_en

i2c_addr[2:0]
tADDIS

i2c_clk

1.4.2 ADDRESSING I2C DEVICES FIGURE 1-6: I2C™ CONTROL BYTE

(MCP23009) FORMAT
The MCP23009 is a slave I2C device that supports 7-bit
slave addressing, with the read/write bit filling out the Control Byte
control byte. The slave address contains four fixed bits S 0 1 0 0 A2 A1 A0 R/W ACK
and three user-defined hardware address bits
(configured via the ADDR pin). Figure 1-6 shows the Slave Address
control byte format.
Start R/W bit
1.4.3 ADDRESSING SPI DEVICES bit ACK bit
(MCP23S09) R/W = 0 = write
R/W = 1 = read
The MCP23S09 is a slave SPI device. The slave
address contains seven fixed bits (no address bits),
with the read/write bit filling out the control byte. FIGURE 1-7: SPI CONTROL BYTE
Figure 1-7 shows the control byte format. FORMAT

CS

Control Byte
0 1 0 0 0 0 0 R/W
Slave Address

R/W bit
R/W = 0 = write
R/W = 1 = read

DS20002121C-page 12  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
FIGURE 1-8: I2C™ ADDRESSING REGISTERS

S 0 1 0 0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

R/W = 0
Device Opcode Register Address

The ACKs are provided by the MCP23009.

FIGURE 1-9: SPI ADDRESSING REGISTERS

CS

0 1 0 0 0 0 0 R/W A7 A6 A5 A4 A3 A2 A1 A0

Device Opcode Register Address

 2009-2014 Microchip Technology Inc. DS20002121C-page 13

MCP23009/MCP23S09
1.5 GPIO Port
The GPIO module is a general purpose 8-bit wide
bidirectional port.
The outputs are open-drain.
The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).
The pull-up resistors are individually configured and
can be enabled when the pin is configured as an input
or output.
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.
Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high impedance.

DS20002121C-page 14  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
1.6 Configuration and Control
Registers
There are eleven (11) registers associated with the
MCP23X09, as shown in Table 1-4.

TABLE 1-4: CONFIGURATION AND CONTROL REGISTERS

Register Address POR/RST
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name (hex) Value
IODIR 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOL 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTEN 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVAL 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCON 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 05 — — SEQOP — — ODR INTPOL INTCC 0000 0000
GPPU 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTF 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAP 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIO 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLAT 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

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MCP23009/MCP23S09
1.6.1 I/O DIRECTION REGISTER
This register controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.

REGISTER 1-1: IODIR – I/O DIRECTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IO<7:0>: Controls the direction of data I/O <7:0>

1 = Pin is configured as an input
0 = Pin is configured as an output

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 MCP23009/MCP23S09
1.6.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.

REGISTER 1-2: IPOL – INPUT POLARITY PORT REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IP<7:0>: Controls the polarity inversion of the input pins <7:0>
1 = GPIO register bit will reflect the opposite logic state of the input pin
0 = GPIO register bit will reflect the same logic state of the input pin

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MCP23009/MCP23S09
1.6.3 INTERRUPT-ON-CHANGE
CONTROL REGISTER
The GPINTEN register controls the
Interrupt-on-Change feature for each pin.
If a bit is set, the corresponding pin is enabled for
Interrupt-on-Change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for Interrupt-on-Change.

REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 GPINT<7:0>: General-purpose I/O interrupt-on-change pins <7:0>

1 = Enable GPIO input pin for Interrupt-on-Change event
0 = Disable GPIO input pin for Interrupt-on-Change event

Refer to the INTCON and DEFVAL registers.

DS20002121C-page 18  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
1.6.4 DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
Interrupt to occur.

REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 DEF<7:0>: Sets the compare value for pins configured for Interrupt-on-Change from defaults <7:0>.
Refer to the INTCON register.
If the associated pin level is the opposite from the register bit, an Interrupt occurs.

Refer to the INTCON and GPINTEN registers.

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MCP23009/MCP23S09
1.6.5 INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin
value is compared for the Interrupt-on-Change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is compared
against the previous value.

REGISTER 1-5: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IOC<7:0>: Controls how the associated pin value is compared for Interrupt-on-Change <7:0>.
1 = Pin value is compared against the associated bit in the DEFVAL register
0 = Pin value is compared against the previous pin value

Refer to the DEFVAL and GPINTEN registers.

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 MCP23009/MCP23S09
1.6.6 CONFIGURATION REGISTER The Interrupt Polarity (INTPOL) bit sets the polarity of
the INT pin. This bit is functional only when the ODR bit
The Sequential Operation (SEQOP) bit controls the
is cleared, configuring the INT pin as active push-pull.
incrementing function of the address pointer. If the
address pointer is disabled, the address pointer does The Interrupt Clearing Control (INTCC) bit configures
not automatically increment after each byte is clocked how Interrupts are cleared. When set (INTCC = 1), the
during a serial transfer. This feature is useful when it is Interrupt is cleared when the INTCAP register is read.
desired to continuously poll (read) or modify (write) a When cleared (INTCC = 0), the Interrupt is cleared
register. when the GPIO register is read.
The Open-Drain (ODR) control bit enables/disables the The Interrupt can only be cleared when the Interrupt
INT pin for open-drain configuration. condition is inactive. Refer to Section 1.7.4 “Clearing
Interrupts” for details.

REGISTER 1-6: IOCON – I/O EXPANDER CONFIGURATION REGISTER

U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — SEQOP — — ODR INTPOL INTCC
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 Unimplemented: Read as ‘0’
bit 5 SEQOP: Sequential Operation mode bit.
1 = Sequential operation disabled, address pointer does not increment
0 = Sequential operation enabled, address pointer increments
bit 4 Unimplemented: Read as ‘0’
bit 3 Unimplemented: Read as ‘0’
bit 2 ODR: Configures the INT pin as an open-drain output.
1 = Open-drain output (overrides the INTPOL bit)
0 = Active driver output (INTPOL bit sets the polarity)
bit 1 INTPOL: Sets the polarity of the INT output pin.
1 = Active-High
0 = Active-Low
bit 0 INTCC: Interrupt Clearing Control
1 = Reading INTCAP register clears the Interrupt
0 = Reading GPIO register clears the Interrupt

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MCP23009/MCP23S09
1.6.7 PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set, the corresponding port pin is
internally pulled up with an internal resistor.

REGISTER 1-7: GPPU – GPIO PULL-UP RESISTOR REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PU<7:0>: Controls the internal pull-up resistors on each pin (when configured as an input or output)
<7:0>.
1 = Pull-Up enabled
0 = Pull-Up disabled

FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS
GPIO Pin Internal Pull-Up Current vs. VDD
400
350
T = -40°C
300
250
IPU (µA)

T = +25°C
200
150
T = +125°C
100
T = +85°C
50
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)

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 MCP23009/MCP23S09
1.6.8 INTERRUPT FLAG REGISTER
The INTF register reflects the Interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the Interrupt.
This register is read-only. Writes to this register will be
ignored.

REGISTER 1-8: INTF – INTERRUPT FLAG REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 INT<7:0>: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are
enabled (GPINTEN) <7:0>.
1 = Pin caused Interrupt
0 = Interrupt not pending

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MCP23009/MCP23S09
1.6.9 INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at
the time the Interrupt occurred. The register is
read-only’ and is updated only when an Interrupt
occurs. The register will remain unchanged until the
Interrupt is cleared via a read of INTCAP or GPIO.

REGISTER 1-9: INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER

R-x R-x R-x R-x R-x R-x R-x R-x
ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ICP<7:0>: Reflects the logic level on the port pins at the time of Interrupt due to pin change <7:0>.
1 = Logic-High
0 = Logic-Low

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 MCP23009/MCP23S09
1.6.10 PORT REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.

REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 GP<7:0>: Reflects the logic level on the pins <7:0>.
1 = Logic-High
0 = Logic-Low

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MCP23009/MCP23S09
1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.

REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 OL<7:0>: Reflects the logic level on the output latch <7:0>.
1 = Logic-High
0 = Logic-Low

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 MCP23009/MCP23S09
1.7 Interrupt Logic 1.7.4 CLEARING INTERRUPTS
If enabled, the MCP23X09 activates the INT interrupt The Interrupt will remain active until the INTCAP or
output when one of the port pins changes state or when GPIO register is read (depending on IOCON.INTCC).
a pin does not match the pre-configured default. Each Writing to these registers will not affect the Interrupt.
pin is individually configurable as follows: The Interrupt condition will be cleared after the LSb of
the data is clocked out during a read operation of GPIO
• Enable/disable interrupt via GPINTEN or INTCAP (depending on IOCON.INTCC).
• Can Interrupt on either pin change or change from
default as configured in DEFVAL Note: Assuming IOCON.INTCC = 0 (INT
Both conditions are referred to as Interrupt-on-Change cleared on GPIO read), the value in
(IOC). INTCAP can be lost if GPIO is read before
INTCAP while another IOC is pending.
The Interrupt Control Module uses the following
After reading GPIO, the Interrupt will clear
registers/bits:
and then set due to the pending IOC,
• GPINTEN – Interrupt enable register causing the INTCAP register to update.
• INTCON – Controls the source for the IOC
• DEFVAL – Contains the register default for IOC
operation
• IOCON (ODR and INTPOL) – Configures the INT
pin as push-pull, open-drain and active level (high
or low).

1.7.1 IOC FROM PIN CHANGE

If enabled, the MCP23X09 will generate an Interrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. See the GPINTEN and INTCON
registers.

1.7.2 IOC FROM REGISTER DEFAULT

If enabled, the MCP23X09 will generate an Interrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC-enabled pins will be compared. See
the GPINTEN, INTCON and DEFVAL registers.

1.7.3 INTERRUPT OPERATION

The INT interrupt output can be configured as
active-low, active-high or open-drain via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with Interrupt-on-Change (IOC) enabled
(GPINTEN register) can cause an Interrupt. Pins
configured as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC will generate an internal device Interrupt and
the device will capture the value of the port and copy it
into INTCAP.
The first Interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
Interrupt conditions on the port will not cause an
Interrupt to occur as long as the Interrupt is not cleared
by a read of INTCAP or GPIO.

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MCP23009/MCP23S09
1.7.5 INTERRUPT CONDITIONS FIGURE 1-11: INTERRUPT-ON-PIN-CHANGE
There are two possible configurations to cause
Interrupts (configured via INTCON): GPx
1. Pins configured for Interrupt-on-Pin-Change
will cause an Interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an Interrupt occurs. For example, an INT ACTIVE ACTIVE
Interrupt occurs by an input changing from 1 to
0. The new initial state for the pin is a logic 0. Port value Read GPIO Port value
is captured or INTCAP is captured
2. Pins configured for Interrupt-on-Change from
into INTCAP into INTCAP
register value will cause an Interrupt to occur if
the corresponding input pin differs from the
register bit. The Interrupt condition will remain FIGURE 1-12: INTERRUPT-ON-CHANGE
as long as the condition exists, regardless of
FROM REGISTER
whether the INTAP or GPIO is read.
DEFAULT
See Figures 1-11 and 1-12 for more information on the
interrupt operations. DEFVAL
GP: 7 6 5 4 3 2 1 0

X X X X X 1 X X

GP2

INT ACTIVE ACTIVE

Port value
is captured Read GPIO
into INTCAP or INTCAP
(INT clears only if Interrupt
condition does not exist.)

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 MCP23009/MCP23S09
2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.0V
Voltage on RESET with respect to VSS ..................................................................................................... -0.3V to +14V
Voltage on all other pins with respect to VSS (except VDD and GPIOA/B) ..................................... -0.6V to (VDD + 0.6V)
Voltage on GPIO Pins .................................................................................................................................. -0.6V to 5.5V
Total power dissipation (Note 1) ..........................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................200 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD)  20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)   20 mA
Maximum output current sunk by any output pin ....................................................................................................25 mA
Maximum output current sunk by any output pin (VDD = 1.8V) ...............................................................................10 mA
ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.

Note 1: Power dissipation is calculated as follows:

PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL).

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MCP23009/MCP23S09
2.1 DC Characteristics
Electrical Characteristics: Unless otherwise indicated, all limits are specified
DC Characteristics
for 1.8V  VDD  5.5V at -40C  TA  +125C.
Param.
Characteristic Sym. Min. Typ.(2) Max. Units Conditions
No.
D001 Supply Voltage VDD 1.8 — 5.5 V
D002 VDD Start Voltage VPOR — VSS — V
to Ensure Power-On Reset
D003 VDD Rise Rate to Ensure SVDD 0.05 — — V/ms Design guidance only.
Power-On Reset Not tested.
D004 Supply Current IDD — — 1 mA SCL/SCK = 1 MHz
D005 Standby (Idle) current IDDS — — 1 µA –40°C  TA  +85°C
— — 6 µA +85°C  TA  +125°C
Input Low-Voltage
D031 CS, GPIO, SCL/SCK, VIL VSS — 0.2 VDD V
SDA, SI, RESET
Input High-Voltage
D041 CS, SCL/SCK, SDA, SI, VIH 0.8 VDD — VDD V
RESET
GPIO VIH 0.8 VDD — 5.5 V
Input Leakage Current
D060 I/O port pins IIL — — ±1 µA VSS  VPIN  VDD
Output Leakage Current
D065 I/O port pins ILO — — ±1 µA VSS  VPIN  VDD
D070 GPIO internal pull-up IPU — 220 — µA VDD = 5V, GP Pins = VSS
current (Note 1)
Output Low-Voltage
D080 GPIO VOL — — 0.6 V IOL = 8.5 mA, VDD = 4.5V
(open-drain)
INT — — 0.6 IOL = 1.6 mA, VDD = 4.5V
SO, SDA — — 0.6 IOL = 3.0 mA, VDD = 1.8V
SDA — — 0.8 IOL = 3.0 mA, VDD = 4.5V
Output High-Voltage
D090 INT, SO VOH VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V
VDD – 0.7 — — IOH = -400 µA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101 GPIO, SO, INT CIO — — 50 pF These are load conditions for
D102 SDA CB — — 400(1) the timing specifications.
Refer to Figure 2-1.
SDA test condition is 135 pF.
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.

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 MCP23009/MCP23S09
2.2 AC CHARACTERISTICS

FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

VDD

Pin
1 k
SCL and 50 pF
SDA pin
MCP23009
135 pF

FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING

VDD

RESET
30 32
31

Internal
RESET

34

Output pin

TABLE 2-1: RESET AND DEVICE RESET TIMER REQUIREMENTS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for
AC Characteristics
1.8V  VDD  5.5V at -40C  TA  +125C.
Param.
Sym. Characteristic Min. Typ.(2) Max. Units Conditions
No.
30 TRSTL RESET Pulse Width (low) 1 — — µs VDD = 5.0V
32 THLD Device active after reset high — 0 — µs VDD = 5.0V
31 TPOR POR at device power-up — 20 — µs VDD = 5.0V
34 TIOZ Output high-impedance from — — 1 µs
RESET Low
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.

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MCP23009/MCP23S09
TABLE 2-2: GP AND INT PINS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
AC Characteristics
1.8V  VDD  5.5V at -40C  TA  +125C.
Param.
Sym. Characteristic Min. Typ.(2) Max. Units Conditions
No.
50 tGPOV Serial data to output valid — — 500 ns
51 tINTD Interrupt pin disable time — — 600 ns
52 tGPIV GP input change to register valid — 450 — ns Note 1
53 tGPINT IOC event to INT active — — 600 ns
54 tGLITCH Glitch filter on GP pins — — 50 ns Note 1
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.

FIGURE 2-3: GPIO AND INT TIMING

SCL

SDA
In D1 D0

LSb of data byte zero

during a write or read
command, depending
on parameter 50

GPn
Output
Pin

51
INT
Pin
INT pin active INT pin
inactive

53
GPn
Input
Pin

52

Register
Loaded

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 MCP23009/MCP23S09
TABLE 2-3: HARDWARE ADDRESS LATCH TIMING
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
AC Characteristics
1.8V  VDD  5.5V at -40C  TA  +125C.
Param.
Sym. Characteristic Min. Typ.(2) Max. Units Conditions
No.
40 tADEN Time from VDD stable after — 0 — µs Note 1
POR to ADC enable
41 tADDRLAT Time from ADC enable to — 50 — ns Note 1
address decode and latch
42 tADDIS Time from raising edge of — 10 — ns Note 1
serial clock to ADC disable
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.

FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING

40
VDD

41
adc_en

i2c_addr[2:0]
42

SCL

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MCP23009/MCP23S09
FIGURE 2-5: I2C™ BUS START/STOP BITS TIMING

SCL
91 93
90 92

SDA

Start Stop
Condition Condition
Note 1: Refer to Figure 2-1 for load conditions.

FIGURE 2-6: I2C™ BUS DATA TIMING

103 100 102
101
SCL
90 106
91 107 92
SDA
In
109 109 110
SDA
Out
Note 1: Refer to Figure 2-1 for load conditions.

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 MCP23009/MCP23S09
TABLE 2-4: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Electrical Characteristics: Unless otherwise indicated, all limits are
I2C™ AC Characteristics specified for 1.8V  VDD  5.5V at -40C  TA  +125C,
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF.
Param.
Characteristic Sym. Min. Typ. Max. Units Conditions
No.
100 Clock High Time: THIGH
100 kHz mode 4.0 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.06 — — µs 2.7V – 5.5V
101 Clock Low Time: TLOW
100 kHz mode 4.7 — — µs 1.8V – 5.5V
400 kHz mode 1.3 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
102 SDA and SCL Rise Time: TR
100 kHz mode (Note 1) — — 1000 ns 1.8V – 5.5V
400 kHz mode 20 + 0.1 CB(2) — 300 ns 1.8V – 5.5V
3.4 MHz mode 10 — 80 ns 2.7V – 5.5V
103 SDA and SCL Fall Time: TF
100 kHz mode (Note 1) — — 300 ns 1.8V – 5.5V
400 kHz mode 20 + 0.1 CB(2) — 300 ns 1.8V – 5.5V
3.4 MHz mode 10 — 80 ns 2.7V – 5.5V
90 Start Condition Setup Time: TSU:STA
100 kHz mode 4.7 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
91 Start Condition Hold Time: THD:STA
100 kHz mode 4.0 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
106 Data Input Hold Time: THD:DAT
100 kHz mode 0 — 3.45 µs 1.8V – 5.5V
400 kHz mode 0 — 0.9 µs 1.8V – 5.5V
3.4 MHz mode 0 — 0.07 µs 2.7V – 5.5V
107 Data Input Setup Time: TSU:DAT
100 kHz mode 250 — — ns 1.8V – 5.5V
400 kHz mode 100 — — ns 1.8V – 5.5V
3.4 MHz mode 0.01 — — µs 2.7V – 5.5V
92 Stop Condition Setup Time: TSU:STO
100 kHz mode 4.0 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified from 10 to 400 (pF).
3: This parameter is not applicable in high-speed mode (3.4 MHz).

 2009-2014 Microchip Technology Inc. DS20002121C-page 35

MCP23009/MCP23S09
TABLE 2-4: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, all limits are
I2C™ AC Characteristics specified for 1.8V  VDD  5.5V at -40C  TA  +125C,
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF.
Param.
Characteristic Sym. Min. Typ. Max. Units Conditions
No.
109 Output Valid From Clock: TAA
100 kHz mode — — 3.45 µs 1.8V – 5.5V
400 kHz mode — — 0.9 µs 1.8V – 5.5V
3.4 MHz mode — — 0.18 µs 2.7V – 5.5V
110 Bus Free Time: TBUF
100 kHz mode (Note 3) 4.7 — — µs 1.8V – 5.5V
400 kHz mode 1.3 — — µs 1.8V – 5.5V
3.4 MHz mode N/A — N/A µs 2.7V – 5.5V
Bus Capacitive Loading: CB
100 kHz and 400 kHz (Note 2) — — 400 pF Note 1
3.4 MHz — — 100 pF Note 1
Input Filter Spike TSP
Suppression: (SDA and SCL)
100 kHz and 400 kHz — — 50 ns Note 1
3.4 MHz — — 10 ns Note 1
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified from 10 to 400 (pF).
3: This parameter is not applicable in high-speed mode (3.4 MHz).

FIGURE 2-7: SPI INPUT TIMING

3
CS
11
1 6 10
Mode 1,1 7 2
SCK Mode 0,0

4 5
SI
MSB in LSB in

SO high impedance

DS20002121C-page 36  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
FIGURE 2-8: SPI OUTPUT TIMING

CS

2
8 9
SCK Mode 1,1
Mode 0,0

12
14
13
SO MSB out LSB out

don’t care
SI

 2009-2014 Microchip Technology Inc. DS20002121C-page 37

MCP23009/MCP23S09
TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, all limits are specified
SPI Interface AC Characteristics
for 1.8V  VDD  5.5V at -40C  TA  +125C.
Param.
Characteristic Sym. Min. Typ. Max. Units Conditions
No.
Clock Frequency FCLK — — 10 MHz 1.8V – 5.5V
1 CS Setup Time TCSS 50 — — ns
2 CS Hold Time TCSH 50 — — ns 1.8V – 5.5V
3 CS Disable Time TCSD 50 — — ns 1.8V – 5.5V
4 Data Setup Time TSU 10 — — ns 1.8V – 5.5V
5 Data Hold Time THD 10 — — ns 1.8V – 5.5V
6 CLK Rise Time TR — — 2 µs Note 1
7 CLK Fall Time TF — — 2 µs Note 1
8 Clock High Time THI 45 — — ns 1.8V – 5.5V
9 Clock Low Time TLO 45 — — ns 1.8V – 5.5V
10 Clock Delay Time TCLD 50 — — ns
11 Clock Enable Time TCLE 50 — — ns
12 Output Valid from Clock TV — — 45 ns 1.8V – 5.5V
Low
13 Output Hold Time THO 0 — — ns
14 Output Disable Time TDIS — — 100 ns
Note 1: This parameter is characterized, not 100% tested.

FIGURE 2-9: TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12)

TV vs. VDD
40
35
30 T = +125°C

25
TV (ns)

T = +85°C
20 T = -40°C

15
10
T = +25°C
5
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)

DS20002121C-page 38  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
16-Lead QFN (3x3x0.9 mm) Example

2S9
EYWW E432
256

18-Lead PDIP (300 mil) Example

MCP23S09
E/P e
^^3
1432256

18-Lead SOIC (7.50 mm) Example

MCP23S09
e3
E/SO ^^
1432
256

20-Lead SSOP (5.30 mm) Example

MCP23009
E/SS e
^^3
1432256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2009-2014 Microchip Technology Inc. DS20002121C-page 39

MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002121C-page 40  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002121C-page 41

MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002121C-page 42  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09

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 2009-2014 Microchip Technology Inc. DS20002121C-page 43

MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002121C-page 44  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002121C-page 45

MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002121C-page 46  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

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1 2
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0ROGHG3DFNDJH:LGWK (   
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 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
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5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

 2009-2014 Microchip Technology Inc. DS20002121C-page 47

MCP23009/MCP23S09

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002121C-page 48  2009-2014 Microchip Technology Inc.

 MCP23009/MCP23S09
APPENDIX A: REVISION HISTORY

Revision C (August 2014)

The following is the list of modifications:
1. Added ESD data in the Absolute Maximum
Ratings (†) section.
2. Updated Figure 1-1.
3. Updated the DC Characteristics table.
4. Updated the Package Marking Information
section.
5. Minor typographical changes.

Revision B (May 2009)

The following is the list of modifications:
1. Added the 3x3 QFN package (MG package
marking).
2. Updated Revision History.

Revision A (December 2008)

• Original Release of this Document.

 2009-2014 Microchip Technology Inc. DS20002121C-page 49

MCP23009/MCP23S09
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. -X /XX Examples:

a) MCP23009-E/MG: Extended Temperature,
Device Temperature Package
16LD QFN package
Range
b) MCP23009-E/P: Extended Temperature,
18LD PDIP package
Device: MCP23009: 8-Bit I/O Expander w/ I2C™ Interface c) MCP23009-E/SO: Extended Temperature,
MCP23009T: 8-Bit I/O Expander w/ I2C Interface 18LD SOIC package
(Tape and Reel) d) MCP23009T-E/SO: Tape and Reel,
MCP23S09: 8-Bit I/O Expander w/ SPI Interface Extended Temperature,
MCP23S09T: 8-Bit I/O Expander w/ SPI Interface 18LD SOIC package
(Tape and Reel) e) MCP23009-E/SS: Extended Temperature,
20LD SSOP package
Temperature E = -40C to +125C (Extended) f) MCP23009T-E/SS: Tape and Reel,
Range: Extended Temperature,
20LD SSOP package

Package: MG = Plastic Quad Flat, No Lead Package – a) MCP23S09-E/MG: Extended Temperature,

3x3x0.9 mm Body, 16-Lead 16LD QFN package
P = Plastic Dual In-Line – 300 mil Body, 18-Lead b) MCP23S09T-E/MG: Tape and Reel,
SO = Plastic Small Outline – Wide, 7.50 mm Body, Extended Temperature,
18-Lead 16LD QFN package
SS = Lead Plastic Shrink Small Outline – c) MCP23S09-E/P: Extended Temperature,
5.30 mm Body, 20-Lead 18LD PDIP package
d) MCP23S09-E/SO: Extended Temperature,
18LD SOIC package
e) MCP23S09T-E/SO: Tape and Reel,
Extended Temperature,
18LD SOIC package

DS20002121C-page 50  2009-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-540-6

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2009-2014 Microchip Technology Inc. DS20002121C-page 51

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
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Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2943-5100 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/ Fax: 852-2401-3431
India - Pune France - Paris
support
Australia - Sydney Tel: 91-20-3019-1500 Tel: 33-1-69-53-63-20
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03/25/14
Fax: 86-756-3210049

DS20002121C-page 52  2009-2014 Microchip Technology Inc.