A B C D E

1 1

PWWHA
2 Delhi 10RG 2

LA-7201P REV 1.0 Schematic

3
Intel Processor(Sandy Bridge) / PCH(Cougar Point) 3

2011-01-31 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 1 of 53
A B C D E
 A B C D E

Fan Control Circuit

Intel CPU page 5

PCI-Express 8X 2.5GHz Sandy Bridge

1

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s

FDI X8 DMI X4
2.7GT/s 5GT/s
USB Port 2IN1 RTS5137 Int. Camera
VGA Board(GDDR3)
USB port 0,1 USB port 10 USB port 11
USB page 31 page 34 page 19
CRT
5V 480MHz
NVIDIA N12M-GE-S-B1 BGA 533P page 20

2 2
page 13,14,15,16,17,18 PCIeMini Card
USB WiMax USB port 9
5V 480MHz page 32
LVDS Conn.
page 19
PCIe 1x PCIeMini Card
1.5V 5GT/s
WLAN PCIe port 2
Intel PCH page 32

Cougar Point - M
RTL8105E 10/100M SATA port 0 SATA HDD
RJ45 PCIe 1x 5V 6GHz(600MB/s) SATA port 0
page 33 PCIe port 1 1.5V 5GT/s page 31
page 33
FCBGA-989
25mm*25mm SATA port 2 SATA ODD
5V 3GHz(300MB/s) SATA port 2
3
page 31 3

page 21,22,23,24,25,26,27,28,29

HD Audio 3.3V 24MHz

LPC BUS
3.3V 33 MHz
RTC CKT. HDA Codec
page 21 ALC259-VB5-GR
SPI ROM Debug Port ENE KB930 QFN 48P page 36
page 39 page 38
(4MB)
page 21
DC/DC Interface CKT.
page 41

Touch Pad Int.KBD EC ROM Ext. SPK Conn HP Conn

page 40 page 39
4 Power Circuit DC/DC (128KB) MIC Conn 4
page 39 page 37 page 37 page 37
page 42,43,44,45,46,
47,48,49,50

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/09/03 2012/12/31 Title
Power/B Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 40 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 2 of 53
A B C D E
 A B C D E

B+ DESIGN CURRENT 0.1A +3VL

Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 10A +5VALW
SUSP#

DESIGN CURRENT 1.8A +1.8VS

SY8033BDBC

1 SUSP 1

N-CHANNEL DESIGN CURRENT 5.5A +5VS

SI4800

Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 6A +3VALW

WOL_EN#

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

SUSP AO-3413

TPS51125ARGER N-CHANNEL DESIGN CURRENT 4.5A +3VS

SI4800 VGA_ENVDD

P-CHANNEL DESIGN CURRENT 2A +LCD_VDD

SUSP or 0.75VR_EN# AO-3413

DESIGN CURRENT 0.5A +0.75VS

G2992F1U
2 2

VR_ON
Ipeak=53A, Imax=36A, Iocp min=70A DESIGN CURRENT 53A +CPU_CORE
ISL95831CRZ-T
SUSP#

Ipeak=20A, Imax=14A, Iocp min=26A DESIGN CURRENT 21A +VGA_CORE

TPS51218DSCR

SUSP#
Ipeak=12.5A, Imax=8.75A, Iocp min=21.4A
DESIGN CURRENT 17A +1.05VS_VCCP
TPS5117
VCCPPWRGD

Ipeak=6A, Imax=4.2A, Iocp min=7.76A DESIGN CURRENT 6A +VCCSA

3 3
TPS51117

SYSON
Ipeak=16.5A, Imax=11.55A, Iocp min=21.03A
DESIGN CURRENT 20A +1.5V
TPS51117RGYR SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
SUSP

N-CHANNEL DESIGN CURRENT 0.7A +1.5VS

FDS6676AS

VGA_PWROK#

N-CHANNEL DESIGN CURRENT 3A +1.5V_MEM_GFX

4 4
FDS6676AS

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 3 of 53
A B C D E
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails
+5VS
+RTCVCC B+ +3VL +5VALW +1.5V
+3VS
+3VALW
+1.8VS
+VSB
1 power +1.5VS 1

plane +1.05VS
+0.75VS
+CPU_CORE
+GFX_CORE

State

BTO Option Table

Function DIS only MINI PCI-E SLOT LAN Camera & Mic

description SLOT1 LAN Camera & Mic

S0 explain WIMAX 10/100M Giga Camera & Mic

O O O O O O
BTO DIS@ WIMAX@ 8105ELDO@ 8105ESWR@ 8111E@ CAM@
2 S1 2
O O O O O O
S3 Function PCH HDMI/Non-HDMI EC Chip Zero ODD
O O O O O X
description 930 or 9012
S5 S4/AC
O O O O X X
explain 930 Complete Simple
S5 S4/ Battery only
O O O X X X BTO Q65R3@ HDMI@/NHDMI@ 930@ 9012@ S9012@ ZODD@

S5 S4/AC & Battery

don't exist
O X X X X X

PCH SM Bus Address

3 3
Power Device HEX Address
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
+3VS WLAN/WIMAX SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#

Full ON HIGH HIGH HIGH

S1(Power On Suspend) HIGH HIGH HIGH

EC SM Bus1 Address EC SM Bus2 Address S3 (Suspend to RAM) LOW HIGH HIGH

S4 (Suspend to Disk) LOW LOW HIGH

Power Device HEX Address Power Device HEX Address
S5 (Soft OFF) LOW LOW LOW
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
G3 LOW LOW LOW
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 4 of 53
A B C D E
 A B C D E

JCPUB
@ Stuff R41 and R42 if do not support eDP
1000P_0402_50V7K 2 1 C487 PM_DRAM_PW RGD_R 100 MHz
@ PROC_SELECT# A28 CLK_CPU_DMI +1.05VS_VCCP
BCLK CLK_CPU_DMI 22

MISC

CLOCKS
1000P_0402_50V7K 2 1 C488 H_PW RGOOD H_SNB_IVB# C26 A27 CLK_CPU_DMI#
25 H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_DMI# 22
120 MHz CLK_CPU_DPLL# R42 1 2 1K_0402_5%
T1 PAD TP_SKTOCC# AN34 SKTOCC# CLK_CPU_DPLL CLK_CPU_DPLL R41 1
DPLL_REF_SSCLK A16 2 1K_0402_5%
A15 CLK_CPU_DPLL#
DPLL_REF_SSCLK#
1 1
T2 PAD H_CATERR# AL33 CATERR#

THERMAL
H_PECI AN33 R8 H_DRAMRST#
38 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7

DDR3
MISC
R450
38,43 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R1437 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R1438 2
SM_RCOMP[1] A5 1 25.5_0402_1% Layout Note:Place these
A4 SM_RCOMP_2 R1439 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
H_THERMTRIP# AN32
26 H_THERMTRIP# THERMTRIP#

Remove R14(o ohm) for HW Review demand AP29 XDP_PRDY#_R R1 1 @ 2 0_0402_5% XDP_PRDY#
PRDY# XDP_PREQ#_R R2 1 @
PREQ# AP27 2 0_0402_5% XDP_PREQ#

AR26 XDP_TCK_R R4 1 @ 2 0_0402_5% XDP_TCK

TCK

PWR MANAGEMENT
XDP_TMS_R R6 1 @ 2 0_0402_5% XDP_TMS

JTAG & BPM

TMS AR27
+1.05VS_VCCP H_PM_SYNC AM34 AP30 XDP_TRST#_R R7 1 @ 2 0_0402_5% XDP_TRST# Routed as a single daisy chain
23 H_PM_SYNC PM_SYNC TRST#
AR28 XDP_TDI_R R8 1 @ 2 0_0402_5% XDP_TDI
R47 TDI
2 1 62_0402_5% H_PROCHOT#
TDO AP26 XDP_TDO_R R10 1 @ 2 0_0402_5% XDP_TDO
26 H_PW RGOOD H_PW RGOOD AP33 R36
UNCOREPWRGOOD
1 2 +3VS
2 1K_0402_5% 2
R51 2 1 10K_0402_5% H_PW RGOOD AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# 23
PM_SYS_PW RGD_BUF 1 2 PM_DRAM_PW RGD_R V8
R454 130_0402_5% SM_DRAMPWROK
AT28 XDP_BPM#0_R R12 1 @ 2 0_0402_5% XDP_BPM#0
BPM#[0] XDP_BPM#1_R R13 1 @ 0_0402_5% XDP_BPM#1
BPM#[1] AR29 2
AR30 XDP_BPM#2_R R15 1 @ 2 0_0402_5% XDP_BPM#2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R R18 1 @ 0_0402_5% XDP_BPM#3
AR33 RESET# BPM#[3] AT30 2
PS3@ C93 AP32
0.1U_0402_16V4Z +3VALW +1.5V_CPU BPM#[4]
BPM#[5] AR31
2 1 AT31
BPM#[6]
FAN Control Circuit (RPM and PWM)
1

U10 AR32
74AHC1G09GW _TSSOP5 BPM#[7]
5

PS3@ R312 PS3@ R339 +5VS JFAN2 @

1 21 200_0402_5% 1A +FAN2 1
P

23,38 PM_PW ROK B 1

0_0402_5% 4 PM_SYS_PW RGD_BUF PU/PD for JTAG signals 2
2

O Sandy Bridge_rPGA_Rev0p61 @ 2
23 DRAMPW ROK 2 A 2 2 3 3
G

+1.05VS_VCCP C13 C15

R340 XDP_TMS_R R28 2 1 51_0402_5% 10U_0805_10V6K 1000P_0402_50V7K 4
3

39_0402_5% @ GND
5 GND
R384 @ XDP_TDI_R R29 1 1
2 1 51_0402_5% U1
1 2 0_0402_5% 1 8 ACES_85204-0300N
1 2

W PS3@ XDP_TDO R30 EN GND

D 2 1 51_0402_5% 2 VIN GND 7
+FAN2 3 6 R24 10K_0402_5%
SUSP Q5 XDP_TCK_R R31 VOUT GND
9,32,41,47 SUSP 2 2 1 51_0402_5% 38 EN_DFAN1 4 VSET GND 5 2 1 +3VS
G 2N7002_SOT23-3 10mil 1
S @ XDP_TRST#_R R32 2 1 51_0402_5% APL5607KI-TRG_SO8 FAN_SPEED1
3

C17 1
10U_0805_10V6K C14
3 2 0.01U_0402_25V7K 3
@
JXDP 2

Buffered Reset to CPU XDP Connector XDP_PREQ#

XDP_PRDY#
1
2
@

+3VS 3
XDP_BPM#0 4 +3VS
XDP_BPM#1 5
6
FAN Control Circuit

1
PLT_RST# 13,25,32,33,35,38,39
1 0.1U_0402_16V4Z XDP_BPM#2 7
C84 XDP_BPM#3 8 R1444
+1.05VS_VCCP 9 10K_0402_5%
H_PW RGOOD R35 1 @ 2 1K_0402_5%XDP_CPU_HOOK0 10 @ JFAN @
2 PBTN_OUT# R152 @ 0_0402_5% XDP_CPU_HOOK1
23,38 PBTN_OUT# 1 2 11 1

2
1
1

U3 CFG0 R37 1 @ 2 1K_0402_5%XDP_CPU_HOOK2 12 +5VS FANPW M 2

10 CFG0 38 FANPW M 2
1 R69 23,38,49 VGATE VGATE R451 1 @ 2 0_0402_5% XDP_CPU_HOOK3 13 3
OE# 75_0402_5% CLK_CPU_ITP +FAN1 3
VCC 5 22 CLK_CPU_ITP 14 38 FAN_SPEED1 1 4 4
CLK_CPU_ITP# 15 C899
22 CLK_CPU_ITP#
2 R155 +1.05VS_VCCP 16 1A R1445 0.01U_0402_25V7K ACES_85204-0400N
2

IN 43_0402_1% PLT_RST# @ XDP_CPU_HOOK6 +FAN1 @

1 2 17 1 2
BUFO_CPU_RST# BUF_CPU_RST# R40 1K_0402_5% XDP_DBRESET# 0_0603_5% 2
OUT 4 1 2 18 2
3 19 C902 @ +5VS
GND
1

XDP_TDO 20 40 mil D85

74AHC1G125GW _SOT353-5 R209 XDP_TRST# 21 10U_0805_10V6K 1 2

1
0_0402_5% XDP_TDI 1 @
1 22 2 1
@ C8 XDP_TMS 23 1SS355_SOD323-2 1000P_0402_50V7K
0.1U_0402_10V6K 24 @ D86 C901
2

@ 25 BAS16_SOT23-3 C900 @
2 XDP_TCK @ 1 2
26

2
4 4
27 10U_0805_10V6K
28 @

Close to Connector
MOLEX 52435-2671
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_JTAG/XDP/FAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 5 of 53
A B C D E
 A B C D E

PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical

1
impedance = 43 m ohm (4 mils)
R34
24.9_0402_1% PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)

2
1 J22 PEG_COMP 1
PEG_ICOMPI
PEG_ICOMPO J21
DMI_PTX_CRX_N0 B27 H22
23 DMI_PTX_CRX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_PTX_CRX_N1 B25
23 DMI_PTX_CRX_N1 DMI_RX#[1]
DMI_PTX_CRX_N2 A25
23 DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[8..15] 13
DMI_PTX_CRX_N3 B24 K33
23 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
PEG_RX#[1] M35
DMI_PTX_CRX_P0 B28 L34
23 DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2]
DMI_PTX_CRX_P1 B26 J35
23 DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]

DMI
DMI_PTX_CRX_P2 A24 J32
23 DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
DMI_PTX_CRX_P3 B23 H34
23 DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6] H31
DMI_CTX_PRX_N0 G21 G33
23 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
DMI_CTX_PRX_N1 E22 G30 PCIE_GTX_C_CRX_N8
23 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
DMI_CTX_PRX_N2 F21 F35 PCIE_GTX_C_CRX_N9
23 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
DMI_CTX_PRX_N3 D21 E34 PCIE_GTX_C_CRX_N10
23 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PCIE_GTX_C_CRX_N11
DMI_CTX_PRX_P0 PEG_RX#[11] PCIE_GTX_C_CRX_N12
23 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33
DMI_CTX_PRX_P1 D22 D31 PCIE_GTX_C_CRX_N13
23 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]

PCI EXPRESS* - GRAPHICS

DMI_CTX_PRX_P2 F20 B33 PCIE_GTX_C_CRX_N14
23 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
DMI_CTX_PRX_P3 C21 C32 PCIE_GTX_C_CRX_N15
23 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_C_CRX_P[8..15] 13
PEG_RX[0] J33
PEG_RX[1] L35
PEG_RX[2] K34
FDI_CTX_PRX_N0 A21 H35
23 FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
FDI_CTX_PRX_N1 H19 H32
23 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
FDI_CTX_PRX_N2 E19 G34
23 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
FDI_CTX_PRX_N3 F18 G31

Intel(R) FDI
23 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
2 FDI_CTX_PRX_N4 B21 F33 2
23 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
FDI_CTX_PRX_N5 C20 F30 PCIE_GTX_C_CRX_P8
23 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
FDI_CTX_PRX_N6 D18 E35 PCIE_GTX_C_CRX_P9
23 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
FDI_CTX_PRX_N7 E17 E33 PCIE_GTX_C_CRX_P10
23 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PCIE_GTX_C_CRX_P11
PEG_RX[11] PCIE_GTX_C_CRX_P12
PEG_RX[12] D34
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_C_CRX_P13
23 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 G19 C33 PCIE_GTX_C_CRX_P14
23 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
FDI_CTX_PRX_P2 E20 B32 PCIE_GTX_C_CRX_P15
23 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3 G18
23 FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[8..15] 13
FDI_CTX_PRX_P4 B20 M29
23 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 C19 M32
23 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
FDI_CTX_PRX_P6 D19 M31
23 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
FDI_CTX_PRX_P7 F17 L32
23 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
PEG_TX#[4] L29
23 FDI_FSYNC0 FDI_FSYNC0 J18 K31
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5]
23 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28
PEG_TX#[7] J30
23 FDI_INT FDI_INT H20 J28 PCIE_CTX_GRX_N8 C29 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N8
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N9 C30 .1U_0402_16V7K PCIE_CTX_C_GRX_N9
PEG_TX#[9] H29 1 2
23 FDI_LSYNC0 FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N10 C31 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N10
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N11 C32 .1U_0402_16V7K PCIE_CTX_C_GRX_N11
23 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2
F27 PCIE_CTX_GRX_N12 C33 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N12
PEG_TX#[12] PCIE_CTX_GRX_N13 C34 .1U_0402_16V7K PCIE_CTX_C_GRX_N13
PEG_TX#[13] D28 1 2
F26 PCIE_CTX_GRX_N14 C35 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N14
PEG_TX#[14] PCIE_CTX_GRX_N15 C36 .1U_0402_16V7K PCIE_CTX_C_GRX_N15
PEG_TX#[15] E25 1 2
+1.05VS_VCCP R9 1 2 24.9_0402_1% EDP_COMP A18 eDP_COMPIO PCIE_CTX_C_GRX_P[8..15] 13
A17 eDP_ICOMPO PEG_TX[0] M28
+1.05VS_VCCP R33 2 1 10K_0402_5% B16 M33
3 @ eDP_HPD PEG_TX[1] 3
PEG_TX[2] M30
PEG_TX[3] L31
C15 eDP_AUX PEG_TX[4] L28
Reserve R33 for HW Review demand D15 eDP_AUX# PEG_TX[5] K30
eDP

PEG_TX[6] K27
eDP_COMP signals should be PEG_TX[7] J29
C17 J27 PCIE_CTX_GRX_P8 C45 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P8
shorted near balls and F16
eDP_TX[0] PEG_TX[8]
H28 PCIE_CTX_GRX_P9 C46 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P9
eDP_TX[1] PEG_TX[9]
routed with typical C16 eDP_TX[2] PEG_TX[10] G28 PCIE_CTX_GRX_P10 C47 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P10
G15 E28 PCIE_CTX_GRX_P11 C48 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P11
impedance <25m ohm eDP_TX[3] PEG_TX[11]
F28 PCIE_CTX_GRX_P12 C49 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P12
PEG_TX[12] PCIE_CTX_GRX_P13 C50 .1U_0402_16V7K PCIE_CTX_C_GRX_P13
C18 eDP_TX#[0] PEG_TX[13] D27 1 2
E16 E26 PCIE_CTX_GRX_P14 C51 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P14
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P15 C52 .1U_0402_16V7K PCIE_CTX_C_GRX_P15
D16 eDP_TX#[2] PEG_TX[15] D25 1 2
F15 eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_DMI/PEG/FDI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 6 of 53
A B C D E
 A B C D E

JCPUC JCPUD
11 DDR_A_D[0..63]
12 DDR_B_D[0..63]

AB6 DDRA_CLK0 AE2 DDRB_CLK0

SA_CLK[0] DDRA_CLK0 11 SB_CLK[0] DDRB_CLK0 12
AA6 DDRA_CLK0# AD2 DDRB_CLK0#
SA_CLK#[0] DDRA_CLK0# 11 SB_CLK#[0] DDRB_CLK0# 12
DDR_A_D0 C5 V9 DDRA_CKE0 DDR_B_D0 C9 R9 DDRB_CKE0
SA_DQ[0] SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDRA_CLK1 DDR_B_D4 SB_DQ[3] DDRB_CLK1
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 11 A9 SB_DQ[4] SB_CLK[1] AE1 DDRB_CLK1 12
DDR_A_D5 C6 AB5 DDRA_CLK1# DDR_B_D5 A8 AD1 DDRB_CLK1#
SA_DQ[5] SA_CLK#[1] DDRA_CLK1# 11 SB_DQ[5] SB_CLK#[1] DDRB_CLK1# 12
1 DDR_A_D6 C2 V10 DDRA_CKE1 DDR_B_D6 D9 R10 DDRB_CKE1 1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6] SB_CKE[1] DDRB_CKE1 12
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] SA_CLK[2] AB4 F1 SB_DQ[10] SB_CLK[2] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] SA_CLK[3] AB3 J7 SB_DQ[16] SB_CLK[3] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDR_B_D18 SB_DQ[17] SB_CLK#[3]
K1 SA_DQ[18] SA_CKE[3] W10 K10 SB_DQ[18] SB_CKE[3] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDRA_SCS0# DDR_B_D22 SB_DQ[21] DDRB_SCS0#
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# 11 K8 SB_DQ[22] SB_CS#[0] AD3 DDRB_SCS0# 12
DDR_A_D23 K2 AL3 DDRA_SCS1# DDR_B_D23 K7 AE3 DDRB_SCS1#
SA_DQ[23] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[23] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDR_B_D25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDRA_ODT0 DDR_B_D29 SB_DQ[28] DDRB_ODT0
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 11 N5 SB_DQ[29] SB_ODT[0] AE4 DDRB_ODT0 12

DDR SYSTEM MEMORY B

DDR_A_D30 N9 AG3 DDRA_ODT1 DDR_B_D30 M2 AD4 DDRB_ODT1

DDR SYSTEM MEMORY A

SA_DQ[30] SA_ODT[1] DDRA_ODT1 11 SB_DQ[30] SB_ODT[1] DDRB_ODT1 12
DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR_A_D32 SA_DQ[31] SA_ODT[2] DDR_B_D32 SB_DQ[31] SB_ODT[2]
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
2 DDR_A_D35 AK5 DDR_B_D35 AP3 2
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 11 AN3 SB_DQ[36] DDR_B_DQS#[0..7] 12
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D38 SA_DQ[37] SA_DQS#[0] SB_DQ[37] SB_DQS#[0]
AJ5 SA_DQ[38] SA_DQS#[1] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[38] SB_DQS#[1] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D39 AP2 K6 DDR_B_DQS#2
DDR_A_D40 SA_DQ[39] SA_DQS#[2] SB_DQ[39] SB_DQS#[2]
AJ8 SA_DQ[40] SA_DQS#[3] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[40] SB_DQS#[3] N3 DDR_B_DQS#3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
DDR_A_D42 SA_DQ[41] SA_DQS#[4] SB_DQ[41] SB_DQS#[4]
AJ9 SA_DQ[42] SA_DQS#[5] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[42] SB_DQS#[5] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D43 AT6 AK12 DDR_B_DQS#6
DDR_A_D44 SA_DQ[43] SA_DQS#[6] SB_DQ[43] SB_DQS#[6]
AH8 SA_DQ[44] SA_DQS#[7] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[44] SB_DQS#[7] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 DDR_B_D45 AN8
DDR_A_D46 SA_DQ[45] DDR_B_D46 SB_DQ[45]
AL9 SA_DQ[46] AR6 SB_DQ[46]
DDR_A_D47 AL8 DDR_B_D47 AR5
DDR_A_D48 SA_DQ[47] DDR_B_D48 SB_DQ[47]
AP11 SA_DQ[48] DDR_A_DQS[0..7] 11 AR9 SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
SA_DQ[59] DDR_A_MA[0..15] 11 SB_DQ[59]
DDR_A_D60 AL14 DDR_B_D60 AT12
SA_DQ[60] SB_DQ[60] DDR_B_MA[0..15] 12
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
3 SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3 3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
11 DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 12 DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
DDR_A_BS1 AF10 V1 DDR_A_MA8 DDR_B_BS1 AA7 T5 DDR_B_MA8
11 DDR_A_BS1 SA_BS[1] SA_MA[8] 12 DDR_B_BS1 SB_BS[1] SB_MA[8]
DDR_A_BS2 V6 W5 DDR_A_MA9 DDR_B_BS2 R6 R3 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
11 DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 12 DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_RAS# AB8 R5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SA_MA[14] 12 DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_W E# AF9 V7 DDR_A_MA15 DDR_B_W E# AB9 R4 DDR_B_MA15
11 DDR_A_W E# SA_WE# SA_MA[15] 12 DDR_B_W E# SB_WE# SB_MA[15]

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @

+1.5V
1

R466
W PS3@ 0_0402_5% R465
1 2 1K_0402_5%
PS3@ R467
Q14 1K_0402_5%
2
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2

4 SM_DRAMRST# 11,12 4
2

BSS138_NL_SOT23-3
R464 PS3@
G
2

4.99K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

1

C140
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
1 2 DRAMRST_CNTRL 1 2
22 DRAMRST_CNTRL_PCH
R463 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_DDR3
PS3@ 0.047U_0402_25V6K Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PS3@ Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 7 of 53
A B C D E
 A B C D E

+CPU_CORE
JCPUF POWER
53A (SV 35W) +1.05VS_VCCP
8.5A TOP Socket Cavity x 7 +1.05VS_VCCP Decoupling:
2X 330U (6m ohm), 12X 22U
AG35 VCC1
AG34 AH13 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC2 VCCIO1
1 AG33 VCC3 VCCIO2 AH10 1 1 1 1 1 1 1 1 1 1 1
AG32 AG10 C146 C144 C143 C141 C137 C136 C135 C134 C133 C142
VCC4 VCCIO3
AG31
AG30
VCC5 VCCIO4 AC10
Y10
+CPU_CORE Decoupling:
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
AG29 VCC7 VCCIO6 U10 4X 470U (4m ohm), 16X 22U, 10X 10U
AG28 VCC8 VCCIO7 P10
AG27 L10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC9 VCCIO8
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AF34
AF33
VCC12 VCCIO11 J12
J11 1 1 1 1 1 1 1 1 1
Bottom Socket Cavity
VCC13 VCCIO12 C147 C145 C163 C153 C160 C152 C139 C138 C132
AF32 VCC14 VCCIO13 H14
AF31 H12 @ @ @ @ @ @ @
VCC15 VCCIO14 +CPU_CORE
AF30 VCC16 VCCIO15 H11
2 2 2 2 2 2 2 2 2
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
PEG AND DDR

AF27 G12 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13 1 1 1 1 1 1 1 1 1 1 1
AD34 F12 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111
VCC22 VCCIO21 330U_D2_2V_Y
AD33 VCC23 VCCIO22 F11
AD32 E14 @
VCC24 VCCIO23 ESR 9mohm 2 2 2 2 2 2 2 2 2 2 2
AD31 VCC25 VCCIO24 E12 1 1 1
AD30
AD29
VCC26
E11
Bottom Socket Cavity x 5 C10 + C11 + @ C12 + 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VCC27 VCCIO25
AD28 VCC28 VCCIO26 D14
AD27 D13 330U_D2_2V_Y
VCC29 VCCIO27 2 2 2
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 C13 330U_D2_2V_Y
VCC33 VCCIO31
AC32 VCC34 VCCIO32 C12
2 2
AC31
AC30
VCC35 VCCIO33 C11
B14
Top Socket Edge
VCC36 VCCIO34
AC29 VCC37 VCCIO35 B12
AC28 A14 +CPU_CORE
VCC38 VCCIO36
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 A11 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC41 VCCIO39
AA34 VCC42
AA33 VCC43 VCCIO40 J23 1 1 1 1 1 1 1 1 1
AA32 C159 C151 C130 C129 C124 C123 C122 C121 C125
VCC44
AA31 VCC45
AA30 @
VCC46 2 2 2 2 2 2 2 2 2
AA29 VCC47
AA28 VCC48
AA27 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC49
AA26 VCC50
CORE SUPPLY

Y35 VCC51
Y34 VCC52
Y33 VCC53 +1.05VS_VCCP +1.05VS_VCCP
Y32 VCC54 9/02 Remove C126, C131 by Power Demand
Y31 VCC55
Y30 VCC56 close to CPU Top Socket Cavity
1

Y29 VCC57
Y28 R70 R68
VCC58 130_0402_5% 75_0402_5% +CPU_CORE
Y27 VCC59
Y26 VCC60
V35
2

VCC61
SVID

V34 AJ29 H_CPU_SVIDALRT# 1 2 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

VCC62 VIDALERT# VR_SVID_ALRT# 49
V33 AJ30 H_CPU_SVIDCLK R67 1 2 43_0402_1%
VCC63 VIDSCLK VR_SVID_CLK 49
V32 AJ28 H_CPU_SVIDDAT R63 1 2 0_0402_5% 1 1 1 1 1 1 1 1
VCC64 VIDSOUT VR_SVID_DAT 49
V31 R66 0_0402_5% C158 C150 C128 C127 C120 C118 C119 C117
3 VCC65 3
V30 VCC66 Pull high resistor on VR side
V29 VCC67 2 2 2 2 2 2 2 2
V28 VCC68
V27 VCC69
V26 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC70
U35 VCC71
U34 VCC72
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29
U28
VCC77 Bottom Socket Edge
VCC78 +CPU_CORE
U27 VCC79
U26 VCC80 +CPU_CORE
R35 VCC81
R34 VCC82
2

R33 330U_D2_2V_Y 330U_D2_2V_Y

VCC83 R64
R32 VCC84 Close to CPU
R31 100_0402_1% 1 1 1 1 1
VCC85
R30 VCC86
R29 C2 + C5 + C7 + C9 + C3 +
1

VCC87
SENSE LINES

R28 VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R R65 1 2 0_0402_5% VCCSENSE 49
330U_D2_2V_Y
2 2 2 2 2
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R52 1 2 0_0402_5% VSSSENSE 49
P35 VCC91
P34 330U_D2_2V_Y 330U_D2_2V_Y
VCC92
1

P33 VCC93
P32 VCC94 VCCIO_SENSE B10 VCCIO_SENSE VCCIO_SENSE 47
R62
P31 A10 100_0402_1%
VCC95 VSSIO_SENSE
P30 VCC96
VSS_SENSE_VCCIO
2

4 P29 9/02 Add C898 3Pin Bulk Cap by Power Demand 4

2

VCC97 R102 R105

P28 VCC98
P27 0_0402_5% 100_0402_1% 9/02 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 for Power demand
VCC99 @
P26 VCC100
1

+1.05VS_VCCP
Security Classification Compal Secret Data Compal Electronics, Inc.
Close to CPU Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_POWER-1
Sandy Bridge_rPGA_Rev0p61 @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 8 of 53
A B C D E
 A B C D E

JCPUG
POWER
烉烉

SENSE
LINES
AT24 VAXG1 VAXG_SENSE AK35
AT23 VAXG2 VSSAXG_SENSE AK34 PS3@ short

2
AT21 VAXG3
R14 AT20 VAXG4 WPS3@ open
0_0402_5% AT18 VAXG5
AT17 VAXG6 33A +V_SM_VREF should PJ32
1 AR24 1

1
VAXG7 have 20 mil trace width
AR23 VAXG8 1 1 2 2 +1.5VS
AR21 R111 @
VAXG9 0_0402_5%
AR20 VAXG10 JUMP_43X118

VREF
AR18 VAXG11 2 1 R122
AR17 VAXG12
AP24 VAXG13 SM_VREF AL1 +V_SM_VREF_CNT 2 3 +V_SM_VREF 1 2 +1.5V_CPU
AP23 VAXG14

1
AP21 1 Q2
VAXG15 R486 C148 @ R252 1K_0402_5%
AP20 VAXG16 8/20 Add PJ32 for Cost down +1.5V to +1.5V_CPU
AP18 @ AP2302GN-HF_SOT23-3 1K_0402_5%
VAXG17 1

100K_0402_5%

0.1U_0402_16V4Z
AP17 VAXG18 +1.5V_CPU Decoupling:
2
AN24

2
VAXG19
AN23 VAXG20
RUN_ON_CPU1.5VS3 1X 330U (6m ohm), 6X 10U
AN21 VAXG21
AN20 +1.5V_CPU
VAXG22

DDR3 -1.5V RAILS

AN18 VAXG23
AN17 VAXG24 5A

GRAPHICS
AM24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VAXG25 VDDQ1
AM23 VAXG26 VDDQ2 AF4 1
AM21 VAXG27 VDDQ3 AF1 1 1 1 1 1 1
AM20 AC7 C114 C115 C116 C149 C154 C155 + C875
VAXG28 VDDQ4 330U_2.5V_M_R17
AM18 VAXG29 VDDQ5 AC4
AM17 AC1 ESR 17mohm
VAXG30 VDDQ6 2 2 2 2 2 2 2
AL24 VAXG31 VDDQ7 Y7
AL23 VAXG32 VDDQ8 Y4
AL21 Y1 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VAXG33 VDDQ9
AL20 VAXG34 VDDQ10 U7
AL18 VAXG35 VDDQ11 U4
2 AL17 U1 2
VAXG36 VDDQ12
AK24 VAXG37 VDDQ13 P7
AK23 VAXG38 VDDQ14 P4
AK21 VAXG39 VDDQ15 P1
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43 +VCCSA Decoupling:
AJ23 VAXG44
AJ21 VAXG45 1X 330U (6m ohm), 3X 10U
AJ20 VAXG46
AJ18 VAXG47
AJ17 Bottom Socket Cavity +VCCSA
VAXG48
AH24 6A VCCSA_VID0 VCCSA_VID1 +VCCSA
SA RAIL
VAXG49
AH23 VAXG50
AH21 M27 10U_0805_10V6K 10U_0805_10V6K 1 2VCCSA_SENSE
VAXG51 VCCSA1 R253 0_0402_5%
AH20 VAXG52 VCCSA2 M26 0 0 0.90 V For Sandy Bridge
AH18 VAXG53 VCCSA3 L26 1
AH17 VAXG54 VCCSA4 J26 1 1 1 1
C100 C447 C476 C477 + C877
VCCSA5 J25 0 1 0.80 V
J24 330U_2.5V_M_R17
VCCSA6 @ @
VCCSA7 H26
2 2 2 2 2
VCCPLL Decoupling: VCCSA8 H25 1 0 0.75 V
1.8V RAIL

+1.8VS
1X 330U (6m ohm), 1X 10U, 2x1U 10U_0805_10V6K 10U_0805_10V6K
1 1 0.65 V
1.2A Bottom Socket Edge
R76
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 H23 VCCSA_SENSE
VCCPLL1 VCCSA_SENSE VCCSA_SENSE 46
MISC

3 0_0805_5% 3
A6 VCCPLL2
1 A2 VCCPLL3 1 R95 2
C185 1 1 1 VCCSA_VID0 0_0402_5% @
@+ C186 C206 C230 C22 VCCSA_VID0
FC_C22
VCCSA_VID1 C24 VCCSAP_VID1 46
1U_0402_6.3V6K
2

2
2 2 2 2

330U_B2_2.5VM_R15M 1U_0402_6.3V6K Sandy Bridge_rPGA_Rev0p61 @

R114 R119
@
+1.5V_CPU +1.5V Only for PWWHA DIS PS3@
10K_0402_5% 10K_0402_5% +1.5V_CPU +1.5V
C213 1 2 0.1U_0402_16V4Z PJ30 @
1

2 2 1 1
C212 1 2 0.1U_0402_16V4Z
JUMP_43X118
08/18 Reserve R119 to follow CRB 1.0 C211 1 2 0.1U_0402_16V4Z
Q33 PS3@
C210 1 2 0.1U_0402_16V4Z 1 8
S D
2 S D 7

2
1 3 S D 6
R449 C179 4 5
470_0805_5% 10U_0805_10V4K G D
PS3@ PS3@ FDS6676AS_SO8 R455 PS3@
2 RUN_ON_CPU1.5VS3 1 2 +VSB

3 1
220K_0402_5%

6
1
Q46B C472 R420
SUSP 5 0.1U_0402_25V6 820K_0402_5% Q46A
PS3@ PS3@ PS3@ 2 SUSP
4 2 SUSP 5,32,41,47
4
2N7002KDW H_SOT363-6

2
2N7002KDW H_SOT363-6

1
PS3@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_POWER-2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 9 of 53
A B C D E
 A B C D E

JCPUE
JCPUH JCPUI CFG Straps for Processor
(CFG[17:0] internal pull high to VCCIO)
AT35 VSS1 VSS81 AJ22 RSVD28 L7
AT32 AJ19 5 CFG0 AG7 CFG2
VSS2 VSS82 CFG0 RSVD29
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22 AK28 CFG[0] RSVD30 AE7

1
AT27 AJ13 T34 F19 T5 PAD CFG1 AK29 AK2
VSS4 VSS84 VSS162 VSS235 T6 PAD CFG2 CFG[1] RSVD31 R254
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30 AL26 CFG[2] RSVD32 W8
AT22 AJ7 T32 E27 T7 PAD CFG3 AL27 1K_0402_1%
VSS6 VSS86 VSS164 VSS237 T11 PAD CFG4 CFG[3]
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24 AK26 CFG[4]
AT16 AJ3 T30 E21 T12 PAD CFG5 AL29 AT26

2
VSS8 VSS88 VSS166 VSS239 T15 PAD CFG6 CFG[5] RSVD33
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 AL30 CFG[6] RSVD34 AM33
1 AT10 AJ1 T28 E15 T18 PAD CFG7 AM31 AJ27 1
VSS10 VSS90 VSS168 VSS241 T16 PAD CFG8 CFG[7] RSVD35
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AM32 CFG[8]
AT4 AH34 T26 E10 T19 PAD CFG9 AM30 PEG Static Lane Reversal
VSS12 VSS92 VSS170 VSS243 T21 PAD CFG10 CFG[9]
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM28 CFG[10] - CFG2 is for the 16x
AR25 AH30 P8 E8 T20 PAD CFG11 AM26
VSS14 VSS94 VSS172 VSS245 T44 PAD CFG12 CFG[11]
AR22 AH29 P6 E7 AN28
AR19
AR16
VSS15
VSS16
VSS17
VSS95
VSS96
VSS97
AH28
AH26
P5
P3
VSS173
VSS174
VSS175
VSS246
VSS247
VSS248
E6
E5
T45
T46
PAD
PAD
CFG13
CFG14
AN31
AN26
CFG[12]
CFG[13]
CFG[14]
RSVD37
RSVD38
T8
J16
*
1: Normal Operation;
AR13 AH25 P2 E4 T47 PAD CFG15 AM27 H16 CFG2 Lane # definition matches
VSS18 VSS98 VSS176 VSS249 T26 PAD CFG16 CFG[15] RSVD39
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3 AK31 CFG[16] RSVD40 G16
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2 T27 PAD CFG17 AN29 CFG[17]
socket pin map definition
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35 0:Lane Reversed
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29 RSVD41 AR35
AP28 AG8 N29 D26 T22 PAD AJ31 AT34
VSS25 VSS105 VSS183 VSS256 T24 PAD RSVD1 RSVD42 CFG4
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20 AH31 RSVD2 RSVD43 AT33
AP22 AF6 N27 D17 T25 PAD AJ33 AP35
VSS27 VSS107 VSS185 VSS258 RSVD3 RSVD44

1
AP19 AF5 N26 C34 T23 PAD AH33 AR34
VSS28 VSS108 VSS186 VSS259 RSVD4 RSVD45 R255
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 AF2 L33 C28 1K_0402_1%
VSS30 VSS110 VSS188 VSS261 @
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27 AJ26 RSVD5

RESERVED
AP7 AE34 L27 C25

2
VSS32 VSS112 VSS190 VSS263
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10 SA_DIMM_VREFDQ RSVD46 B34
AN30 AE31 L6 C1 CPU_RSVD6 B4 A33
VSS35 VSS115 VSS193 VSS266 CPU_RSVD7 RSVD6 RSVD47
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22 D1 RSVD7 RSVD48 A34
AN25 AE29 L4 B19 SB_DIMM_VREFDQ B35 Embedded Display Port
AN22
VSS37
VSS38 VSS VSS117
VSS118 AE28 L3
VSS195
VSS196 VSS VSS268
VSS269 B17
RSVD49
RSVD50 C35 Presence Strap

1
2 AN19 AE27 L2 B15 2
VSS39 VSS119 VSS197 VSS270
AN16 AE26 L1 B13 F25 1 : Disabled; No
AN13
AN10
VSS40
VSS41
VSS42
VSS120
VSS121
VSS122
AE9
AD7
K35
K32
VSS198
VSS199
VSS200
VSS271
VSS272
VSS273
B11
B9
R115
1K_0402_1%
R116 F24
1K_0402_1% F23
RSVD8
RSVD9
RSVD10
* Physical Display
AN7 AC9 K29 B8 D24 AJ32 Port attached to

2
VSS43 VSS123 VSS201 VSS274 RSVD11 RSVD51
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7 G25 RSVD12 RSVD52 AK32 mbedded Display
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5 G24 RSVD13 CFG4 Port
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3 E23 RSVD14
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2 D23 RSVD15
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35 C30 RSVD16 RSVD53 AH27
AM16 AB35 H27 A32 A31 T28 PAD 0 : Enabled; An
VSS49 VSS129 VSS207 VSS280 RSVD17
AM13 AB34 H24 A29 B30
AM10
VSS50 VSS130
AB33 H21
VSS208 VSS281
A26 B29
RSVD18 external Display
VSS51 VSS131 VSS209 VSS282 RSVD19
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23 D30 RSVD20 RSVD54 AN35 CLK_RES_ITP 22 Port device is
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20 B31 RSVD21 RSVD55 AM35 CLK_RES_ITP# 22 connected to the
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3 A30 RSVD22
AM2 AB29 H10 C29 Embedded Display
VSS55 VSS135 VSS213 RSVD23
AM1 VSS56 VSS136 AB28 H9 VSS214 Port
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216 J20 RSVD24
AL28 VSS59 VSS139 Y9 H6 VSS217 B18 RSVD25 RSVD56 AT2
AL25 VSS60 VSS140 Y8 H5 VSS218 A19 RSVD26 RSVD57 AT1
AL22 Y6 H4 VCCIO_SEL AR1 CFG6
VSS61 VSS141 VSS219 RSVD58
AL19 VSS62 VSS142 Y5 H3 VSS220
AL16 Y3 H2 J15 CFG5
VSS63 VSS143 VSS221 RSVD27
AL13 VSS64 VSS144 Y2 H1 VSS222

1
AL10 VSS65 VSS145 W35 G35 VSS223
AL7 W34 G32 B1 R257 R256
VSS66 VSS146 VSS224 KEY 1K_0402_1% 1K_0402_1%
AL4 VSS67 VSS147 W33 G29 VSS225
3 @ 3
AL2 VSS68 VSS148 W32 G26 VSS226
AK33 W31 G23

2
VSS69 VSS149 VSS227
AK30 VSS70 VSS150 W30 G20 VSS228
AK27 VSS71 VSS151 W29 G17 VSS229
AK25 VSS72 VSS152 W28 G11 VSS230
AK22 W27 F34 Sandy Bridge_rPGA_Rev0p61 @
VSS73 VSS153 VSS231
AK19 VSS74 VSS154 W26 F31 VSS232
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 VSS76 VSS156 U8 PCIE Port Bifurcation Straps
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5 11: (Default) x16 - Device 1
AK4 U3 CFG7
AJ25
VSS79 VSS159
U2
functions 1 and 2 disabled
VSS80 VSS160

1
R258 10: x8, x8 - Device 1
1K_0402_1%
@ * function 1 enabled ;
Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @ function 2 disabled

2
CFG[6:5] 01: Reserved -
(Device 1 function 1
disabled ; function
PEG DEFER TRAINING 2 enabled)

1: (Default) PEG Train immediately following xxRESETB 00: x8,x4,x4 - Device 1

CFG7 de assertion functions 1 and 2
4 4
enabled
0: PEG Wait for BIOS for training

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_GND/RSVD/CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 10 of 53
A B C D E
 A B C D E

+1.5V +1.5V
JDDRL DDR3 SO-DIMM A
1 2
+VREF_DQA
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] 7
5 DQ0 DQ5 6 DDR_A_DQS#[0..7] 7
1 1 DDR_A_D1 7 8
C156 C157 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] 7
11 12 DDR_A_DQS0
DM0 DQS0
0.1U_0402_16V4Z

2.2U_0603_6.3V6K
13 VSS VSS 14 DDR_A_MA[0..15] 7
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
1 25 VSS VSS 26 1
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
Close to JDDRL.1 29 DQS1 RESET# 30 SM_DRAMRST# 7,12 +1.5V
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36

1
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20 R79
DDR_A_D17 DQ16 DQ20 DDR_A_D21 1K_0402_1%
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46

2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48 +VREF_DQA
49 50 DDR_A_D22
VSS DQ22

1
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23 R81
53 DQ19 VSS 54
55 56 DDR_A_D28 1K_0402_1%
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60

2
DQ25 VSS DDR_A_DQS#3
61 VSS DQS3# 62
63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDRA_CKE0 73 74 DDRA_CKE1
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
7 DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
2 DDR_A_MA9 A12/BC# A11 DDR_A_MA7 2
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
DDRA_CLK0 101 102 DDRA_CLK1
7 DDRA_CLK0 CK0 CK1 DDRA_CLK1 7
DDRA_CLK0# 103 104 DDRA_CLK1#
7 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 7
105 VDD VDD 106
DDR_A_MA10 DDR_A_BS1 +1.5V
107 A10/AP BA1 108 DDR_A_BS1 7
DDR_A_BS0 109 110 DDR_A_RAS#
7 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 7
111 VDD VDD 112

1
DDR_A_W E# 113 114 DDRA_SCS0#
7 DDR_A_W E# WE# S0# DDRA_SCS0# 7
DDR_A_CAS# 115 116 DDRA_ODT0 R80
7 DDR_A_CAS# CAS# ODT0 DDRA_ODT0 7
117 118 1K_0402_1%
DDR_A_MA13 VDD VDD DDRA_ODT1
119 A13 ODT1 120 DDRA_ODT1 7
DDRA_SCS1# 121 122

2
7 DDRA_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAA
TEST VREF_CA
127 VSS VSS 128

1
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37 R82
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_A_DQS#4 VSS VSS
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1

2
DQS4 VSS DDR_A_D38 C161 C162
139 VSS DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DQ34 DQ39
2.2U_0603_6.3V6K

0.1U_0402_16V4Z

DDR_A_D35 143 144

DQ35 VSS DDR_A_D44 2 2
145 VSS DQ44 146
3 DDR_A_D40 147 148 DDR_A_D45 3
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
DDR_A_DQS#5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
151 VSS DQS5# 152
153 154 DDR_A_DQS5 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
DM5 DQS5
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 close to JDDRL.126 +1.5V
Change C218 to OSCON at DVT
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52 @ +1.5V +0.75VS
DDR_A_D49 DQ48 DQ52 DDR_A_D53 C218 1 2 390U_2.5V_M_R10
+
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_A_DQS#6 169 170 C164 1 2 0.1U_0402_16V4Z C165 1 2 10U_0603_6.3V6M
DDR_A_DQS6 DQS6# DM6 C166 1
171 DQS6 VSS 172 2 10U_0603_6.3V6M
173 174 DDR_A_D54 C167 1 2 0.1U_0402_16V4Z
DDR_A_D50 VSS DQ54 DDR_A_D55 C168 1
175 DQ50 DQ55 176 2 10U_0603_6.3V6M C169 2 1 1U_0402_6.3V6K
DDR_A_D51 177 178 C170 1 2 0.1U_0402_16V4Z
DQ51 VSS DDR_A_D60 C171 1
179 VSS DQ60 180 2 10U_0603_6.3V6M C172 2 1 1U_0402_6.3V6K
DDR_A_D56 181 182 DDR_A_D61 C173 1 2 0.1U_0402_16V4Z
DDR_A_D57 DQ56 DQ61 C174 1
183 DQ57 VSS 184 2 10U_0603_6.3V6M C175 2 1 1U_0402_6.3V6K
185 186 DDR_A_DQS#7
VSS DQS7# DDR_A_DQS7 C176 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M C177 2 1 1U_0402_6.3V6K
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62 C178 1 2 10U_0603_6.3V6M
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
R90 1 2 195 196
10K_0402_5% VSS VSS
197 SA0 EVENT# 198
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA 12,22,32
201 202 PM_SMBCLK
0.1U_0402_16V4Z

SA1 SCL PM_SMBCLK 12,22,32

203 204
2.2U_0603_6.3V6K

1 1 +0.75VS VTT VTT +0.75VS

1

C182
C181 205 206
R91 GND1 BOSS1
4 207 GND2 BOSS2 208 4
2 2 10K_0402_5%
2

FOX_AS0A626-U2SN-7F_204P
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 11 of 53
A B C D E
 A B C D E

+1.5V +1.5V
JDDRH
1 2
+VREF_DQB
DDR_B_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_B_D4
DDR_B_D5
Reverse Type
5 6
DDR_B_D1 7
DQ0
DQ1
DQ5
VSS 8
DDR_B_DQS#0
DDR3 SO-DIMM B
9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS VSS 14
C183 C184 DDR_B_D2 15 16 DDR_B_D6 DDR_B_DQS#[0..7] 7
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
2.2U_0603_6.3V6K

0.1U_0402_16V4Z
19 VSS VSS 20 DDR_B_DQS[0..7] 7
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_D[0..63] 7
DQ9 DQ13
1 25 VSS VSS 26 1
DDR_B_DQS#1 27 28 DDR_B_MA[0..15] 7
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# 7,11
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
Close to JDDRH.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 DDR_B_D20 +1.5V
39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 VSS VSS 44

1
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2 R83
47 DQS2 VSS 48
49 50 DDR_B_D22 1K_0402_1%
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54

2
DQ19 VSS DDR_B_D28
55 VSS DQ28 56 +VREF_DQB
DDR_B_D24 57 58 DDR_B_D29
DQ24 DQ29

1
DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3 R84
61 VSS DQS3# 62
63 64 DDR_B_DQS3 1K_0402_1%
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30

2
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDRB_CKE0 73 74 DDRB_CKE1
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
7 DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
2 DDR_B_MA9 A12/BC# A11 DDR_B_MA7 2
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
DDRB_CLK0 101 102 DDRB_CLK1
7 DDRB_CLK0 CK0 CK1 DDRB_CLK1 7
DDRB_CLK0# 103 104 DDRB_CLK1#
7 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 7
105 VDD VDD 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 7
DDR_B_BS0 109 110 DDR_B_RAS#
7 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 7
111 VDD VDD 112

1
DDR_B_W E# 113 114 DDRB_SCS0#
7 DDR_B_W E# WE# S0# DDRB_SCS0# 7
DDR_B_CAS# 115 116 DDRB_ODT0 R86
7 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 7
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD DDRB_ODT1
119 A13 ODT1 120 DDRB_ODT1 7
DDRB_SCS1# 121 122

2
7 DDRB_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAB
TEST VREF_CA
127 VSS VSS 128

1
DDR_B_D37 129 130 DDR_B_D32
DDR_B_D36 DQ32 DQ36 DDR_B_D33 R94
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_B_DQS#4 VSS VSS
135 DQS4# DM4 136 1 1
DDR_B_DQS4 137 138 C187 C188

2
DQS4 VSS DDR_B_D38
139 VSS DQ38 140
2.2U_0603_6.3V6K

0.1U_0402_16V4Z

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2
143 DQ35 VSS 144
145 146 DDR_B_D44
3 DDR_B_D40 VSS DQ44 DDR_B_D45 3
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
DDR_B_DQS5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
153 DM5 DQS5 154
155 156 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
DDR_B_D42 VSS VSS DDR_B_D46
DDR_B_D43
157 DQ42 DQ46 158
DDR_B_D47
Close to JDDRH.126
159 DQ43 DQ47 160
161 162 +1.5V
DDR_B_D48 VSS VSS DDR_B_D52 +1.5V +0.75VS
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 VSS VSS 168
DDR_B_DQS#6 169 170 C190 1 2 0.1U_0402_16V4Z C191 1 2 10U_0603_6.3V6M
DDR_B_DQS6 DQS6# DM6 C192 1
171 DQS6 VSS 172 2 10U_0603_6.3V6M
173 174 DDR_B_D50 C193 1 2 0.1U_0402_16V4Z
DDR_B_D54 VSS DQ54 DDR_B_D51 C194 1
175 DQ50 DQ55 176 2 10U_0603_6.3V6M C195 2 1 1U_0402_6.3V6K
DDR_B_D55 177 178 C196 1 2 0.1U_0402_16V4Z
DQ51 VSS DDR_B_D60 C197 1
179 VSS DQ60 180 2 10U_0603_6.3V6M C198 2 1 1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61 C199 1 2 0.1U_0402_16V4Z
DDR_B_D57 DQ56 DQ61 C200 1
183 DQ57 VSS 184 2 10U_0603_6.3V6M C201 2 1 1U_0402_6.3V6K
185 186 DDR_B_DQS#7
VSS DQS7# DDR_B_DQS7 C202 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M C203 2 1 1U_0402_6.3V6K
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62 C204 1 2 10U_0603_6.3V6M
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196
10K_0402_5% VSS VSS
197 SA0 EVENT# 198
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA 11,22,32
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK 11,22,32
2.2U_0603_6.3V6K
1 1 1 R99 2 +0.75VS 203 204 +0.75VS
@ 10K_0402_5% VTT VTT
C207 205 206
C208 GND1 BOSS1
4 207 GND2 BOSS2 208 4
2 2 @
0.1U_0402_16V4Z
FOX_AS0A626-UASN-7F_204P
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 12 of 53
A B C D E
 A B C D E

+3VS
PCIE_CTX_C_GRX_P[8..15]
6 PCIE_CTX_C_GRX_P[8..15]
PCIE_CTX_C_GRX_N[8..15]
6 PCIE_CTX_C_GRX_N[8..15]
UV1A VGA_CRT_CLK 4.7K_0402_5% 2 1 RV23
PCIE_GTX_C_CRX_P[8..15] Part 1 of 5
6 PCIE_GTX_C_CRX_P[8..15]
AE12 N1 VGA_CRT_DATA 4.7K_0402_5% 2 1 RV24
PCIE_GTX_C_CRX_N[8..15] PEX_RX0 GPIO0
6 PCIE_GTX_C_CRX_N[8..15] AF12 PEX_RX0_N GPIO1 G1
AG12 C1 VGA_PW M I2CH_SCL 10K_0402_5% 2 1 @ RV100
PEX_RX1 GPIO2 VGA_PW M 19
AG13 M2 VGA_ENVDD FERMI Changed
PEX_RX1_N GPIO3 VGA_ENVDD 19
AF13 M3 VGA_ENBKL I2CH_SDA 10K_0402_5% 2 1 @ RV101
PEX_RX2 GPIO4 VGA_ENBKL 38
AE13 K3 GPU_VID0
PEX_RX2_N GPIO5 GPU_VID0 50
AE15 K2 GPU_VID1 I2CB_SCL 2.2K_0402_5% 1 2 RV27
PEX_RX3 GPIO6 GPU_VID1 50
1 AF15 PEX_RX3_N GPIO7 J2 1
AG15 C2 GPU_GPIO8 I2CB_SDA 2.2K_0402_5% 1 2 RV28
PEX_RX4 GPIO8

GPIO
AG16 M1 GPU_GPIO9
PEX_RX4_N GPIO9 GPU_GPIO8 10K_0402_5%
AF16 PEX_RX5 GPIO10 D2 2 1 RV102
AE16 PEX_RX5_N GPIO11 D1
AE18 J3 GPU_GPIO12 GPU_GPIO9 10K_0402_5% 1 2 RV26
PEX_RX6 GPIO12 @ TV8
AF18 PEX_RX6_N GPIO13 J1
AG18 K1 GPU_GPIO12 10K_0402_5% 1 2 RV29
PEX_RX7 GPIO14
AG19 PEX_RX7_N GPIO15 F3 HDMI_HPD 26,30
PCIE_CTX_C_GRX_P8 AF19 G3 LCD_EDID_CLK 2.2K_0402_5% 1 2 RV14
PCIE_CTX_C_GRX_N8 PEX_RX8 GPIO16
AE19 PEX_RX8_N GPIO17 G2
PCIE_CTX_C_GRX_P9 AE21 F1 LCD_EDID_DATA 2.2K_0402_5% 1 2 RV17
PCIE_CTX_C_GRX_N9 PEX_RX9 GPIO18
AF21 PEX_RX9_N GPIO19 F2
PCIE_CTX_C_GRX_P10 AG21
PCIE_CTX_C_GRX_N10 PEX_RX10 VGA_PW M 10K_0402_5%1
AG22 PEX_RX10_N DACA_HSYNC AD2 VGA_CRT_HSYNC 20 2 RV10
PCIE_CTX_C_GRX_P11 AF22 AD1
PEX_RX11 DACA_VSYNC VGA_CRT_VSYNC 20
PCIE_CTX_C_GRX_N11 AE22 VGA_ENBKL 10K_0402_5%1 2 RV11

DACA
PCIE_CTX_C_GRX_P12 PEX_RX11_N
AE24 PEX_RX12 DACA_RED AE2 VGA_CRT_R 20
PCIE_CTX_C_GRX_N12 AF24 AD3 VGA_CRT_B 20
PCIE_CTX_C_GRX_P13 PEX_RX12_N DACA_BLUE HDMI_HPD NHDMI@ 1
AG24 PEX_RX13 DACA_GREEN AE3 VGA_CRT_G 20 2
PCIE_CTX_C_GRX_N13 AF25 R25 100K_0402_5%
PCIE_CTX_C_GRX_P14 PEX_RX13_N DACA_VREF CV13 1
AG25 PEX_RX14 DACA_VREF AF1 2 0.1U_0402_16V4Z
PCIE_CTX_C_GRX_N14 AG26 AE1 DACA_RSET 1 2
PEX_RX14_N DACA_RSET

PCI EXPRESS
PCIE_CTX_C_GRX_P15 AF27 RV6 124_0402_1%
PCIE_CTX_C_GRX_N15 AE27
PEX_RX15
U6
Close to GPU
PEX_RX15_N DACB_HSYNC VGA_CRT_R RV3
DACB_VSYNC U4 1 2 150_0402_1%
AD10

DACB
PEX_TX0 VGA_CRT_G RV4
AD11 PEX_TX0_N DACB_RED T5 1 2 150_0402_1%
AD12 PEX_TX1 DACB_BLUE R4
2 AC12 T4 VGA_CRT_B RV5 1 2 150_0402_1% 2
PEX_TX1_N DACB_GREEN
AB11 PEX_TX2
AB12 R6 +3VS
PEX_TX2_N DACB_VREF
AD13 PEX_TX3 DACB_RSET V6
AD14 PEX_TX3_N
AD15 PEX_TX4
AC15 PEX_TX4_N

1
AB14 AF3 GPU_JTAG_TCK @ TV1
PEX_TX5 JTAG_TCK GPU_JTAG_TDI @ TV2 @ RV7
AB15 PEX_TX5_N JTAG_TDI AG4
AC16 AE4 GPU_JTAG_TDO @ TV3 10K_0402_5%
PEX_TX6 JTAG_TDO

TEST
AD16 AF4 GPU_JTAG_TMS @ TV4
PEX_TX6_N JTAG_TMS GPU_JTAG_TRST#
AD17 AG3 1 2

2
PEX_TX7 JTAG_TRST_N RV9 1K_0402_1% GPU_TESTMODE
AD18 PEX_TX7_N
PCIE_GTX_C_CRX_P8 CV18 2 1 .1U_0402_16V7K PCIE_GTX_CRX_P8 AC18 AD25 GPU_TESTMODE
PCIE_GTX_C_CRX_N8 CV19 .1U_0402_16V7K PCIE_GTX_CRX_N8 PEX_TX8 TESTMODE
2 1 AB18 PEX_TX8_N

1
PCIE_GTX_C_CRX_P9 CV20 2 1 .1U_0402_16V7K PCIE_GTX_CRX_P9 AB19
PCIE_GTX_C_CRX_N9 CV21 .1U_0402_16V7K PCIE_GTX_CRX_N9 PEX_TX9 RV8
2 1 AB20 PEX_TX9_N
PCIE_GTX_C_CRX_P10 CV22 2 1 .1U_0402_16V7K PCIE_GTX_CRX_P10 AD19 R1 VGA_CRT_CLK 20 10K_0402_5%
PCIE_GTX_C_CRX_N10 CV23 .1U_0402_16V7K PCIE_GTX_CRX_N10 PEX_TX10 I2CA_SCL
2 1 AD20 PEX_TX10_N I2CA_SDA T3 VGA_CRT_DATA 20
PCIE_GTX_C_CRX_P11 CV24 2 1 .1U_0402_16V7K PCIE_GTX_CRX_P11 AD21

2
PCIE_GTX_C_CRX_N11 CV25 .1U_0402_16V7K PCIE_GTX_CRX_N11 PEX_TX11 I2CB_SCL
2 1 AC21 PEX_TX11_N I2CB_SCL R2
PCIE_GTX_C_CRX_P12 CV26 2 1 .1U_0402_16V7K PCIE_GTX_CRX_P12 AB21 R3 I2CB_SDA
PCIE_GTX_C_CRX_N12 CV27 .1U_0402_16V7K PCIE_GTX_CRX_N12 PEX_TX12 I2CB_SDA
2 1 AB22 PEX_TX12_N
PCIE_GTX_C_CRX_P13 CV28 2 1 .1U_0402_16V7K PCIE_GTX_CRX_P13 AC22 A2 LCD_EDID_CLK 19
PEX_TX13 I2CC_SCL
I2C

PCIE_GTX_C_CRX_N13 CV29 2 1 .1U_0402_16V7K PCIE_GTX_CRX_N13 AD22 B1 LCD_EDID_DATA 19

PCIE_GTX_C_CRX_P14 CV30 .1U_0402_16V7K PCIE_GTX_CRX_P14 PEX_TX13_N I2CC_SDA
2 1 AD23 PEX_TX14
PCIE_GTX_C_CRX_N14 CV31 2 1 .1U_0402_16V7K PCIE_GTX_CRX_N14 AD24 A3 I2CH_SCL
PCIE_GTX_C_CRX_P15 CV32 .1U_0402_16V7K PCIE_GTX_CRX_P15 PEX_TX14_N GPIO20 I2CH_SDA
2 1 AE25 PEX_TX15 GPIO21 A4 FERMI Changed
PCIE_GTX_C_CRX_N15 CV33 2 1 .1U_0402_16V7K PCIE_GTX_CRX_N15 AE26
3 PEX_TX15_N GPU_SMBCLK 3
I2CS_SCL T1
AB10 T2 GPU_SMBDAT
22 CLK_PCIE_VGA PEX_REFCLK I2CS_SDA
22 CLK_PCIE_VGA# AC10 PEX_REFCLK_N
1 2 PEX_TSTCLK_OUT AF10
@ RV13 200_0402_1% PEX_TSTCLK_OUT# PEX_TSTCLK_OUT XTALSSIN
Differential signal AE10 PEX_TSTCLK_OUT_N XTAL_SSIN D11 1 2
RV12 10K_0402_5%
2 1 AG10 E9 XTALOUTBUFF 1 2 +3VS
RV15 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF RV16 10K_0402_5%
1 2 AD9 E10 NV_CLK_27M_OUT +3VS
5,25,32,33,35,38,39 PLT_RST#
CLK

RV18 0_0402_5% PEX_RST_N XTAL_OUT

2
+3VS 1 2 CLK_REQ# AE9 D10 CLK_27M_IN
RV21 10K_0402_5% PEX_CLKREQ_N XTAL_IN YV1 RV22 RV25
2.2K_0402_5% 2.2K_0402_5%
N12M-GE-S-B1 BGA 533P CLK_27M_IN 1 2 NV_CLK_27M_OUT

5
N12MR1@ QV1B

1
27MHZ_16PF_X5H027000FG1H
18P_0402_50V8J

18P_0402_50V8J
R39 0_0402_5% 1 1 GPU_SMBCLK 4 3 EC_SMB_CK2 22,38
CV34

CV35
CLK_27M_IN 1 @ 2 CLK_27M
CLK_27M 22

2
2N7002KDW H_SOT363-6
1

QV1A
R405 2 2 GPU_SMBDAT 1 6 EC_SMB_DA2 22,38
10_0402_5%
@ 2N7002KDW H_SOT363-6
2

C88
1 Near GPU
10P_0402_50V8J
4
@ 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12M PCIe,DAC,GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 13 of 53
A B C D E
 A B C D E

UV1C
Part 3 of 5 UV1E
19 LCD_TXCLK+ AC4 C15 B2 Part 5 of 5 U2
IFPA_TXC NC GND GND
19 LCD_TXCLK- AD4 IFPA_TXC_N NC D15 B5 GND GND U5

NC
19 LCD_TXOUT0+ V5 IFPA_TXD0 PGOOD J5 1 2 B8 GND GND U11
19 LCD_TXOUT0- V4 @ RV1 10K_0402_1% B11 U12
IFPA_TXD0_N GB1B-64 : PGOOD GND GND
19 LCD_TXOUT1+ AA5 IFPA_TXD1 B14 GND GND U13
19 LCD_TXOUT1- AA4 IFPA_TXD1_N B17 GND GND U14
19 LCD_TXOUT2+ W4 IFPA_TXD2 B20 GND GND U15
19 LCD_TXOUT2- Y4 IFPA_TXD2_N MULTI_STRAP_REF2_GND T6 1 2 B23 GND GND U16
+3VS AB4 W6 RV2 40.2_0402_1% B26 U17

DBG
IFPA_TXD3 DBG_DATA1 GB1B-64 : MULTI_STRAP_REF2_GND GND GND
AB5 IFPA_TXD3_N DBG_DATA2 Y6 E2 GND GND U23
DBG_DATA3 AA6 E5 GND GND U26
1 15K_0402_1%
DBG_DATA4 N3 E8 GND GND V9 1

10K_0402_1%

10K_0402_1%
AB3 E11 V19
45.3K_0402_1%

34.8K_0402_1%

IFPB_TXC GND GND

2

2
@ AB2 E17 W11
IFPB_TXC_N GND GND
RV49

RV50

RV51

RV97

RV98
W1 IFPB_TXD4 E20 GND GND W14
V1 C7 STRAP0 E23 W17
IFPB_TXD4_N STRAP0 GND GND
W3 E26 Y2

STRAP
IFPB_TXD5 GND GND

LVDS / TMDS
@ @ W2 B9 STRAP1 H2 Y5
1

1
IFPB_TXD5_N STRAP1 GND GND

GND
AA2 IFPB_TXD6 H5 GND GND Y23
AA3 A9 STRAP2 J11 Y26
STRAP0 IFPB_TXD6_N STRAP2 GND GND
AB1 IFPB_TXD7 J14 GND GND AC2
STRAP1 AA1 J17 AC5
STRAP2 IFPB_TXD7_N GND GND
K9 GND GND AC6
STRAP3 K19 AC8
STRAP4 GND GND
G4 IFPC_AUX_I2CW_SCL BUFRST_N N5 L2 GND GND AC11
G5 IFPC_AUX_I2CW_SDA_N L5 GND GND AC14
P4 IFPC_L0 L11 GND GND AC17
N4 L12 AC20
34.8K_0402_1%

4.99K_0402_1%
4.99K_0402_1%

4.99K_0402_1%

IFPC_L0_N GND GND

GENERAL
20K_0402_1%

M5 IFPC_L1 THERMDN D8 L13 GND GND AC23

2

M4 IFPC_L1_N L14 GND GND AC26

RV55

RV57
RV56

RV41

RV99

L4 IFPC_L2 THERMDP D9 L15 GND GND AF2

K4 IFPC_L2_N L16 GND GND AF5
H4 IFPC_L3 L17 GND GND AF8
@ @ J4 M12 AF11
1

IFPC_L3_N STRAP4 GND GND

STRAP4 N2 M13 GND GND AF14
Fermi changed M14 GND GND AF17
D3 F9 STRAP3 M15 AF20
IFPD_AUX_I2CX_SCL STRAP3 GND GND
D4 IFPD_AUX_I2CX_SDA_N M16 GND GND AF23
F5 IFPD_L0 P2 GND GND AF26
F4 IFPD_L0_N P5 GND GND T16
2 E4 B10 P9 T15 2
IFPD_L1 ROM_CS_N GND GND
D5 IFPD_L1_N P19 GND GND T14

SERIAL
C3 C9 ROM_SCLK_GPU P23 F6
IFPD_L2 ROM_SCLK GND GND
C4 IFPD_L2_N P26 GND
B3 A10 ROM_SI_GPU T12 A15 1 2
IFPD_L3 ROM_SI GND FB_CAL_PU_GND RV42 40.2_0402_1%
B4 IFPD_L3_N T13 GND
C10 ROM_SO_GPU B16 1 2
ROM_SO FB_CAL_TERM_GND RV43 60.4_0402_1%
VGA_HDMI_CLK F7 W16 F11 1 2
30 VGA_HDMI_CLK IFPE_AUX_I2CY_SCL GND_SENSE MULTI_STRAP_REF0_GND
VGA_HDMI_DATA G6 RV44 40.2K_0402_1%
30 VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N
30 VGA_HDMI_TX2+ VGA_HDMI_TX2+ D6 E14 F10 1 2
VGA_HDMI_TX2- IFPE_L0 GND_SENSE MULTI_STRAP_REF1_GND RV46 40.2K_0402_1%
30 VGA_HDMI_TX2- C6 IFPE_L0_N IFPAB_RSET AB6 1 2
30 VGA_HDMI_TX1+ VGA_HDMI_TX1+ A6 @ RV32 1K_0402_1%
VGA_HDMI_TX1- IFPE_L1 N12M-GE-S-B1 BGA 533P
30 VGA_HDMI_TX1- A7 IFPE_L1_N IFPC_RSET R5 1 2
30 VGA_HDMI_TX0+ VGA_HDMI_TX0+ B6 @ RV45 1K_0402_1% N12MR1@
VGA_HDMI_TX0- IFPE_L2
30 VGA_HDMI_TX0- B7 IFPE_L2_N IFPD_RSET M6 1 2
30 VGA_HDMI_CLK+ VGA_HDMI_CLK+ E6 @ RV47 1K_0402_1%
VGA_HDMI_CLK- IFPE_L3
30 VGA_HDMI_CLK- E7 IFPE_L3_N IFPE_RSET F8 1 2
HDMI@ RV48 1K_0402_1%

N12M-GE-S-B1 BGA 533P

N12MR1@ Resistor Values Pull-up to +3VS Pull-down to Gnd
+3VS
Physical Logical Logical Logical Logical 5K 1000 0000
HDMI@ Power Rail
1 2 VGA_HDMI_CLK Strapping pin Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0 10K 1001 0001
RV119 4.7K_0402_5% ROM_SO +3VS XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
HDMI@ 15K 1010 0010
1 2 VGA_HDMI_DATA ROM_SCLK +3VS PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
3 RV120 4.7K_0402_5% 3
20K 1011 0011
ROM_SI +3VS RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
25K 1100 0100
STRAP2 +3VS PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
30K 1101 0101
STRAP1 +3VS 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
+3VS
35K 1110 0110
STRAP0 +3VS USER[3] USER[2] USER[1] USER[0]
45K 1111 0111
15K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
2

Hynix (800MHZ) 64MX16 H5TQ1G63DFR-12C SA0000324C0 512MB 0010 RV59 PD 15K (SD034150280)
RV53

RV54
RV52

@ @ RV59 PD 34.8K (SD034348280)

Hynix (900MHZ) 128MX16 H5TQ2G63BFR-11C SA00003YO00 1GB 0110
1

ROM_SCLK_GPU
ROM_SI_GPU RV59 PD 20K (SD034200280)
ROM_SO_GPU Samsung (800MHZ) 64MX16 K4W1G1646G-BC12 SA00004HS00 512MB 0011
15K_0402_1%
15K_0402_1%

10K_0402_1%
2

2
RV60
RV58

RV59

Samsung (900MHZ) 128MX16 K4W2G1646C-HC11 SA000047Q00 1GB 0111 RV59 PD 45.3K (SD034453280)

@ @
1

4 4
X76

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12M LVDS,HDMI,DP,GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 14 of 53
A B C D E
 A B C D E

UV1D
NV DG for VDD Cap: +VGA_CORE +VGA_CORE Part 4 of 5 ůŽƐĞƚŽWŝŶ ϭϳϰϳƚŽďĞĐůŽƐĞƚŽƚŚĞ'Wh
J9 A13
0.01uF 10% X7R x6 VDD FBVDDQ Ϯ͘ϵϳ

22U_0603_6.3V6M

22U_0603_6.3V6M
J10 B13 +1.5V_MEM_GFX
0.047uF 10% X7R x3 VDD FBVDDQ

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M
1 J12 VDD FBVDDQ C13
0.1uF 10% X7R x1 1 1 J13 D13 1 1 1 1 1 1
VDD FBVDDQ

CV38

CV45

CV46

CV47

CV48

CV39
4.7uF 10% X5R x1 C876 + L9 D14 @ @
330U_2.5V_M_R17 CV164 CV163 VDD FBVDDQ
For GB1b-64 add: M9 VDD FBVDDQ E13
@ M11 F13
4.7u X5R x1 2 2 2
M17
VDD FBVDDQ
F14
2 2 2 2 2 2
N10M SPEC FBVDDQ TYP. 1.8V.
VDD FBVDDQ
N9 VDD FBVDDQ F15
N11 VDD FBVDDQ F16
N12 VDD FBVDDQ F17
1 N13 VDD FBVDDQ F19 1
N14 F22

0.047U_0402_25V6K

0.047U_0402_25V6K

0.047U_0402_25V6K
VDD FBVDDQ +1.5V_MEM_GFX
N15 VDD FBVDDQ H23

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
N16 VDD FBVDDQ H26 1 1 1
N17 VDD FBVDDQ J15
1 1 1 1 1 1 1 N19 J16 CV52 CV53 CV54
VDD FBVDDQ

CV49

CV40

CV50

CV41

CV51

CV42

CV43
P11 VDD FBVDDQ J18
2 2 2
P12 VDD FBVDDQ J19
P13 VDD FBVDDQ L19
2 2 2 2 2 2 2
P14 VDD FBVDDQ L23
P15 VDD FBVDDQ L26
P16 VDD FBVDDQ M19
P17 N22 +1.05VS_VCCP
VDD FBVDDQ
R9 VDD FBVDDQ U22
0.022U_0402_25V7K

0.022U_0402_25V7K

1U_0402_6.3V6K
R11 Y22

0.022U_0402_25V7K

0.022U_0402_25V7K

0.022U_0402_25V7K
VDD FBVDDQ

POWER

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

22U_0805_6.3V6M
R12 VDD
1 1 1 1 1 1 R13 VDD PEX_IOVDDQ AG6
CV58 CV59 CV60 R14 AF6 1 1 1 1 1 1 1
VDD PEX_IOVDDQ

CV61

CV62

CV63

CV64

CV65

CV66

CV67
CV162 CV161 CV44 R15 AE6
VDD PEX_IOVDDQ
R16 VDD PEX_IOVDDQ AD6
2 2 2 2 2 2
R17 VDD PEX_IOVDDQ AC13
2 2 2 2 2 2 2
T9 VDD PEX_IOVDDQ AC7
T11
under GPU T17
VDD Ϯ PEX_IOVDDQ AB17
AB16
VDD PEX_IOVDDQ
U9 VDD PEX_IOVDDQ AB13
U19 AB9 +1.05VS_VCCP
+3VS LV1 220R 100MHZ W9
VDD PEX_IOVDDQ
AB8 W>>K^dK>> W>EZ'Wh
PBY160808T-221Y-N_2P VDD PEX_IOVDDQ
W10 VDD PEX_IOVDDQ AB7

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

22U_0805_6.3V6M

10U_0603_6.3V6M
1 2 +3.3V_RUN_VDD33 W12
2 VDD 2
W13 VDD PEX_IOVDD AG7 1 1 1 1 1 1 1
4.7U_0603_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

CV70

CV71

CV72

CV73

CV77

CV78

CV79
W18 VDD PEX_IOVDD AF7
1 1 1 1 1 W19 VDD PEX_IOVDD AE7
AD8
Ϯ PEX_IOVDD 2 2 2 2 2 2 2
CV74

CV75

CV68

CV76

CV69
ϭϮϬŵ A12
PEX_IOVDD AD7
AC9
2 2 2 2 2 VDD33 PEX_IOVDD
B12 VDD33
C12 VDD33 PEX_PLLVDD AF9 +PEX_PLLVDD
D12 VDD33
E12 K6 +PLLVDD
+1.8VS 220R 100MHZ VDD33 VID_PLLVDD
LV11 PBY160808T-221Y-N_2P ϮϮϬŵ +3VS
F12 VDD33
L6 ϭϮϬŵ
+IFPAB_IOVDD SP_PLLVDD
2 1
ϭϮϬŵ AG9 K5 W>EZ'Wh LV2
PEX_SVDD_3V3 PLLVDD
4.7U_0603_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

20 mil SBK160808T-300Y-N_2P
4.7U_0603_6.3V6K

.1U_0402_16V7K

1 1 1 1 R19 +FB_AVDD 2 1
FB_PLLAVDD
CV175

CV166

CV174

.1U_0402_16V7K
1 1 V3 IFPA_IOVDD 100mA +1.05VS_VCCP
CV172

CV80

CV81

1U_0402_6.3V6K

10U_0603_6.3V6M
FB_PLLAVDD AC19 1 1
+IFPAB_IOVDD V2 1
2 2 2 2 IFPB_IOVDD

CV165
T19 100mA CV82 CV83
2 2 FB_DLLAVDD
J6 IFPCD_IOVDD 2 2
+IFPE_IOVDD +DACA_VDD 2
H6 IFPE_IOVDD DACA_VDD AG2

W5 1 2 add for GB1b-64

+IFPAB_PLLVDD DACB_VDD RV63 10K_0402_1%
AD5 IFPAB_PLLVDD
+1.05VS_VCCP +1.5V_MEM_VDDQ +1.05VS_VCCP
LV10
P6 IFPC_PLLVDD FB_CAL_PD_VDDQ B15 2
RV65
1
40.2_0402_1%
+1.5V_MEM_GFX ϭϮϬŵadd for GB1b-64
LV4
3 SBK160808T-121Y-N_2P ϮϮϬŵ N6 W15 VDD_SENSE 50
SBK160808T-121Y-N_2P 3
+IFPAB_PLLVDD IFPD_PLLVDD VDD_SENSE +PEX_PLLVDD
2 1 2 1
+IFPE_PLLVDD D7 E15
IFPE_PLLVDD VDD_SENSE
4.7U_0603_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
route as 50ohm
1 1 1 1 1 1 1
CV167

CV90

CV92

CV93

CV91
N12M-GE-S-B1 BGA 533P
CV171

CV168 N12MR1@
1

2 2 2 RV20 2 2 2 2
10K_0402_5%

add for GB1b-64

2

+1.05VS_VCCP
+1.05VS_VCCP LV3 +3VS
LV12 285mA SBK160808T-300Y-N_2P ϭϱϬŵ͕ϭϬŵŝů 300ohm 100MHz ESR0.25ohm
2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPE_IOVDD 2 1 +PLLVDD ϭϮϬŵ LV7
BLM18PG181SN1D_0603 add for GB1b-64 MMZ1608D301BT_2P
22U_0603_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

10U_0603_6.3V6M
HDMI@ 1 1 1 1 CV173 1 +DACA_VDD 1 2
CV84

CV173 10K_0402_5% 1 1 1 1 1
CV169
CV87

CV88

CV179

CV180

CV181

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

4.7U_0603_6.3V6K
CV160 CV170 0.1U_0402_16V4Z NHDMI@

4.7U_0603_6.3V6K
HDMI@ HDMI@ HDMI@ HDMI@
2 2 2 2 2
2 2 2 2 2 1 1 1 1 1 1 1

CV107

CV109

CV110

CV108

CV112

CV114
CV113
1U_0402_6.3V6K

+3VS 2 2 2 2 2 2 2
LV8 220mA
4 2 1 1U_0402_6.3V6K 0.1U_0402_16V4Z +IFPE_PLLVDD 4
BLM18PG181SN1D_0603 add for GB1b-64
HDMI@

1 1 1 1 1
CV215
CV178 CV159 CV176 CV182 0.1U_0402_16V4Z CV215
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 2 2 NHDMI@
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12M Power
4.7U_0603_6.3V6K 0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 15 of 53
A B C D E
 A B C D E

FBAD[0..63]
FBAD[0..63] 17,18
FBA_CMD[0..30]
FBA_CMD[0..30] 17,18
DQMA#[0..7]
DQMA#[0..7] 17,18
DQSA_RN[0..7]
DQSA_RN[0..7] 17,18
DQSA_W P[0..7]
DQSA_W P[0..7] 17,18
1 1

UV1B
Part 2 of 5 Mode E - Mirror Mode Mapping
FBAD0 D22 G24 FBA_CMD0
FBAD1 FBA_D0 FBA_CMD0 FBA_CMD1 PAD~D TV6@
E24 FBA_D1 FBA_CMD1 F27 DATA Bus
FBAD2 E22 F25 FBA_CMD2
FBA_D2 FBA_CMD2
FBAD3 D24 F26 FBA_CMD3 Address 0..31 32..63
FBA_CMD3 FBAD4 FBA_D3 FBA_CMD3 FBA_CMD4
D26 FBA_D4 FBA_CMD4 G26
FBAD5 D27 G27 FBA_CMD5 CMD0 ODT_L
FBA_D5 FBA_CMD5
1
10K_0402_5%

FBAD6 C27 G25 FBA_CMD6

FBA_D6 FBA_CMD6
RV66

CKE_1 FBAD7 B27 J25 FBA_CMD7 CMD1 CS1#_L

FBAD8 FBA_D7 FBA_CMD7 FBA_CMD8
A21 FBA_D8 FBA_CMD8 J24
FBAD9 B21 H24 FBA_CMD9 CMD2 CS0#_L
FBAD10 FBA_D9 FBA_CMD9 FBA_CMD10
C21 H22
2

FBAD11 FBA_D10 FBA_CMD10 FBA_CMD11

C19 FBA_D11 FBA_CMD11 J26 CMD3 CKE_L
FBAD12 C18 G22 FBA_CMD12
FBAD13 FBA_D12 FBA_CMD12 FBA_CMD13
D18 FBA_D13 FBA_CMD13 G23 CMD4 A9 A11
FBAD14 B18 J22 FBA_CMD14
FBAD15 FBA_D14 FBA_CMD14 FBA_CMD15
C16 FBA_D15 FBA_CMD15 J27 CMD5 A6 A7
FBA_CMD19 FBAD16 E21 M24 FBA_CMD16
FBAD17 FBA_D16 FBA_CMD16 FBA_CMD17 PAD~D TV5@
F21 FBA_D17 FBA_CMD17 L24 CMD6 A3 BA1
1
10K_0402_5%

FBAD18 D20 J23 FBA_CMD18

FBA_D18 FBA_CMD18
RV68

FBAD19 F20 K23 FBA_CMD19 CMD7 A0 A12

FBAD20 FBA_D19 FBA_CMD19 FBA_CMD20
ODT_2 D17 FBA_D20 FBA_CMD20 K22
FBAD21 F18 M23 FBA_CMD21 CMD8 A8 A8
FBAD22 FBA_D21 FBA_CMD21 FBA_CMD22
D16 K24
2

2 FBAD23 FBA_D22 FBA_CMD22 FBA_CMD23 2

E16 FBA_D23 FBA_CMD23 M27 CMD9 A12 A0
FBAD24 A22 N27 FBA_CMD24
FBAD25 FBA_D24 FBA_CMD24 FBA_CMD25
C24 FBA_D25 FBA_CMD25 M26 CMD10 A1 A2

MEMORY INTERFACE
FBAD26 D21 K26 FBA_CMD26
FBAD27 FBA_D26 FBA_CMD26 FBA_CMD27
B22 FBA_D27 FBA_CMD27 K27 CMD11 RAS# RAS#
FBAD28 C22 K25 FBA_CMD28
FBA_CMD0 FBAD29 FBA_D28 FBA_CMD28 FBA_CMD29
A25 FBA_D29 FBA_CMD29 M25 CMD12 A13 A14
FBAD30 B25 L22 FBA_CMD30
FBA_D30 FBA_CMD30
1
10K_0402_5%

FBAD31 A26 CMD13 BA1 A3

FBA_D31
RV71

FBAD32 U24 C26 DQMA#0

FBAD33 FBA_D32 FBA_DQM0 DQMA#1
ODT_1 V24 FBA_D33 FBA_DQM1 B19 CMD14 A14 A13
FBAD34 V23 D19 DQMA#2
FBAD35 FBA_D34 FBA_DQM2 DQMA#3
R24 D23 CMD15 CAS# CAS#
2

FBAD36 FBA_D35 FBA_DQM3 DQMA#4

T23 FBA_D36 FBA_DQM4 T24
FBAD37 R23 AA23 DQMA#5 CMD16 CKE_H
FBAD38 FBA_D37 FBA_DQM5 DQMA#6
P24 FBA_D38 FBA_DQM6 AB27
FBAD39 P22 T26 DQMA#7 CMD17 CS1#_H
FBAD40 FBA_D39 FBA_DQM7
AC24 FBA_D40
FBAD41 AB23 D25 DQSA_RN0 CMD18 CS0#_H
FBA_CMD16 FBAD42 FBA_D41 FBA_DQS_RN0 DQSA_RN1
AB24 FBA_D42 FBA_DQS_RN1 A18
FBAD43 W24 E18 DQSA_RN2 CMD19 ODT_H
FBA_D43 FBA_DQS_RN2
1
10K_0402_5%

FBAD44 AA22 B24 DQSA_RN3

FBA_D44 FBA_DQS_RN3
RV72

FBAD45 W23 R22 DQSA_RN4 CMD20 RST RST

FBAD46 FBA_D45 FBA_DQS_RN4 DQSA_RN5
CKE_2 W22 FBA_D46 FBA_DQS_RN5 Y24
FBAD47 V22 AA27 DQSA_RN6 CMD21 A7 A6
FBAD48 FBA_D47 FBA_DQS_RN6 DQSA_RN7
AA25 R27
2

FBAD49 FBA_D48 FBA_DQS_RN7

W27 FBA_D49 CMD22 A4 A5
FBAD50 W26 C25 DQSA_W P0
FBAD51 FBA_D50 FBA_DQS_WP0 DQSA_W P1
3
W25 FBA_D51 FBA_DQS_WP1 A19 CMD23 A11 A9 3
FBAD52 AB25 E19 DQSA_W P2
FBAD53 FBA_D52 FBA_DQS_WP2 DQSA_W P3
AB26 FBA_D53 FBA_DQS_WP3 A24 CMD24 A2 A1
FBAD54 AD26 T22 DQSA_W P4
FBA_CMD20 FBAD55 FBA_D54 FBA_DQS_WP4 DQSA_W P5
AD27 FBA_D55 FBA_DQS_WP5 AA24 CMD25 A10 WE#
FBAD56 V25 AA26 DQSA_W P6
FBA_D56 FBA_DQS_WP6
1
10K_0402_5%

FBAD57 R25 T27 DQSA_W P7 CMD26 A5 A4

FBA_D57 FBA_DQS_WP7
RV75

FBAD58 V26
FBAD59 FBA_D58 +FB_VREF
RST V27 FBA_D59 FB_VREF A16 CMD27 BA2 A15
FBAD60 R26
FBAD61 FBA_D60
T25 F24 CLKA0 17 CMD28 WE# A10
2

FBAD62 FBA_D61 FBA_CLK0

N25 FBA_D62 FBA_CLK0_N F23 CLKA0# 17
FBAD63 N26 CMD29 BA0 BA0
FBA_D63
FBA_CLK1 N24 CLKA1 18
FBA_CLK1_N N23 CLKA1# 18 CMD30 A15 BA2
FBA_DEBUG M22 1 2 +1.5V_MEM_GFX
RV76 10K_0402_5%

N12M-GE-S-B1 BGA 533P

+1.5V_MEM_GFX N12MR1@
1.1K_0402_1%
1 RV77

16mil
2

+FB_VREF
4 4
1
1.1K_0402_1%

0.01U_0402_25V7K

1
@
RV78

CV128

2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12M MEM Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 16 of 53
A B C D E
 A B C D E

Memory Partition A - Lower 32 bits

FBA_CMD[0..30]
FBA_CMD[0..30] 16,18
16mil FBAD[0..63]
16mil FBAD[0..63] 16,18
UV4 UV3 DQMA#[0..7]
DQMA#[0..7] 16,18
+FBA_VREF0 M8 E3 FBAD1 +FBA_VREF0 M8 E3 FBAD30 DQSA_RN[0..7]
+1.5V_MEM_GFX VREFCA DQL0 VREFCA DQL0 DQSA_RN[0..7] 16,18
1 H1 F7 FBAD6 H1 F7 FBAD24 1
VREFDQ DQL1 FBAD0 VREFDQ DQL1 FBAD31 DQSA_W P[0..7]
DQL2 F2 DQL2 F2 DQSA_W P[0..7] 16,18
FBA_CMD7 N3 F8 FBAD7 FBA_CMD7 N3 F8 FBAD28
A0 DQL3 A0 DQL3
1
1.1K_0402_1%

FBA_CMD10 P7 H3 FBAD3 Group0 FBA_CMD10 P7 H3 FBAD29 Group3

A1 DQL4 A1 DQL4
RV80

FBA_CMD24 P3 H8 FBAD5 FBA_CMD24 P3 H8 FBAD26

FBA_CMD6 A2 DQL5 FBAD2 FBA_CMD6 A2 DQL5 FBAD25
N2 A3 DQL6 G2 N2 A3 DQL6 G2
FBA_CMD22 P8 H7 FBAD4 FBA_CMD22 P8 H7 FBAD27
FBA_CMD26 A4 DQL7 FBA_CMD26 A4 DQL7
P2 P2
2

FBA_CMD5 A5 FBA_CMD5 A5
R8 A6 R8 A6
FBA_CMD21 R2 D7 FBAD17 FBA_CMD21 R2 D7 FBAD14
+FBA_VREF0 FBA_CMD8 A7 DQU0 FBAD21 FBA_CMD8 A7 DQU0 FBAD10
T8 A8 DQU1 C3 T8 A8 DQU1 C3
FBA_CMD4 R3 C8 FBAD19 FBA_CMD4 R3 C8 FBAD15
A9 DQU2 A9 DQU2
1.1K_0402_1%

0.01U_0402_25V7K

FBA_CMD25 L7 C2 FBAD20 Group2 FBA_CMD25 L7 C2 FBAD11

FBA_CMD23 A10/AP DQU3 FBAD18 FBA_CMD23 A10/AP DQU3 FBAD12
1 R7 A11 DQU4 A7 R7 A11 DQU4 A7 Group1
1

RV79

CV129

FBA_CMD9 N7 A2 FBAD22 FBA_CMD9 N7 A2 FBAD8

FBA_CMD12 T3
A12
A13
DQU5
DQU6 B8 FBAD16 FBA_CMD12 T3
A12
A13
DQU5
DQU6 B8 FBAD13 Mode E - Mirror Mode Mapping
FBA_CMD14 T7 A3 FBAD23 FBA_CMD14 T7 A3 FBAD9
2 FBA_CMD30 A14 DQU7 FBA_CMD30 A14 DQU7
M7 A15/BA3 +1.5V_MEM_GFX
M7 A15/BA3 +1.5V_MEM_GFX
DATA Bus
2

Address 0..31 32..63

FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD13 BA0 VDD FBA_CMD13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD0 ODT_L
FBA_CMD27 M3 G7 FBA_CMD27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD1 CS1#_L
VDD K8 VDD K8
CLKA0 N1 N1 CMD2 CS0#_L
VDD CLKA0 VDD
16 CLKA0 J7 CK VDD N9 J7 CK VDD N9
K7 R1 CLKA0# K7 R1 CMD3 CKE_L
16 CLKA0# CK VDD CK VDD
1

FBA_CMD3 K9 R9 FBA_CMD3 K9 R9
2 RV81 CKE/CKE0 VDD CKE/CKE0 VDD 2
CMD4 A9 A11
243_0402_1%
FBA_CMD0 K1 A1 FBA_CMD0 K1 A1 CMD5 A6 A7
FBA_CMD2 ODT/ODT0 VDDQ FBA_CMD2 ODT/ODT0 VDDQ
L2 A8 L2 A8
2

FBA_CMD11 CS/CS0 VDDQ FBA_CMD11 CS/CS0 VDDQ

J3 RAS VDDQ C1 J3 RAS VDDQ C1 CMD6 A3 BA1
CLKA0# FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
FBA_CMD28 CAS VDDQ FBA_CMD28 CAS VDDQ
L3 WE VDDQ D2 L3 WE VDDQ D2 CMD7 A0 A12
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD8 A8 A8
DQSA_W P0 F3 H2 DQSA_W P3 F3 H2
DQSA_W P2 DQSL VDDQ DQSA_W P1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD9 A12 A0
CMD10 A1 A2
DQMA#0 E7 A9 DQMA#3 E7 A9
DQMA#2 DML VSS DQMA#1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD11 RAS# RAS#
VSS E1 VSS E1
VSS G8 VSS G8 CMD12 A13 A14
DQSA_RN0 G3 J2 DQSA_RN3 G3 J2
DQSA_RN2 DQSL VSS DQSA_RN1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD13 BA1 A3
VSS M1 VSS M1
VSS M9 VSS M9 CMD14 A14 A13
VSS P1 VSS P1
FBA_CMD20 T2 P9 FBA_CMD20 T2 P9 CMD15 CAS# CAS#
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD16 CKE_H
CMD17 CS1#_H
1

1
243_0402_1%

J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1

243_0402_1%
3
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 CMD18 CS0#_H 3
RV82

RV83
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 CMD19 ODT_H
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD20 RST RST
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD21 A7 A6
VSSQ G9 VSSQ G9
CMD22 A4 A5
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD23 A11 A9
K4W 1G1646E-HC12_FBGA96 K4W 1G1646E-HC12_FBGA96
@ @ CMD24 A2 A1
+1.5V_MEM_GFX CMD25 A10 WE#
+1.5V_MEM_GFX
CMD26 A5 A4
CMD27 BA2 A15
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
CMD28 WE# A10
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV139

CV140

CV141

CV142

CV143
CMD29 BA0 BA0
CV1

CV2

CV130

CV131

CV132

CV133

CV134

CV135

CV136

CV3

CV4

CV137

CV138

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CMD30 A15 BA2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12M VRAM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 17 of 53
A B C D E
 A B C D E

Memory Partition A - Upper 32 bits

16mil
16mil UV6 FBAD[0..63]
FBAD[0..63] 16,17
UV5
+FBA_VREF1 M8 E3 FBAD61 FBA_CMD[0..30]
VREFCA DQL0 FBA_CMD[0..30] 16,17
+FBA_VREF1 M8 E3 FBAD35 H1 F7 FBAD57
VREFCA DQL0 FBAD32 VREFDQ DQL1 FBAD58 DQMA#[0..7]
H1 VREFDQ DQL1 F7 DQL2 F2 DQMA#[0..7] 16,17
1 F2 FBAD38 FBA_CMD9 N3 F8 FBAD60 1
FBA_CMD9 DQL2 FBAD33 FBA_CMD24 A0 DQL3 FBAD56 DQSA_RN[0..7]
N3 A0 DQL3 F8 Group4 P7 A1 DQL4 H3 Group7 DQSA_RN[0..7] 16,17
FBA_CMD24 P7 H3 FBAD37 FBA_CMD10 P3 H8 FBAD62
FBA_CMD10 A1 DQL4 FBAD34 FBA_CMD13 A2 DQL5 FBAD59 DQSA_W P[0..7]
P3 A2 DQL5 H8 N2 A3 DQL6 G2 DQSA_W P[0..7] 16,17
FBA_CMD13 N2 G2 FBAD39 FBA_CMD26 P8 H7 FBAD63
FBA_CMD26 A3 DQL6 FBAD36 FBA_CMD22 A4 DQL7
P8 A4 DQL7 H7 P2 A5
+1.5V_MEM_GFX FBA_CMD22 P2 FBA_CMD21 R8
FBA_CMD21 A5 FBA_CMD5 A6 FBAD51
R8 A6 R2 A7 DQU0 D7
1.1K_0402_1%

FBA_CMD5 R2 D7 FBAD42 FBA_CMD8 T8 C3 FBAD52

FBA_CMD8 A7 DQU0 FBAD46 FBA_CMD23 A8 DQU1 FBAD49
T8 A8 DQU1 C3 R3 A9 DQU2 C8
1

RV84

FBA_CMD23 R3 C8 FBAD40 FBA_CMD28 L7 C2 FBAD53

FBA_CMD28 A9 DQU2 FBAD45 FBA_CMD4 A10/AP DQU3 FBAD48
L7 A10/AP DQU3 C2 R7 A11 DQU4 A7 Group6
FBA_CMD4 R7 A7 FBAD44 Group5 FBA_CMD7 N7 A2 FBAD54
FBA_CMD7 A11 DQU4 FBAD43 FBA_CMD14 A12 DQU5 FBAD50
N7 A12 DQU5 A2 T3 A13 DQU6 B8
FBA_CMD14 T3 B8 FBAD41 FBA_CMD12 T7 A3 FBAD55
2

+FBA_VREF1 FBA_CMD12 A13 DQU6 FBAD47 FBA_CMD27 A14 DQU7

T7 A3 M7
FBA_CMD27 M7
A14
A15/BA3
DQU7 A15/BA3 +1.5V_MEM_GFX Mode E - Mirror Mode Mapping
+1.5V_MEM_GFX
1.1K_0402_1%

0.01U_0402_25V7K
1

1 FBA_CMD29 M2 B2 DATA Bus

BA0 VDD
RV85

CV144

FBA_CMD29 M2 B2 FBA_CMD6 N8 D9
BA0 VDD BA1 VDD
FBA_CMD6 N8 BA1 VDD D9 FBA_CMD30 M3 BA2 VDD G7 Address 0..31 32..63
FBA_CMD30 M3 G7 K2
2 BA2 VDD VDD
K2 K8 CMD0 ODT_L
2

VDD VDD
VDD K8 VDD N1
N1 CLKA1 J7 N9 CMD1 CS1#_L
VDD CLKA1# CK VDD
16 CLKA1 J7 CK VDD N9 K7 CK VDD R1
K7 R1 FBA_CMD16 K9 R9 CMD2 CS0#_L
16 CLKA1# CK VDD CKE/CKE0 VDD
FBA_CMD16 K9 R9
CKE/CKE0 VDD
CMD3 CKE_L
2 FBA_CMD19 K1 A1 2
FBA_CMD19 FBA_CMD18 ODT/ODT0 VDDQ
K1 ODT/ODT0 VDDQ A1 L2 CS/CS0 VDDQ A8 CMD4 A9 A11
FBA_CMD18 L2 A8 FBA_CMD11 J3 C1
CLKA1 FBA_CMD11 CS/CS0 VDDQ FBA_CMD15 RAS VDDQ
J3 RAS VDDQ C1 K3 CAS VDDQ C9 CMD5 A6 A7
FBA_CMD15 K3 C9 FBA_CMD25 L3 D2
FBA_CMD25 CAS VDDQ WE VDDQ
L3 WE VDDQ D2 VDDQ E9 CMD6 A3 BA1
1

VDDQ E9 VDDQ F1
RV86 F1 DQSA_W P7 F3 H2 CMD7 A0 A12
243_0402_1% DQSA_W P4 VDDQ DQSA_W P6 DQSL VDDQ
F3 DQSL VDDQ H2 C7 DQSU VDDQ H9
DQSA_W P5 C7 H9 CMD8 A8 A8
DQSU VDDQ
2

DQMA#7 E7 A9 CMD9 A12 A0

CLKA1# DQMA#4 DQMA#6 DML VSS
E7 DML VSS A9 D3 DMU VSS B3
DQMA#5 D3 B3 E1 CMD10 A1 A2
DMU VSS VSS
VSS E1 VSS G8
G8 DQSA_RN7 G3 J2 CMD11 RAS# RAS#
DQSA_RN4 VSS DQSA_RN6 DQSL VSS
G3 DQSL VSS J2 B7 DQSU VSS J8
DQSA_RN5 B7 J8 M1 CMD12 A13 A14
DQSU VSS VSS
VSS M1 VSS M9
VSS M9 VSS P1 CMD13 BA1 A3
P1 FBA_CMD20 T2 P9
FBA_CMD20 VSS RESET VSS
T2 RESET VSS P9 VSS T1 CMD14 A14 A13
VSS T1 L8 ZQ/ZQ0 VSS T9
L8 ZQ/ZQ0 VSS T9 CMD15 CAS# CAS#

1
243_0402_1%
J1 NC/ODT1 VSSQ B1 CMD16 CKE_H
1
243_0402_1%

RV88
J1 NC/ODT1 VSSQ B1 L1 NC/CS1 VSSQ B9
RV87

L1 NC/CS1 VSSQ B9 J9 NC/CE1 VSSQ D1 CMD17 CS1#_H

J9 NC/CE1 VSSQ D1 2 L9 NCZQ1 VSSQ D8
3 3
L9 NCZQ1 VSSQ D8 VSSQ E2 CMD18 CS0#_H
E2 E8
2

VSSQ VSSQ
VSSQ E8 VSSQ F9 CMD19 ODT_H
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9 CMD20 RST RST
VSSQ G9
96-BALL CMD21 A7 A6
96-BALL SDRAM DDR3
SDRAM DDR3 K4W 1G1646E-HC12_FBGA96 CMD22 A4 A5
K4W 1G1646E-HC12_FBGA96 @
@ CMD23 A11 A9
+1.5V_MEM_GFX +1.5V_MEM_GFX CMD24 A2 A1
CMD25 A10 WE#
CMD26 A5 A4
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CMD27 BA2 A15
CV148

CV149

CV150

CV151

CV154

CV155

CV156

CV157

CV158
CV5

CV6

CV145

CV146

CV147

CV7

CV8

CV152

CV153

CMD28 WE# A10

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CMD29 BA0 BA0
CMD30 A15 BA2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P VRAM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 18 of 53
A B C D E
 A B C D E

+LCD_VDD +3VS

Reserve for EMI request

1
1 1

1
R107
1 @ 2 150_0603_5% R108
R78 0_0402_5% 100K_0402_5% +3VS
L55 CAM@ W=80mils

2
1 1 USB20_P11_R
25 USB20_P11 2 2

2
6
25 USB20_N11 4 3 USB20_N11_R 2
4 3 Q1A C228
W CM-2012-900T_0805 2 0.1U_0402_16V7K

3
S
1 G
1 @ 2 2N7002KDW H_SOT363-6 1 R109 2LCDPW R_GATE 2 Q17

1
R96 0_0402_5% 47K_0402_5% 1 AO3413_SOT23

3
D

1
C229 +LCD_VDD
0.01U_0402_25V7K W=80mils
Q1B 2
13 VGA_ENVDD 5
1
2N7002KDW H_SOT363-6 C233

4
0.1U_0402_16V4Z

2
8/20 Swap USB20_P11 and USB20_N11 for layout request 2
R112
100K_0402_5%

1
2
LCD/PANEL BD. Conn. 2

Pin13 GND for EMI , But Cable is NC CAM@ W=20mils

0.1U_0402_16V4Z
2 1 +3VS_LVDS_CAM 2 CAM@ 1 +3VS
C225 0_0603_5% R388
JLVDS @
1 1
31 2 D84 @
G1 2 USB20_N11_R
32 G2 3 3 2
33 4 USB20_P11_R 1
G3 4
34 G4 5 5 3
6 INT_MIC_CLK
6 INT_MIC_CLK 36
7 INT_MIC_DATA PACDN042Y3R_SOT23-3
7 INT_MIC_DATA 36
8 +LCD_VDD_R
8
9 9
10 10 +3VS
11 LCD_EDID_CLK LCD_EDID_CLK 13
11 LCD_EDID_DATA
12 12 LCD_EDID_DATA 13
13 13
14 14 LCD_TXOUT0- 14 For EMI 1 1
15 LCD_TXOUT0+ 14 @
15 C231 C232
16 16
17 LCD_TXOUT1- 14 680P_0402_50V7K 0.1U_0402_16V4Z
17 2 2
18 18 LCD_TXOUT1+ 14
19 19
20 20 LCD_TXOUT2- 14
21 21 LCD_TXOUT2+ 14
22 22 1 2
3 R120 47K_0402_5% 3
23 23 LCD_TXCLK- 14
24 LCD_TXCLK+ 14 D2
24 VGA_D_PW M
25 25 1 2 VGA_PW M 13
26 BKOFF#_R
26 RB751V40_SC76-2
27 27
28 28 1 D1 2 BKOFF# 38
29 RB751V40_SC76-2
29
30 30 1 2 1.5A
R113 10K_0402_5% +LCD_VDD_R 2 L15 1 +LCD_VDD
+LCD_INV 0_0805_5%
ACES_88341-3001 1 1
B+ C226 C227
Rated Current MAX:600mA 0.1U_0402_16V4Z 4.7U_0805_10V4Z
L2 2 2
2 1
1 1 FBMA-L11-201209-221LMA30T_0805

C234 C235
68P_0402_50V8J 0.1U_0402_25V6
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/eDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 19 of 53
A B C D E
 A B C D E

CRT CONNECTOR

1
D3 @ D4 @ D5 @
+3VS
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1 40 mils

3
1 1 2
1 3 RB491D_SOT23-3 1 1
1.1A_6V_MINISMDC110F-2
C237
0.1U_0402_16V4Z
L3 2
13 VGA_CRT_R 1 2 NBQ100505T-800Y_0402 CRT_R_L @

13 VGA_CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L

13 VGA_CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L

JCRT @
6 6
T76 PAD 11
R138 R139 R140 CRT_R_L 11
1

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
1

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 7 7

1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 12
2 2
8 8
2 2 2 2 2 2 HSYNC 13 13
CRT_B_L 3

2
3
+CRT_VCC 9 9
VSYNC 14 16
T77 PAD 14 G
4 4 G 17
10 10
CRT_DDC_CLK 15 15
5 5
ALLTO_C10532-11505-L_15P-T

2 2
+CRT_VCC

1 2
C244 0.1U_0402_16V4Z 2 1
R141 10K_0402_5%

5
1 OE#
P
2 4 D_CRT_HSYNC 1 2 HSYNC
13 VGA_CRT_HSYNC A Y
+CRT_VCC L6 10_0402_5%

G
U6
SN74AHCT1G125GW _SOT353-5

5
1
OE#
P
2 4 D_CRT_VSYNC 1 2 VSYNC
13 VGA_CRT_VSYNC A Y L7 10_0402_5%

10P_0402_50V8J

10P_0402_50V8J
1 1

G
U7
SN74AHCT1G125GW _SOT353-5 C245 C246

3
@ @
2 2

3 3

+CRT_VCC

+3VS

2
R153 R159
4.7K_0402_5% 4.7K_0402_5%

1
2
Q205A

13 VGA_CRT_CLK 5 1 6 CRT_DDC_CLK

2N7002KDW H_SOT363-6
Q205B
13 VGA_CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002KDW H_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 20 of 53
A B C D E
 A B C D E

U2A
CMOS Setting, near DDR Door JCOMS @ PCH_RTCX1 LPC_AD0
2 1 A20 RTCX1 FWH0 / LAD0 C38 LPC_AD0 38,39
R292 1 2 PCH_RTCRST# 1 2 C216 15P_0402_50V8J A38 LPC_AD1

LPC
+RTCVCC FWH1 / LAD1 LPC_AD1 38,39
20K_0402_5% Y3 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 38,39

1
C247 2 LPC_AD3

10M_0402_5%
1 2 NC OSC 1 FWH3 / LAD3 C37 LPC_AD3 38,39
1U_0402_6.3V6K PCH_RTCRST# D20 RTCRST#

R291
3 4 D36 LPC_FRAME#
NC OSC FWH4 / LFRAME# LPC_FRAME# 38,39
PCH_SRTCRST# G22
32.768KHZ_12.5PF_Q13MC14610002 SRTCRST#
iME Setting. E36

RTC
2
JME @ SM_INTRUDER# LDRQ0#
2 1 K22 INTRUDER# LDRQ1# / GPIO23 K36
R293 1 2PCH_SRTCRST# 1 2 C205 15P_0402_50V8J
20K_0402_5% PCH_INTVRMEN C17 V5 SERIRQ
INTVRMEN SERIRQ SERIRQ 38,39
1 C248 2 1 1
1U_0402_6.3V6K
AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 31
R286 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0
36 AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 31

SATA 6G
AP7 SATA_PTX_DRX_N0
Integrated SUS 1.05V VRM Enable AZ_SYNC L34
SATA0TXN
AP5 SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 31 HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 31
High - Enable Internal VRs PCH_SPKR T10 AM10
36 PCH_SPKR SPKR SATA1RXN
PCH_INTVRMEN (must be always pulled high) SATA1RXP AM8
R142 1 2 33_0402_5% AZ_RST# K34 AP11
36 AZ_RST_HD# HDA_RST# SATA1TXN
SATA1TXP AP10
+RTCVCC AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
36 AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 31
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 31
R117 1 2 SM_INTRUDER# G34 AH5 SATA_PTX_DRX_N2
1M_0402_5% HDA_SDIN1 SATA2TXN
AH4 SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 31 ODD
SATA2TXP SATA_PTX_DRX_P2 31 +3VS
R118 1 2 PCH_INTVRMEN C34

IHDA
330K_0402_5% HDA_SDIN2
+3VS
PCH_SPK SATA3RXN AB8
+3VALW 2 @ 1 A34 AB10
@ High = Enabled (No Reboot) R273 1K_0402_5% HDA_SDIN3 SATA3RXP
AF3 SERIRQ 2 1
SATA3TXN
1 2 PCH_SPKR Low = Disabled (Default) SATA3TXP AF1 R136 10K_0402_5%
R276 1K_0402_5% R289 1 2 33_0402_5% AZ_SDOUT A36 +3VS
36 AZ_SDOUT_HD

SATA
HDA_SDO
SATA4RXN Y7
+3VALW Y5
R580 1 SATA4RXP
38 PW RME_CTRL# 2 0_0402_5% C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3
1 2 CR_CPPE# AD1 SATA_LED# R336 2 1 10K_0402_5%
R560 10K_0402_5% CR_CPPE# SATA4TXP
N32 HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS Y1 CR_W AKE# R334 2 1 10K_0402_5%
2 SATA5RXP 2
SATA5TXN AB3
PCH_JTAG_TCK J3 AB1
JTAG_TCK SATA5TXP PCH_GPIO19 R335 1 2 10K_0402_5%
T37 PAD PCH_JTAG_TMS H7 Y11

JTAG
JTAG_TMS SATAICOMPO
PCH_JTAG_TDI K5 Y10 SATAICOMP 1 2
HDA_SDO
T38 PAD JTAG_TDI SATAICOMPI +1.05VS_VCC_SATA
R279 37.4_0402_1%
T39 PAD PCH_JTAG_TDO H1 JTAG_TDO
ME debug mode, SATA3RCOMPO AB12
this signal has a weak internal pull down AB13 SATA3_COMP 1 2
SATA3COMPI +1.05VS_SATA3
R280 49.9_0402_1%
*Low = Disable (default)
High = Enable (flash descriptor security overide) PCH_SPICLK T3 AH1 RBIAS_SATA3 1 2
SPI_CLK SATA3RBIAS R281 750_0402_1%
PCH_SPICS# Y14
HDA_SYNC
SPI_CS0#
T1

SPI
SPI_CS1# SATA_LED#
*This signal has a weak internal pull
H=>On Die PLL is supplied by 1.5V
down SATALED# P3

PCH_SPIDI V4 V14 CR_W AKE#

SPI_MOSI SATA0GP / GPIO21
L=>On Die PLL is supplied by 1.8V
PCH_SPIDO U3 P1 PCH_GPIO19
Need to pull high for Huron River platform SPI_MISO SATA1GP / GPIO19 PCH_GPIO19 25
2 1 AZ_SYNC BOOT BIOS Strap Bit 0
+3VALW
R284 1K_0402_5%
for EMI COUGARPOINT_FCBGA989~D HM65R1@

+5VS
2

3 3
G

Q21
1 2 AZ_SYNC_R 3 1
36 AZ_SYNC_HD
R156 33_0402_5%
RTC schematic for non-chargeable
S

1 2 BSS138_NL_SOT23-3
R125 1M_0402_5% 1 @ 2 +3VALW +3VALW +3VALW
R285 0_0402_5%
D13 +RTCBATT
+RTCVCC

2
3 +3VL
1 R363 R330 R278
1 2 2 1 200_0402_5% 200_0402_5% 200_0402_5%
R277 1K_0402_5%
C486

1
BAV70W _SOT323-3

1
0.1U_0402_16V4Z PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
2
4M Byte

2
+3VS R306 R295 R301
100_0402_1% 100_0402_1% 100_0402_1%
@ JRTC
LOTES_AAA-BAT-054-K01

1
U13 1
PCH_SPICS# 1 8 C494 PCH_SPICLK
PCH_SPIDO CS# VCC
2 DO HOLD# 7
1

3 6 PCH_SPICLK 0.1U_0402_16V4Z 1 2 PCH_JTAG_TCK

WP# CLK PCH_SPIDI 2 R397 R355 51_0402_1%
4 GND DI 5
-

10_0402_5%
W 25Q32BVSSIG_SO8 @
2
2

4 4

C86
1 0812 -> Add R277 for RTC reserve charge
10P_0402_50V8J
@
2
Socket: SP07000F500/SP07000H900
Security Classification Compal Secret Data Compal Electronics, Inc.
Please close to U2 PCH Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

8/30 Change U13 from SA000021A00 to SA00003IN00 due to EOL of SA000021A00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_HDA/JTAG/SATA/SPI/LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 21 of 53
A B C D E
 A B C D E

U2B +3VALW 2 R232 1 2.2K_0402_5% +3VS

PCIE_PRX_C_LANTX_N1 BG34 2 R260 1 2.2K_0402_5% R400 4.7K_0402_5%
33 PCIE_PRX_C_LANTX_N1 PERN1

5
PCIE_PRX_C_LANTX_P1 BJ34 E12 EC_LID_OUT# EC_LID_OUT# 38 Q3B R386 4.7K_0402_5%
33 PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11
LAN 33 PCIE_PTX_C_LANRX_N1 C498 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 AV32
C497 2 PETN1
33 PCIE_PTX_C_LANRX_P1 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 AU32 PETP1 SMBCLK H14 PCH_SMBCLK PCH_SMBDATA 3 4 PM_SMBDATA 11,12,32

2
PCIE_PRX_W LANTX_N2 BE34 C9 PCH_SMBDATA 2N7002KDW H_SOT363-6
32 PCIE_PRX_W LANTX_N2 PERN2 SMBDATA
WLAN PCIE_PRX_W LANTX_P2 BF34 Q3A
32 PCIE_PRX_W LANTX_P2 PERP2
32 PCIE_PTX_C_W LANRX_N2 C501 2 1 0.1U_0402_16V7K PCIE_PTX_W LANRX_N2 BB32 PCH_SMBCLK 6 1
PETN2 PM_SMBCLK 11,12,32
32 PCIE_PTX_C_W LANRX_P2 C502 2 1 0.1U_0402_16V7K PCIE_PTX_W LANRX_P2 AY32

SMBUS
PETP2
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH 2N7002KDW H_SOT363-6
1 BG36 PERN3 7 DRAMRST_CNTRL_PCH 1
BJ36 C8 PCH_SMLCLK0
PERP3 SML0CLK
AV34 PETN3
AU34 G12 PCH_SMLDATA0
+3VS PETP3 SML0DATA
+3VALW 2 R364 1 2.2K_0402_5% +3VS
BF36 PERN4
R287 1 2 10K_0402_5% CLKREQ_JET# BE36 2 R385 1 2.2K_0402_5%
PERP4

5
AY34 C13 PCH_GPIO74 Q4B
R338 1 PETN4 SML1ALERT# / PCHHOT# / GPIO74
2 10K_0402_5% CLKREQ_W LAN# BB34 PETP4
2N7002KDW H_SOT363-6
E14 PCH_SMLCLK1 PCH_SMLDATA1 3 4

PCI-E*
SML1CLK / GPIO58 EC_SMB_DA2 13,38
BG37 PERN5

2
BH37 M16 PCH_SMLDATA1 Q4A
PERP5 SML1DATA / GPIO75
AY36 PETN5
BB36 PCH_SMLCLK1 6 1
PETP5 EC_SMB_CK2 13,38

35 PCIE_PRX_C_USBTX_N6 PCIE_PRX_C_USBTX_N6 BJ38 2N7002KDW H_SOT363-6

PCIE_PRX_C_USBTX_P6 PERN6
USB30 35 PCIE_PRX_C_USBTX_P6 BG38

Controller
C519 1 PERP6
35 PCIE_PTX_C_USBRX_N6 2 0.1U_0402_16V7K PCIE_PTX_USBRX_N6 AU36 PETN6 CL_CLK1 M7
C869 1 2 0.1U_0402_16V7K PCIE_PTX_USBRX_P6 AV36
35 PCIE_PTX_C_USBRX_P6 PETP6
Control Link only for support Intel IAMT.

Link
+3VALW BG40 T11
PERN7 CL_DATA1
BJ40 PERP7
AY40 +3VALW
R343 1 PETN7
210K_0402_5% CLKREQ_LAN# BB40 PETP7 CL_RST1# P10

R344 1 210K_0402_5% PCH_GPIO26 BE38 EC_LID_OUT# R123 1 2 10K_0402_5%

PERN8
BC38 PERP8
R345 1 210K_0402_5% CLKREQ_CR# AW38 DRAMRST_CNTRL_PCH R228 1 2 1K_0402_5%
PETN8
AY38 PETP8
2 R346 1 210K_0402_5% CLKREQ_USB30# PCH_GPIO74 R234 1 2 10K_0402_5% 2
M10 CLK_REQ_VGA#
R348 1 PEG_A_CLKRQ# / GPIO47
210K_0402_5% PANEL_SEL
33 CLK_LAN#
CLK_LAN# Y40 CLKOUT_PCIE0N
PCH_SMLCLK0 R238 1 2 10K_0402_5%
LAN CLK_LAN Y39
33 CLK_LAN CLKOUT_PCIE0P
R351 1 210K_0402_5% PASSW ORD_CLEAR# AB37 CLK_PCIE_VGA# PCH_SMLDATA0 R239 1 2 10K_0402_5%
CLKOUT_PEG_A_N CLK_PCIE_VGA# 13

CLOCKS
CLKREQ_LAN# J2 AB38 CLK_PCIE_VGA R23
33 CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA 13
1 2 CLK_REQ_VGA# @ R251 1 2 10K_0402_5%

R584 1 @ 2 10K_0402_5% PANEL_SEL CLK_W LAN# AB49 AV22 CLK_CPU_DMI# 10K_0402_5%

32 CLK_W LAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
WLAN CLK_W LAN AB47 AU22 CLK_CPU_DMI
32 CLK_W LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
R564 1 @ 2 10K_0402_5% LVDS_SEL PCH_CLK_DMI# R242 1 2 10K_0402_5%
CLKREQ_W LAN# M1 PCH_CLK_DMI R243 1 2 10K_0402_5%
32 CLKREQ_W LAN# PCIECLKRQ1# / GPIO18
AM12 CLK_DPLL# T13 PAD
CLKOUT_DP_N / CLKOUT_BCLK1_N CLK_DPLL CLKIN_GND1# R244 1
CLKOUT_DP_P / CLKOUT_BCLK1_P AM13 T14 PAD 120 MHz for eDP 2 10K_0402_5%
AA48 CLKIN_GND1 R245 1 2 10K_0402_5%
CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 PCH_CLK_DMI# CLK_DOT# R246 1 2 10K_0402_5%
CLKREQ_JET# CLKIN_DMI_N PCH_CLK_DMI CLK_DOT R247 1
LVDS_SEL V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 10K_0402_5%

CLK_SATA# R248 1 2 10K_0402_5%

LVDS_SEL H L Y37 CLKIN_GND1_N CLKIN_DMI2_N BJ30 CLKIN_GND1# CLK_SATA R249 1 2 10K_0402_5%
CLKOUT_PCIE3N CLKIN_GND1
Y36 CLKOUT_PCIE3P CLKIN_GND1_P CLKIN_DMI2_P BG30
CLK_14M_PCH R250 1 2 10K_0402_5%
Single CLKREQ_CR# A8 PCIECLKRQ3# / GPIO25 CLK_DOT#
Channel (Default) Dual CLKIN_DOT_96N G24
From Clock Gen.
E24 CLK_DOT
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P
AK7 CLK_SATA#
3 PCH_GPIO26 L12
CLKIN_SATA_N / CKSSCD_N
AK5 CLK_SATA
For EMI 3
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P
PANEL_SEL USB30 @
CLK_USB30# V45 K45 CLK_14M_PCH CLK_PCILOOP 2 @ 1 2 1
35 CLK_USB30# CLKOUT_PCIE5N REFCLK14IN
CLK_USB30 V46 R417 10_0402_5% C474 22P_0402_50V8J
35 CLK_USB30 CLKOUT_PCIE5P
PANEL_SEL H L
35 CLKREQ_USB30# CLKREQ_USB30#
L14 PCIECLKRQ5# / GPIO44 H45 CLK_PCILOOP
CLKIN_PCILOOPBACK CLK_PCILOOP 25
Please place under
Channel LVDS EDP DDR SODIMM. AB42 V47 PCH_X1
CLKOUT_PEG_B_N XTAL25_IN PCH_X2
10/25 AB40 CLKOUT_PEG_B_P XTAL25_OUT V49

PASSW ORD_CLEAR# E6 PEG_B_CLKRQ# / GPIO56

1

JPW Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN

+3VALW @ XCLK_RCOMP R354 90.9_0402_1% R365 2
V40 CLKOUT_PCIE6N 1 1M_0402_5%
V42
2

CLKOUT_PCIE6P
Y2
R347 1 2 10K_0402_5% LVDS_SEL T13 PCH_X1 1 2 PCH_X2
PCIECLKRQ6# / GPIO45
V38 K43 CLK_FLEX0 1 @ R578 2 1 25MHZ_20PF_7A25000012 1
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 48MCLK_USB30 35
22_0402_5% C506 C507
FLEX CLOCKS

V37 CLKOUT_PCIE7P
R233 2 @ 1 0_0402_5% F47 PCH_48MCLK 1 R576 2
10 CLK_RES_ITP# CLKOUTFLEX1 / GPIO65 48MCLK_CR 34
R282 2 @ 1 0_0402_5% PANEL_SEL K12 22_0402_5% 27P_0402_50V8J 27P_0402_50V8J
10 CLK_RES_ITP PCIECLKRQ7# / GPIO46 2 2
H47 CLK_FLEX2 T31 PAD
R352 CLKOUTFLEX2 / GPIO66
5 CLK_CPU_ITP# 2 1 0_0402_5% CLK_BCLK_ITP# AK14 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
R353 2 1 0_0402_5% CLK_BCLK_ITP AK13 K49 CLK_FLEX3 1 @ 2 CLK_27M
5 CLK_CPU_ITP CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 CLK_27M 13
R38 0_0402_5%
4 4
COUGARPOINT_FCBGA989~D HM65R1@
Near PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_PCI-E/SMBUS/CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 22 of 53
A B C D E
 A B C D E

U2C

6 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 6
6 DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 6
6 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 6
6 DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
+3VALW DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 6
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 6
1 6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 1
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 6
6 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 6
2 1 DRAMPW ROK 6 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 6
R316 200_0402_5% 6 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
PCH_SUSPW RDN_R DMI3RXP FDI_CTX_PRX_P0
2 1 FDI_RXP0 BG14 FDI_CTX_PRX_P0 6
R218 10K_0402_5% DMI_PTX_CRX_N0 AW24 BB14 FDI_CTX_PRX_P1
6 DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 6
2 1 RI# DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
6 DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 6
R220 10K_0402_5% DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 6
2 1 PCH_LOW _BAT# DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4

DMI
FDI
6 DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 6
R221 10K_0402_5% BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 6
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 6
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
6 DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 6
DMI_PTX_CRX_P2 AY18
6 DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
6 DMI_PTX_CRX_P3 DMI3TXP
2 1 PCH_RSMRST# AW16 FDI_INT
FDI_INT FDI_INT 6
R127 10K_0402_5% PCH_DPW ROK 1 2 PCH_RSMRST#
2 1 PM_PW ROK +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0 R222 0_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 6
R128 10K_0402_5% R130 49.9_0402_1%
2 1 SYS_PW ROK BG25 BC10 FDI_FSYNC1 Stuff R222 if do not support DeepSX state
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 6
R129 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 6
R160 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 6

0_0402_5% 8/30 Reserve R259 For cost down plan A18 DSW VREN +RTCVCC
DSWVRMEN
1 @ R259 2

System Power Management

2 +3VS PAD T34 SUSACK# C12 E22 PCH_DPW ROK DSW VREN R224 2 1 330K_0402_5% 2
0.1U_0402_16V4Z SUSACK# DPWROK
1 2 R225 2 @ 1 330K_0402_5%
C250 5 XDP_DBRESET# XDP_DBRESET# K3 B9 EC_SW I#
SYS_RESET# WAKE# EC_SW I# 33,35
5

U12
1
P

5,38,49 VGATE IN1

4 SYS_PW ROK P12 N3 PM_GPIO32 DSWVREN must be always pulled high to +RTCVCC
PM_PW ROK O SYS_PWROK CLKRUN# / GPIO32
2

烉
5,38 PM_PW ROK IN2
G

* DSWVREN - Internal Deep Sleep 1.05V regulator

烉
SN74AHC1G08DCKR_SC70-5 PM_PW ROK 1 2 PM_PW ROK_R L22 G8 SUS_STAT# T17 PAD
H Enable
3

R216 0_0402_5% PWROK SUS_STAT# / GPIO61

32.768 KHz L Disable
L10 APWROK SUSCLK / GPIO62 N14 CLK_EC 38

DRAMPW ROK B13 D10 PM_SLP_S5#

5 DRAMPW ROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 38
SUSACK# 2 @ 1 PCH_SUSPW RDN_R +3VS
R137 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
38 PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# 38
PM_GPIO32 R313 1 2 8.2K_0402_5%
Stuff R137 if EC does not want to 38 PCH_SUSPW RDN 1 2 PCH_SUSPW RDN_R K16 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# F4 PM_SLP_S3#
PM_SLP_S3# 38
R320 0_0402_5%
involve in the handshake mechanism 8/18 Change Net name from PM_CLKRUN# to
for the DeepSX state entry and exit 5,38 PBTN_OUT# PBTN_OUT# E20 PWRBTN# SLP_A# G10 PM_SLP_A# T35 PAD
PCH_GPIO32 by HW Review demand
1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T58 PAD +3VALW
+3VALW ACPRESENT / GPIO31 SLP_SUS#
R469 330K_0402_5%
3 3
D12
PCH_LOW _BAT# E10 AP14 H_PM_SYNC EC_SW I# R319 1 2 10K_0402_5%
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
38,44 ACIN 1 2

RI# A10 K14 PCH_GPIO29 PCH_GPIO29 R563 1 @ 2 10K_0402_5%

RB751V40_SC76-2 RI# SLP_LAN# / GPIO29

COUGARPOINT_FCBGA989~D HM65R1@

H_PM_SYNC C898 1 2 220P_0402_50V7K

@

9/1 Reserve C894 for ESD requset

D16
PM_PW ROK 2 1 PCH_RSMRST#

RB751V40_SC76-2
D14

43,45 POK 1 2

RB751V40_SC76-2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_DMI/FDI/PM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 23 of 53
A B C D E
 A B C D E

U2D
J47 L_BKLTEN SDVO_TVCLKINN AP43
M45 L_VDD_EN SDVO_TVCLKINP AP45

P45 L_BKLTCTL SDVO_STALLN AM42

SDVO_STALLP AM40
T40 L_DDC_CLK
K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
1 LCTL_CLK T45 1
LCTL_DATA L_CTRL_CLK
P39 L_CTRL_DATA
1 2 LVDS_IBG AF37 P38
R219 2.37K_0402_1% LVD_IBG SDVO_CTRLCLK
AF36 LVD_VBG SDVO_CTRLDATA M39
T40 PAD
AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
AT47 100K_0402_5%
DDPB_AUXP R1433
DDPB_HPD AT40 1 2
AK39

LVDS
LVDSA_CLK#
AK40 LVDSA_CLK DDPB_0N AV42
DDPB_0P AV40
+3VS AN48 AV45
LVDSA_DATA#0 DDPB_1N
AM47 AV46

Digital Display Interface

LVDSA_DATA#1 DDPB_1P
AK47 LVDSA_DATA#2 DDPB_2N AU48
2 1 LCTL_CLK AJ48 AU47
R471 2.2K_0402_5% LVDSA_DATA#3 DDPB_2P
DDPB_3N AV47
AN47 LVDSA_DATA0 DDPB_3P AV49
2 1 LCTL_DATA AM49
R472 2.2K_0402_5% LVDSA_DATA1
AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42

AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 AT38 R473 2 1 100K_0402_5%
LVDSB_DATA#0 DDPC_HPD
AH47 LVDSB_DATA#1
2 AF49 AY47 2
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49

N48 CRT_BLUE DDPD_CTRLCLK M43

P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED
AT45

CRT
DDPD_AUXN
T39 CRT_DDC_CLK DDPD_AUXP AT43
M40 BH41 R524 2 1 100K_0402_5%
CRT_DDC_DATA DDPD_HPD

DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
2 1 CRT_IREF T43 BE42
R311 1K_0402_0.5% DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42

COUGARPOINT_FCBGA989~D HM65R1@
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CRT/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 24 of 53
A B C D E
 A B C D E

U2E
NV_CE#0 AY7
+3VS AV7
NV_CE#1
BG26 TP1 NV_CE#2 AU3
RP1 BJ26 BG4
PCI_PIRQC# TP2 NV_CE#3
8 1 BH25 TP3
7 2 PCH_GPIO4 BJ16 AT10
PCH_GPIO2 TP4 NV_DQS0
6 3 BG16 TP5 NV_DQS1 BC8
5 4 PCI_PIRQA# AH38 TP6
AH37 TP7 NV_DQ0 / NV_IO0 AU2
8.2K_0804_8P4R_5% AK43 AT4
TP8 NV_DQ1 / NV_IO1
8/23 PIN swap for layout request AK45 TP9 NV_DQ2 / NV_IO2 AT3
RP2 C18 AT1
PCH_GPIO52 TP10 NV_DQ3 / NV_IO3
1 8 1 N30 TP11 NV_DQ4 / NV_IO4 AY3 1
7 2 PCH_GPIO53 H3 AT5
PCH_GPIO54 TP12 NV_DQ5 / NV_IO5
6 3 AH12 AV3

NVRAM
RF_OFF# TP13 NV_DQ6 / NV_IO6
5 4 AM4 TP14 NV_DQ7 / NV_IO7 AV1
AM5 TP15 NV_DQ8 / NV_IO8 BB1
8.2K_0804_8P4R_5% Y13 BA3
TP16 NV_DQ9 / NV_IO9
K24 TP17 NV_DQ10 / NV_IO10 BB5
RP3 L24 BB3 DMI & FDI Termination Voltage
PCH_GPIO50 TP18 NV_DQ11 / NV_IO11
8 1 AB46 TP19 NV_DQ12 / NV_IO12 BB7
7 2 PCI_PIRQB# AB45 BE8

RSVD
ODD_DA# TP20 NV_DQ13 / NV_IO13
6 3 NV_DQ14 / NV_IO14 BD4 Set to VCC when HIGH
5 4 W L_OFF# BF6 NV_CLE
NV_DQ15 / NV_IO15
Set to VSS when LOW
8.2K_0804_8P4R_5% B21 AV5
TP21 NV_ALE NV_CLE
M20 TP22 AY1
1 2 PCH_GPIO5 AY16 TP23
DF_TVS NV_CLE
R321 8.2K_0402_5% BG46 AV10 +1.8VS
PCI_PIRQD# TP24 NV_RCOMP
1 2
R322 8.2K_0402_5% AT8
NV_RB#

1
BE28 AY5 R324
TP25 NV_RE#_WRB0
BC30 TP26 NV_RE#_WRB1 BA2 2.2K_0402_5%
BE32 TP27
Boot BIOS Strap BJ32 AT12

2
TP28 NV_WE#_CK0 NV_CLE
BC28 TP29 NV_WE#_CK1 BF3 2 1 H_SNB_IVB# 5
RF_OFF# PCH_GPIO19 Boot BIOS Loaction BE30 R323 1K_0402_5%
TP30
BF32 TP31
LPC USB20_N0
0 0 BG32 TP32 USBP0N C24
USB20_P0
USB20_N0 31
8/18 Change R324 From 1K to 2.2K by
2
AV26 TP33 USBP0P A24
USB20_N1
USB20_P0 31 USB-LEFT1 2
0 1 Reserved BB26 TP34 USBP1N C25
USB20_P1
USB20_N1 31 Intel check list demand
AU28 TP35 USBP1P B25 USB20_P1 31 USB-LEFT2
1 0 PCI AY30 TP36 USBP2N C26
AU26 TP37 USBP2P A26
1 1 SPI * AY26 TP38 USBP3N K28
H_SNB_IVB# C895
AV28 TP39 USBP3P H28 1 2 220P_0402_50V7K
AW30 EHCI 1 E28 @
TP40 USBP4N
USBP4P D28
1K_0402_5% 2 @ 1 R537 RF_OFF# C28
USBP5N
USBP5P A28
1K_0402_5% 2 @ 1 R538 PCH_GPIO19 C29 9/1 Reserve C895 for ESD requset
PCH_GPIO19 21 USBP6N
B29
PCI_PIRQA# K40
USBP6P
N28
USB port6 and port7 are disabled on HM65
PCI_PIRQB# PIRQA# USBP7N
K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P
H38 PIRQC# USBP8N L30
PCI_PIRQD# G38 K30
PIRQD# USBP8P +3VALW
USBP9N G30 USB20_N9 32
A16 Swap Override Strap PCH_GPIO50 C46 E30 WiMax

USB
REQ1# / GPIO50 USBP9P USB20_P9 32
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 34
Low= A16 swap override Enable PCH_GPIO54 E40 EHCI 2 A30 USB20_P10 Card Reader RP4
REQ3# / GPIO54 USBP10P USB20_P10 34
WL_OFF# L32 USB20_N11 SLP_CHG_M4 4 5
* High= A16 swap override Disable RF_OFF# D47 GNT1# / GPIO51
USBP11N
USBP11P K32 USB20_P11
USB20_N11 19
USB20_P11 19 Int. Camera USB_OC#0 3 6
PCH_GPIO53 E42 G32 SLP_CHG_M3 2 7
W L_OFF# GNT2# / GPIO53 USBP12N USB_OC#6
32 W L_OFF# F46 GNT3# / GPIO55 USBP12P E32 1 8
USBP13N C32
1K_0402_5% 2 @ 1 R536 W L_OFF# A32 10K_0804_8P4R_5%
PCH_GPIO2 USBP13P
G42 PIRQE# / GPIO2 8/23 PIN swap for layout request
ODD_DA# G40 RP5
31 ODD_DA# PIRQF# / GPIO3
PCH_GPIO4 C42 C33 USBBIAS 1 2 USB_OC#1 4 5
3 PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R535 22.6_0402_1% USB_OC#2 3
D44 PIRQH# / GPIO5 3 6
Within 500 mils USB_OC#5 2 7
B33 USB_OC#7 1 8
PCI_PME# USBRBIAS
T32 PAD K10 PME# 10K_0804_8P4R_5%
PLT_RST# C6 A14 USB_OC#0 USB-LEFT
5,13,32,33,35,38,39 PLT_RST# PLTRST# OC0# / GPIO59 USB_OC#0 31,35,38
K20 USB_OC#1
OC1# / GPIO40 USB_OC#2
OC2# / GPIO41 B17
22_0402_5% 1 2 R525 CLK_EC_R H49 C16 SLP_CHG_M3
38 CLK_PCI_EC CLKOUT_PCI0 OC3# / GPIO42
22_0402_5% 1 2 R526 CLK_PCH H43 L16 SLP_CHG_M4
22 CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43
22_0402_5% 1 2 R527 CLK_SIO J48 A16 USB_OC#5
39 CLK_PCI_DDR CLKOUT_PCI2 OC5# / GPIO9
K42 D14 USB_OC#6
CLKOUT_PCI3 OC6# / GPIO10 USB_OC#7
H40 CLKOUT_PCI4 OC7# / GPIO14 C14

COUGARPOINT_FCBGA989~D HM65R1@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_PCI/USB/NAND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 25 of 53
A B C D E
 A B C D E

+3VS
+3VALW U2F
ODD_EN# 1 2
HDMI_HPD T7 C40 ODD_EN# R106 10K_0402_5%
13,30 HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 41
2 1 USB30_SMI# GATEA20 1 2
R390 1K_0402_5% PCH_GPIO1 A42 B41 PCH_W L_BT_LED R548 10K_0402_5%
EC_SMI# TACH1 / GPIO1 TACH5 / GPIO69 KB_RST#
1 2 1 2
R558 10K_0402_5% PCH_GPIO6 H36 C41 LOGO_LED R559 10K_0402_5%
PCH_GPIO12 TACH2 / GPIO6 TACH6 / GPIO70 LOGO_LED
1 2 1 2
R556 10K_0402_5% 38 EC_SCI# EC_SCI# E38 A40 MAXIC_SELECT PAD T75 R436 10K_0402_5%
PCH_GPIO28 TACH3 / GPIO7 TACH7 / GPIO71 PCH_W L_BT_LED
1 1 2 1 2 1
R557 10K_0402_5% 38 EC_SMI# EC_SMI# C10 R110 10K_0402_5%
PCH_GPIO57 GPIO8
1 2
R549 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
+3VS USB30_SMI# G2 P4 GATEA20
35 USB30_SMI# GPIO15 A20GATE GATEA20 38
AU16

CPU/MISC
BT_ON# PCH_GPIO16 PECI
1 2 U2 SATA4GP / GPIO16
R567 10K_0402_5% P5 KB_RST#
RCIN# KB_RST# 38
1 2 HDMI_HPD

GPIO
R539 @ 10K_0402_5% PCH_GPIO17 D40 AY11 H_PW RGOOD
TACH0 / GPIO17 PROCPWRGD H_PW RGOOD 5
1 2 PCH_GPIO1
R540 10K_0402_5% BT_DET# T5 AY10 PCH_THRMTRIP# 1 2
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# 5
1 2 BT_DET# R416 390_0402_5%
R542 10K_0402_5% E8 T14
OPTIMUS_EN# GPIO24 / MEM_LED INIT3_3V#
1 2
R554 10K_0402_5% PCH_GPIO27 E16
ODD_DETECT# GPIO27
1 2 This signal has weak internal
R545 200K_0402_5% PCH_GPIO28 P8
1 2 PCH_GPIO6 GPIO28
AH8
pull-up, can't be pulled low
R546 10K_0402_5% BT_ON# NC_1
32 BT_ON# K1 STP_PCI# / GPIO34
1 2 PCH_GPIO16 AK11 8/18 Remove PCH PECI by HW Review demand
R577 10K_0402_5% PCH_GPIO35 NC_2
T74 PAD K4 GPIO35
1 2 EC_SCI# AH10
R550 10K_0402_5% ODD_DETECT# NC_3
31 ODD_DETECT# V8 SATA2GP / GPIO36
1 2 CIR_EN# AK10
R551 100K_0402_5% PCH_GPIO37 NC_4
M5 SATA3GP / GPIO37
1 2 ISDBT_DET P37
2 R552 @ 10K_0402_5% OPTIMUS_EN# NC_5 2
N2 SLOAD / GPIO38
1 2 PCH_GPIO49
R553 10K_0402_5% CIR_EN# M3
PCH_GPIO17 SDATAOUT0 / GPIO39
1 2
R555 10K_0402_5% ISDBT_DET V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
PCH_GPIO49 V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
PCH_GPIO57 D6 BH3
@ USB30_SMI# GPIO57 VSS_NCTF_17
2 1
R437 10K_0402_5% BH47
PCH_GPIO37 VSS_NCTF_18
2 1
R547 10K_0402_5% A4 BJ4
PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
2 1
R402 10K_0402_5% A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
1 2 ISDBT_DET

NCTF
R328 47K_0402_5% A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

3 3
GPIO28
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
On-Die PLL Voltage Regulator
BE1 E1 H_THERMTRIP# C896 1 2 220P_0402_50V7K
* H: Enable VSS_NCTF_11 VSS_NCTF_29 @
L: Disable BE49 VSS_NCTF_12 VSS_NCTF_30 E49
H_PW RGOOD C897 1 2 220P_0402_50V7K
BF1 F1 @
R325 @ VSS_NCTF_13 VSS_NCTF_31
1 2 1K_0402_5% PCH_GPIO28
BF49 VSS_NCTF_14 VSS_NCTF_32 F49

9/1 Reserve C896, C897 for ESD requset

COUGARPOINT_FCBGA989~D HM65R1@

GPIO8
Integrated Clock Chip Enable (Removed)
H: Disable
L: Enable
*
R326 1 @ 2 1K_0402_5% EC_SMI#

4 4
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CPU/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 26 of 53
A B C D E
 A B C D E

+1.05VS_VCCP U2G POWER +3VS

PJ31 @ L12
PCH Power Rail Table
1300mA
2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC 0.1U_0402_10V7K 2 1 S0 Iccmax
2 1
AC23
VCCCORE[1] 1mA VCCADAC
1 1 BLM18PG181SN1D_0603 Voltage Rail Voltage
VCCCORE[2] Current (A)

CRT
1 JUMP_43X118 1 1 1 1 AD21 C512 C288 C286 1
C274 C269 C275 C289 VCCCORE[3] 0.01U_0402_25V7K 10U_0603_6.3V6M
AD23 VCCCORE[4] VSSADAC U47

VCC CORE
AF21 VCCCORE[5]
V_PROC_IO 1.05 0.001
10U_0603_6.3V6M 2 2
AF23 VCCCORE[6]
2 2 2 2
AG21 VCCCORE[7]
AG23 VCCCORE[8]
V5REF 5 0.001
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS R26 1 2 0_0402_5%
VCCCORE[9] VCCALVDS
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37 V5REF_SUS 5 0.001
AG29 VCCCORE[12]
AJ23

LVDS
VCCCORE[13]
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VCC3_3 3.3 0.266
AJ27 VCCCORE[15]
AJ29 AM38 +VCCTX_LVDS
VCCCORE[16] VCCTX_LVDS[2]

2
AJ31 VCCCORE[17]
VCCADAC 3.3 0.001
+1.05VS_PCH 60mA AP36 R27
VCCTX_LVDS[3]
0_0402_5%
VCCTX_LVDS[4] AP37 VCCADPLLA 1.05 0.08
AN19

1
VCCIO[28]
VCCADPLLB 1.05 0.08
T30 PAD BJ22 +3VS
VCCAPLLEXP
V33 VCCCORE 1.05 1.3

HVCMOS
VCC3_3[6]
AN16 VCCIO[15]
1
AN17 C272 VCCDMI 1.05 0.042
VCCIO[16] 0.1U_0402_10V7K
VCC3_3[7] V34
2 2 VCCIO 1.05 2.925 2
AN21 VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 R474
VCCIO[18] 0_0603_5% VCCASW 1.05 1.01
+VCCAFDI_VRM
AN27 VCCIO[19] 2925mA VCCVRM[3] AT16 1 2
+1.05VS_PCH AP21 +VCCP_VCCDMI R480 +1.05VS_VCCP VCCSPI 3.3 0.02
VCCIO[20] 0_0805_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VCCDSW 3.3 0.002

DMI
AP24 R477 +1.05VS_PCH
1 1 1 1 1

VCCIO
C277 C273 C279 C510 C511 VCCIO[22] 0_0805_5% C276
AP26 AB36 +1.05VS_VCC_DMI 1 2 1U_0402_6.3V6K VCCDFTERM 1.8 0.19
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 20mA VCCIO[1] 2
2 2 2 2 2 1
AT24 VCCIO[24] C270 VCCRTC 3.3 6 uA
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
AN33 VCCIO[25]
VCCDFTERM VCCSUS3_3 3.3 0.97
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCPNAND[1]
VCCSusHDA 3.3 / 1.5 0.01

NAND / SPI
BH29 VCC3_3[3] VCCPNAND[2] AG17
1 1
C290 190mA VCCVRM 1.5 0.16
0.1U_0402_10V7K AJ16 C278
VCCPNAND[3] 0.1U_0402_10V7K
2 +VCCAFDI_VRM 2 VCCCLKDMI 1.05 0.02
AP16 VCCVRM[2]
VCCPNAND[4] AJ17
3 3
T36 PAD BG6 VCCSSC 1.05 0.095
VCCFDIPLL +3VS

+1.05VS_PCH AP17 VCCIO[27]

VCCDIFFCLKN 1.05 0.055
FDI

V1
20mA VCCSPI

+VCCP_VCCDMI AU20 VCCDMI[2] 1 VCCALVDS 3.3 0.001

C281
COUGARPOINT_FCBGA989~D HM65R1@ 1U_0402_6.3V6K VCCTX_LVDS 1.8 0.06
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 27 of 53
A B C D E
 A B C D E

+3VALW U2J POWER +1.05VS_PCH

1 T42 PAD AD49 N26

C324 VCCACLK VCCIO[29]
1
0.1U_0402_10V7K P26
VCCIO[30] C328
T16
@ 2 VCCDSW3_3 3mA 1U_0402_6.3V6K
"@" Avoid leakage C305 VCCIO[31] P28
2
2 1 +PCH_VCCDSW V12 T27
+3VS DCPSUSBYP VCCIO[32]
0.1U_0402_10V7K T29
L18 +3VS_VCC_CLKF33 VCCIO[33] +3VALW
T38 VCC3_3[5]
1 1 2 +3VS_VCC_CLKF33 1
10UH_LB2012T100MR_20% 1 1 T23
T41 PAD VCCSUS3_3[7] +5VALW +3VALW
BH23 VCCAPLLDMI2 1
C301 C310 119mA T24 C321 +3VALW
10U_0603_6.3V6M 1U_0402_6.3V6K VCCSUS3_3[8] 0.1U_0402_10V7K
+1.05VS_PCH AL29 VCCIO[14]

2
2 2
V23

USB
VCCSUS3_3[9] 2 R512 D8
1
+VCCSUS AL24 V24 100_0402_5% RB751V40_SC76-2
DCPSUS[3] VCCSUS3_3[10] C332
1
C300 P24 0.1U_0402_10V7K

1
1U_0402_6.3V6K VCCSUS3_3[6] 2 +PCH_V5REF_SUS
@ AA19 1
+1.05VS_PCH 2 VCCASW[1]
VCCIO[34] T26 +1.05VS_PCH
AA21 1010mA C326
VCCASW[2] 0.1U_0603_25V7K
+PCH_V5REF_SUS 2
AA24 VCCASW[3] 1mA V5REF_SUS M26

Clock and Miscellaneous

1 1 AA26 @
C311 C312 VCCASW[4] +VCCA_USBSUS C335 1
DCPSUS[4] AN23 2 1U_0402_6.3V6K
AA27 VCCASW[5]
22U_0805_6.3V6M AN24 +3VALW
2 2 VCCSUS3_3[1]
AA29 VCCASW[6]
+1.05VS_PCH 22U_0805_6.3V6M
+5VS +3VS
AA31 VCCASW[7]
L13
1 2 +1.05VS_VCCADPLLA 1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
BLM18PG181SN1D_0603 +3VALW
1 1 1
L14 C323 C294 C308 AC27 R490 D7
+1.05VS_VCCADPLLB VCCASW[9] 100_0402_5%
1 2 VCCSUS3_3[2] N20 RB751V40_SC76-2

PCI/GPIO/LPC
2 BLM18PG181SN1D_0603 1U_0402_6.3V6K 1U_0402_6.3V6K AC29 1 2
2 2 2 VCCASW[10]
N22

1
VCCSUS3_3[3] C293 +PCH_V5REF_RUN
1 1 1 1 AC31 VCCASW[11]
C287 C295 C291 C298 P20 1U_0402_6.3V6K 1
1U_0402_6.3V6K VCCSUS3_3[4] 2
AD29 VCCASW[12]
1U_0402_6.3V6K P22 C304
2 2 2 2 VCCSUS3_3[5] +3VS 1U_0603_10V6K
AD31 VCCASW[13]
10U_0603_6.3V6M 10U_0603_6.3V6M 2
W21 VCCASW[14] VCC3_3[1] AA16
+3VS 1
W23 W16 C313
+1.05VS_PCH VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
R522 W24 T34
+VCCDIFFCLK VCCASW[16] VCC3_3[4] 2
2 1
W26 VCCASW[17] 1 2
0_0603_5% 1 C306
C337 0.1U_0402_10V7K +3VS
W29 VCCASW[18]
1U_0402_6.3V6K
W31 VCCASW[19] VCC3_3[2] AJ2
2 +1.05VS_SATA3 +1.05VS_PCH
1
W33 R516
VCCASW[20] C297
VCCIO[5] AF13 2 1
0.1U_0402_10V7K
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +VCCRTCEXT 2 0_0805_5%
N16 DCPRTC 1
R485 1 AH13 C329
+1.05VS_VCCDIFFCLKN C334 VCCIO[12] 1U_0402_6.3V6K
2 1
1 0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3
0_0603_5% C320 VCCVRM[4] VCCIO[13] 2
1U_0402_6.3V6K 2
3 3
VCCIO[6] AF14
2 +1.05VS_VCCADPLLA BD47

SATA
VCCADPLLA 80mA PAD T43
VCCAPLLSATA AK1
+1.05VS_VCCADPLLB BF47 +VCCAFDI_VRM
+1.05VS_PCH VCCADPLLB 80mA
R521 @ AF11 +VCCAFDI_VRM
+1.05VM_VCCSUS +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH
2 1 AF17 VCCIO[7]
AF33 R491
0_0603_5% VCCIO[8] +1.05VS_VCC_SATA
1
C316 +1.05VS_VCCDIFFCLKN
AF34 VCCIO[9] 55mA VCCIO[2] AC16 2
0_0805_5%
1
AG34 VCCIO[11]
1U_0402_6.3V6K +1.05VS_PCH AC17
VCCIO[3] 1
C331
2 1U_0402_6.3V6K
AG33 VCCIO[10] VCCIO[4] AD17
1
95mA
C318 2
1U_0402_6.3V6K +VCCSST V16 +1.05VS_PCH
DCPSST
2 1
0.1U_0402_10V7K
+1.05VM_VCCSUS T17 T21 +VCCME_22 0_0402_5% 1 2 R509
+RTCVCC C299 DCPSUS[1] VCCASW[22]
V19 DCPSUS[2]
MISC

2
0.1U_0402_10V7K +RTCVCC +1.05VS_VCCP V21 +VCCME_23 0_0402_5% 1 2 R517
R511 VCCASW[23]
1mA
CPU

1 1 1 1 2 0.1U_0402_10V7K +V_CPU_IO BJ8

C327 C330 C336 V_PROC_IO +VCCME_21 0_0402_5% 1
VCCASW[21] T19 2 R520
0_0603_5% 1 1 1
1U_0402_6.3V6K 0.1U_0402_10V7K C322 C303 +3VALW
2 2 2 C325 1
RTC

4.7U_0603_6.3V6K 0.1U_0402_10V7K +RTCVCC A22 10mA P32 C307

HDA

4 2 2 2 VCCRTC VCCSUSHDA 4
0.1U_0402_16V4Z

COUGARPOINT_FCBGA989~D HM65R1@ 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 28 of 53
A B C D E
 A B C D E

U2I U2H
H5 VSS[0]
AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18 AA17 VSS[1] VSS[80] AK38
AY46 VSS[161] VSS[261] K26 AA2 VSS[2] VSS[81] AK4
AY8 VSS[162] VSS[262] K39 AA3 VSS[3] VSS[82] AK42
B11 VSS[163] VSS[263] K46 AA33 VSS[4] VSS[83] AK46
B15 VSS[164] VSS[264] K7 AA34 VSS[5] VSS[84] AK8
B19 VSS[165] VSS[265] L18 AB11 VSS[6] VSS[85] AL16
B23 VSS[166] VSS[266] L2 AB14 VSS[7] VSS[86] AL17
B27 VSS[167] VSS[267] L20 AB39 VSS[8] VSS[87] AL19
B31 VSS[168] VSS[268] L26 AB4 VSS[9] VSS[88] AL2
B35 VSS[169] VSS[269] L28 AB43 VSS[10] VSS[89] AL21
1 B39 VSS[170] VSS[270] L36 AB5 VSS[11] VSS[90] AL23 1
B7 VSS[171] VSS[271] L48 AB7 VSS[12] VSS[91] AL26
F45 VSS[172] VSS[272] M12 AC19 VSS[13] VSS[92] AL27
BB12 VSS[173] VSS[273] P16 AC2 VSS[14] VSS[93] AL31
BB16 VSS[174] VSS[274] M18 AC21 VSS[15] VSS[94] AL33
BB20 VSS[175] VSS[275] M22 AC24 VSS[16] VSS[95] AL34
BB22 VSS[176] VSS[276] M24 AC33 VSS[17] VSS[96] AL48
BB24 VSS[177] VSS[277] M30 AC34 VSS[18] VSS[97] AM11
BB28 VSS[178] VSS[278] M32 AC48 VSS[19] VSS[98] AM14
BB30 VSS[179] VSS[279] M34 AD10 VSS[20] VSS[99] AM36
BB38 VSS[180] VSS[280] M38 AD11 VSS[21] VSS[100] AM39
BB4 VSS[181] VSS[281] M4 AD12 VSS[22] VSS[101] AM43
BB46 VSS[182] VSS[282] M42 AD13 VSS[23] VSS[102] AM45
BC14 VSS[183] VSS[283] M46 AD19 VSS[24] VSS[103] AM46
BC18 VSS[184] VSS[284] M8 AD24 VSS[25] VSS[104] AM7
BC2 VSS[185] VSS[285] N18 AD26 VSS[26] VSS[105] AN2
BC22 VSS[186] VSS[286] P30 AD27 VSS[27] VSS[106] AN29
BC26 VSS[187] VSS[287] N47 AD33 VSS[28] VSS[107] AN3
BC32 VSS[188] VSS[288] P11 AD34 VSS[29] VSS[108] AN31
BC34 VSS[189] VSS[289] P18 AD36 VSS[30] VSS[109] AP12
BC36 VSS[190] VSS[290] T33 AD37 VSS[31] VSS[110] AP19
BC40 VSS[191] VSS[291] P40 AD38 VSS[32] VSS[111] AP28
BC42 VSS[192] VSS[292] P43 AD39 VSS[33] VSS[112] AP30
BC48 VSS[193] VSS[293] P47 AD4 VSS[34] VSS[113] AP32
BD46 VSS[194] VSS[294] P7 AD40 VSS[35] VSS[114] AP38
BD5 VSS[195] VSS[295] R2 AD42 VSS[36] VSS[115] AP4
BE22 VSS[196] VSS[296] R48 AD43 VSS[37] VSS[116] AP42
BE26 VSS[197] VSS[297] T12 AD45 VSS[38] VSS[117] AP46
BE40 VSS[198] VSS[298] T31 AD46 VSS[39] VSS[118] AP8
2 BF10 T37 AD8 AR2 2
VSS[199] VSS[299] VSS[40] VSS[119]
BF12 VSS[200] VSS[300] T4 AE2 VSS[41] VSS[120] AR48
BF16 VSS[201] VSS[301] W34 AE3 VSS[42] VSS[121] AT11
BF20 VSS[202] VSS[302] T46 AF10 VSS[43] VSS[122] AT13
BF22 VSS[203] VSS[303] T47 AF12 VSS[44] VSS[123] AT18
BF24 VSS[204] VSS[304] T8 AD14 VSS[45] VSS[124] AT22
BF26 VSS[205] VSS[305] V11 AD16 VSS[46] VSS[125] AT26
BF28 VSS[206] VSS[306] V17 AF16 VSS[47] VSS[126] AT28
BD3 VSS[207] VSS[307] V26 AF19 VSS[48] VSS[127] AT30
BF30 VSS[208] VSS[308] V27 AF24 VSS[49] VSS[128] AT32
BF38 VSS[209] VSS[309] V29 AF26 VSS[50] VSS[129] AT34
BF40 VSS[210] VSS[310] V31 AF27 VSS[51] VSS[130] AT39
BF8 VSS[211] VSS[311] V36 AF29 VSS[52] VSS[131] AT42
BG17 VSS[212] VSS[312] V39 AF31 VSS[53] VSS[132] AT46
BG21 VSS[213] VSS[313] V43 AF38 VSS[54] VSS[133] AT7
BG33 VSS[214] VSS[314] V7 AF4 VSS[55] VSS[134] AU24
BG44 VSS[215] VSS[315] W17 AF42 VSS[56] VSS[135] AU30
BG8 VSS[216] VSS[316] W19 AF46 VSS[57] VSS[136] AV16
BH11 VSS[217] VSS[317] W2 AF5 VSS[58] VSS[137] AV20
BH15 VSS[218] VSS[318] W27 AF7 VSS[59] VSS[138] AV24
BH17 VSS[219] VSS[319] W48 AF8 VSS[60] VSS[139] AV30
BH19 VSS[220] VSS[320] Y12 AG19 VSS[61] VSS[140] AV38
H10 VSS[221] VSS[321] Y38 AG2 VSS[62] VSS[141] AV4
BH27 VSS[222] VSS[322] Y4 AG31 VSS[63] VSS[142] AV43
BH31 VSS[223] VSS[323] Y42 AG48 VSS[64] VSS[143] AV8
BH33 VSS[224] VSS[324] Y46 AH11 VSS[65] VSS[144] AW14
BH35 VSS[225] VSS[325] Y8 AH3 VSS[66] VSS[145] AW18
BH39 VSS[226] VSS[328] BG29 AH36 VSS[67] VSS[146] AW2
BH43 VSS[227] VSS[329] N24 AH39 VSS[68] VSS[147] AW22
3 3
BH7 VSS[228] VSS[330] AJ3 AH40 VSS[69] VSS[148] AW26
D3 VSS[229] VSS[331] AD47 AH42 VSS[70] VSS[149] AW28
D12 VSS[230] VSS[333] B43 AH46 VSS[71] VSS[150] AW32
D16 VSS[231] VSS[334] BE10 AH7 VSS[72] VSS[151] AW34
D18 VSS[232] VSS[335] BG41 AJ19 VSS[73] VSS[152] AW36
D22 VSS[233] VSS[337] G14 AJ21 VSS[74] VSS[153] AW40
D24 VSS[234] VSS[338] H16 AJ24 VSS[75] VSS[154] AW48
D26 VSS[235] VSS[340] T36 AJ33 VSS[76] VSS[155] AV11
D30 VSS[236] VSS[342] BG22 AJ34 VSS[77] VSS[156] AY12
D32 VSS[237] VSS[343] BG24 AK12 VSS[78] VSS[157] AY22
D34 VSS[238] VSS[344] C22 AK3 VSS[79] VSS[158] AY28
D38 VSS[239] VSS[345] AP13
D42 M14 COUGARPOINT_FCBGA989~D HM65R1@
VSS[240] VSS[346]
D8 VSS[241] VSS[347] AP3
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
4 H32 VSS[256] 4
H34 VSS[257]
F3 VSS[258]

COUGARPOINT_FCBGA989~D HM65R1@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 29 of 53
A B C D E
 5 4 3 2 1

D D

+3VS +HDMI_5V_OUT

+5VS HDMI@
R145

2
HDMI_HPD_U 1 2 HDMI_HPD_C
R452 2 1K_0402_5%
0_0402_5% C264 2

2
0.1U_0402_16V4Z R186 C265
For DISCRETE HDMI@

1
HDMI@ U9 100K_0402_5% 0.1U_0402_16V4Z

1
C 1 C
HDMI@ HDMI@

OE#
1

1
HDMI_HPD_R 1
2 A Y 4
CV296 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ R184 R185
14 VGA_HDMI_CLK+

1
G
2.2K_0402_5% 2.2K_0402_5% 74AHCT1G125GW_SOT353-5
CV293 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC- HDMI@ HDMI@ HDMI@ HDMI@
14 VGA_HDMI_CLK-

3
2
14 VGA_HDMI_CLK 2 1

2
G
CV294 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ R391 0_0402_5%
14 VGA_HDMI_TX0+
CV297 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0- 3 1 HDMI_SCLK
14 VGA_HDMI_TX0-

2
G

D
CV299 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ Q18
14 VGA_HDMI_TX1+
HDMI@ BSH111_SOT23-3
CV298 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1- 14 VGA_HDMI_DATA 2 1 3 1 HDMI@ HDMI_SDATA @ HDMI@
14 VGA_HDMI_TX1-
R401 0_0402_5% +3VS 2 1 2 1 +3VS

D
CV295 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+ R570 R571
14 VGA_HDMI_TX2+
Q19 100K_0402_5% 2.2K_0402_5%
CV300 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2- BSH111_SOT23-3 @ D55
14 VGA_HDMI_TX2-
HDMI@ HDMI_HPD_R 1 2 HDMI_HPD 13,26
CH751H-40PT_SOD323-2
2 1
R403 0_0402_5%
HDMI@
VGA_DVI_TXC- 1 @ 2 HDMI_R_CK- HDMI_R_CK+ 1 HDMI@ 2
R157 0_0402_5% R195 499_0402_1%
L8 HDMI@ HDMI_R_CK- 1 HDMI@ 2
1 2 R197 499_0402_1% HDMI@
1 2 HDMI_R_D1- 1 HDMI@ 2 D53 F2
R198 499_0402_1% +5VS 2 1 +HDMI_5V_OUT_F 2 1 +HDMI_5V_OUT
4 3 HDMI_R_D1+ 1 HDMI@ 2 1.1A_6V_MINISMDC110F-21
4 3 R202 499_0402_1% PMEG2010AEH_SOD123 HDMI@ C259
OCE2012120YZF HDMI_R_D0+ 1 HDMI@ 2 HDMI@
VGA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ R201 499_0402_1% 0.1U_0402_16V4Z
R173 0_0402_5% HDMI_R_D0- 1 HDMI@ 2 2
B B
R203 499_0402_1%
HDMI_R_D2- 1 HDMI@ 2
VGA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+ R205 499_0402_1%
R175 0_0402_5% HDMI_R_D2+ 1 HDMI@ 2
L9 HDMI@ R206 499_0402_1%

1
D
1 2
1 2 Q24
+5VS 2
G 2N7002_SOT23-3
4 3 S HDMI@

3
4 3
OCE2012120YZF
VGA_DVI_TXD0- 1 @ 2 HDMI_R_D0-
R180 0_0402_5%
HDMI Connector
JHDMI @
VGA_DVI_TXD1- 1 @ 2 HDMI_R_D1- HDMI_HPD_C 19
R182 0_0402_5% HP_DET
+HDMI_5V_OUT 18
L10 HDMI@ +5V
17 DDC/CEC_GND
1 HDMI_SDATA
1 2 2 HDMI_SCLK
16 SDA
15
SCL
14
Reserved
4 3 13
4 3 HDMI_R_CK- CEC
12 20
OCE2012120YZF CK- GND
11 21
VGA_DVI_TXD1+ @ HDMI_R_D1+ HDMI_R_CK+ CK_shield GND
1 2 10 22
R183 0_0402_5% HDMI_R_D0- CK+ GND
9 D0- GND 23
8 D0_shield
HDMI_R_D0+ 7
VGA_DVI_TXD2+ @ HDMI_R_D2+ HDMI_R_D1- D0+
1 2 6
R187 0_0402_5% D1-
5
L11 HDMI@ HDMI_R_D1+ D1_shield
4
HDMI_R_D2- D1+
1 1 2 2 3 D2-
A 2 A
HDMI_R_D2+ D2_shield
1
D2+
4 4 3 3
TAITW_PDVBR9-19FLBS4NN4N1
OCE2012120YZF
VGA_DVI_TXD2- 1 @ 2 HDMI_R_D2-
R188 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 30 of 53
5 4 3 2 1
 A B C D E

SATA HDD Conn SATA ODD Conn @

SW 2
1 3
+5VS
Place closely JHDD SATA CONN. ODD_DA#_R
1.2A 2 4

1 1 1 1 JODD @
Close to JODD SMT1-05-A_4P

6
5
C357 C358 C359
C356 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
10U_0603_6.3V6M GND SATA_PTX_C_DRX_P2 C378 1
A+ 2 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 21
2 2 2 2 SATA_PTX_C_DRX_N2 C377 1
A- 3 2 0.01U_0402_25V7K SATA_PTX_DRX_N2 21
GND 4
1 5 SATA_PRX_DTX_N2 C376 1 2 0.01U_0402_25V7K 1
B- SATA_PRX_C_DTX_N2 21
6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P2 21
GND 7

R561 0_0402_5%
8 ODD_DETECT#_R 1 2
DP ODD_DETECT# 26 +5VS_ODD
9 +5VS_ODD ZODD@ Place components closely ODD CONN.
+5V
+5V 10 1.1A
11 ODD_DA#_R 1 2
MD ODD_DA# 25
15 12 R562 0_0402_5% 1 1 1 1 1
GND GND C354
14 GND GND 13 ZODD@ 1
C352 C353 @ C355 C360
C363 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 0.1U_0402_16V4Z
SANTA_206401-1_RV 0.1U_0402_16V4Z 2 2 2 2 2
2 ZODD@
0.1U_0402_16V4Z
JHDD
Close to JHDD
GND 1
2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K
A+ SATA_PTX_DRX_P0 21
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N0 21
4
GND
B-
B+
5
6
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_C_DTX_N0 21
SATA_PRX_C_DTX_P0 21
USB Conn
GND 7

W=60mils
8
2
V33
V33 9
+3VS +5VALW 2.5A
U14
+USB_VCCA For EMI
2
V33 10
GND 11 1 GND VOUT 8 2 1
12 2 7 C361 1000P_0402_50V7K
GND VIN VOUT
GND 13 3 VIN VOUT 6
V5 14 +5VS 35,38 USB_EN# 4 EN FLG 5 USB_OC#0 25,35,38
V5 15 1
16 RT9715BGS_SO8
V5 C362
GND 17
18 4.7U_0805_10V4Z
Reserved 2 @
GND 19 +5VALW 1 2 USB_EN#
20 R161 100K_0402_5%
V12
24 GND V12 21
23 GND V12 22

@ SANTA_191201-1

W=60mils +USB_VCCA
+USB_VCCA C85

C87 2 1

+
3 3
2 1
220U_6.3V_M
+

220U_6.3V_M C60
2 1
C62
2 1 @ For EMI 0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 @ 1 C61
R843 0_0402_5% 2 0_0402_5%
1 2 1
JUSBB @ R842
W CM-2012-900T_0805 1000P_0402_50V7K
1 1 @ W=60mils
25 USB20_P0 2 2 1 1 2 2
USB20_P0_R 3
USB20_N0_R 3 W CM-2012-900T_0805 JUSB2 @
4 4
25 USB20_N0 3 3 4 4 5 5 G7 7 2 2 1 1 1 VCC GND 5
6 8 25 USB20_N1 USB20_N1_R 2 6
L87 6 G8 USB20_P1_R D- GND
25 USB20_P1 3 D+ GND 7
P-TW O_161021-06021_6P-T 3 4 4 8
3 4 GND GND

2
2 @ 1
R839 0_0402_5% L86 D62 @ ALLTOP C107L8-10405-L

2 1 PJDLC05_SOT23-3

R838 0_0402_5%
@

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD/ODD/USB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 31 of 53
A B C D E
 A B C D E

Half PCIe Mini Card-WLAN/ WiMax +3V_W LAN

40 mils
For SED WLAN&BT Combo module circuits
+3VALW 2 1 +3V_W LAN 0.1U_0402_16V4Z BT BT
2 1
1 1 1 on module on module

1
PJ27@ JUMP_43X79
2 2 CM1 CM2 CM3 C253 Enable Disable
+3VS 1 1 47P_0402_50V8J

2
PJ26@ JUMP_43X79 2 2 2 @
0.01U_0402_25V7K 4.7U_0805_10V4Z BT_CRTL H L
1
Short PJ27 for Wimax 1
Short PJ26 for WLAN BT_ON# L H
+1.5VS **If +3V_WLAN is +3VS, please
For SED
0.1U_0402_16V4Z remove D24
1 1 1 BT_CTRL

3
CM7 CM8 CM9 C254
47P_0402_50V8J

6
2 2 2 @ Q50B
0.01U_0402_25V7K 4.7U_0805_10V4Z 5 2N7002KDW H_SOT363-6
26 BT_ON#
Q50A
2 2N7002KDW H_SOT363-6

4
5,9,41,47 SUSP

1
+1.5VS +3V_W LAN
JW LAN @
R1443 1 2 BT_CTRL 1 R327 2 E51_RXD_R
0_0402_5% 1 2 1K_0402_5% +3VS
3 3 4 4
BT_CTRL 1 2BT_CTRL_R 5 6
5 6
22 CLKREQ_W LAN# 7 7 8 8 For isolate Intel Rainbow Peak and

2
G
9 9 10 10 Compal Debug Card.
22 CLK_W LAN# 11 11 12 12
13 14 W LAN_OFF# 1 3
2
22 CLK_W LAN 13 14 W L_OFF# 25 2
15 16

S
15 16
17 17 18 18 Add level shift circuit for WL_OFF# to
19 20 W LAN_OFF# 2N7002_SOT23-3 Q36 avoide leakage from WLAN to PCH
19 20 PLT_RST#
21 21 22 22 PLT_RST# 5,13,25,33,35,38,39
23 24 @
22 PCIE_PRX_W LANTX_N2 23 24
25 26 W LAN_OFF# 1 2 +3V_W LAN
22 PCIE_PRX_W LANTX_P2 25 26
27 28 R565 10K_0402_5%
27 28
29 29 30 30 PM_SMBCLK 11,12,22
22 PCIE_PTX_C_W LANRX_N2 31 31 32 32 PM_SMBDATA 11,12,22
22 PCIE_PTX_C_W LANRX_P2 33 33 34 34
35 35 36 36 USB20_N9 25
WLAN/ WiFi 37 37 38 38 USB20_P9 25 WiMax
+3V_W LAN 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
R16 47 48
47 48
38 E51_TXD 10_0402_5%2 49 49 50 50
1 2 E51_RXD_R 51 52
38 E51_RXD 51 52
0_0402_5%
R17 53 54
GND1 GND2
Debug card using 8/30 Add R1443 for WLAN Mini PCIE Card Pin5
FOX_AS0B226-S40N-7F

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-WLAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 32 of 53
A B C D E
 A B C D E

UL1
+3V_LAN CL3 to CL6 close to Pin 27,39,47,48
22 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 31 CL7 to CL8 close to Pin 12,42
HSOP LED3/EEDO
LED1/EESK 37
22 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 40 1 2
HSON LED0 CL3 0.1U_0402_16V4Z
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% 1 2
22 PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL
PCIE_PTX_C_LANRX_N1 18 32 RL1 2 1 10K_0402_5% CL4 0.1U_0402_16V4Z
22 PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA
1 2
CL5 0.1U_0402_16V4Z
CLKREQ_LAN# 2 1 16 1 LAN_MDI0+ 1 2
22 CLKREQ_LAN# CLKREQB MDIP0
RL19 0_0402_5% 2 LAN_MDI0- CL6 0.1U_0402_16V4Z
PLT_RST# MDIN0 LAN_MDI1+ +LAN_VDD10
1 5,13,25,32,35,38,39 PLT_RST# 25 PERSTB MDIP1 4 1 2 1
5 LAN_MDI1- 8111E@ CL7 0.1U_0402_16V4Z
+3V_LAN CLK_LAN MDIN1 LAN_MDI2+ LL1 8111E@
22 CLK_LAN 19 REFCLK_P NC/MDIP2 7 1 2
CLK_LAN# 20 8 LAN_MDI2- +LAN_REGOUT 1 2 8111E@ CL8 0.1U_0402_16V4Z
22 CLK_LAN# REFCLK_N NC/MDIN2
10 LAN_MDI3+ 2.2UH +-5% NLC252018T-2R2J-N
RL24 2 @ NC/MDIP3
1 10K_0402_5% CLKREQ_LAN#
NC/MDIN3 11 LAN_MDI3- 1 1
LAN_X1 43 Layout Note: LL1 must be
RL25 2 @ CKXTAL1 within 200mil to Pin36, CL9
1 10K_0402_5% EC_SW I# CL13
LAN_X2 44 13 CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
CKXTAL2 DVDD10 +LAN_VDD10
29 200mil to LL1 8111E@ 2 2 8111E@
DVDD10 CL19, CL20,CL21 close to
RTL8105E RTL8111E DVDD10 41
EC_SW I# 28 pin 13,29,45, respectively
23,35 EC_SW I# LANWAKEB
Pin14 NC NC LL1 CL13 CL9 CL22 close to pin 3, respectively
+3VS ISOLATE# 26 27 2.2UH +-5% NLC252018T-2R2J-N 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +LAN_VDD10 CL23,CL24,CL25 close to
ISOLATEB DVDD33 +3V_LAN
Pin15 NC 10K ohm PD 39 8105ESW R@ 8105ESW R@ 8105ESW R@ pin 6,9,41, respectively
DVDD33
Pin38 1K ohm Pull-high 14 NC/SMBCLK AVDD33 12 +3V_LAN
1

RL21 2 8111E@ 1 10K_0402_5% 15 42 1 2

RL22 1 NC/SMBDATA AVDD33 +LAN_VDD10 +LAN_EVDD10
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 CL19 0.1U_0402_16V4Z
1K_0402_5% 48 1 2
RL6 AVDD33 CL20 0.1U_0402_16V4Z
1 2
@ ENSW REG 33 LL2 0_0603_5% 1 2
2

ENSWREG CL21 0.1U_0402_16V4Z

EVDD10 21 +LAN_EVDD10 1 1
ISOLATE# 1 2 +LAN_VDDREG 34 1 2
W OL_EN 38,41 VDDREG CL17
RL433 0_0402_5% 35 3 +LAN_VDD10 CL18 8111E@ CL22 0.1U_0402_16V4Z
VDDREG AVDD10 1U_0402_6.3V6K 0.1U_0402_16V4Z
AVDD10 6 1 2
2 2 8111E@ CL23 0.1U_0402_16V4Z
AVDD10 9
1 2 46 RSET AVDD10 45 1 2
RL7 Sx Enable Sx Disable S0 RL5 2.49K_0402_1% 8111E@ CL24 0.1U_0402_16V4Z
2 15K_0402_5% Wake up Wake up 24 36 +LAN_REGOUT Close to Pin 21 1 2 2
GND REGOUT 8111E@ CL25 0.1U_0402_16V4Z
49 PGND 60 mils
WOL_EN LOW HIGH HIGH
RTL8111E-GR_QFN48_6X6 +3V_LAN +LAN_VDDREG
8111E@
1 2 +3V_LAN
8111E@ LL3 0_0603_5% 1 1

1
For P/N and footprint YL1 CL28 CL29
+3V_LAN
LAN_X1 1 2 LAN_X2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z RL4
Please place them to ISPD page 8111E@ 2 2 8111E@ 0_0402_5%
1
UL1 UL1 1 1 25MHZ_20PF_7A25000012 1 8111E@
CL683 + CL684 CL26 CL27

2
220U_6.3V_M_R16 10U_0805_10V6K 27P_0402_50V8J 27P_0402_50V8J ENSW REG
@ LL3 CL28 CL29

1
2 2 2 2 0_0603_5% 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
8105ESW R@ 8105ESW R@ 8105ESW R@ RL23
8105E-VL 10/100M 8105E-VL 10/100M 0_0402_5%
8105ELDO@ 8105ESW R@ 8105ELDO@
FOR EMI ISN TEST DEMAND.

2
UL3 RL4
8/30 Add UL3 at DVT LAN Conn. 0_0402_5%
8105ESW R@
JLAN

UL3 8105ELDO@ RJ45_MIDI3- 8 RTL8105E-VC RTL8105E-VC

10/100M transformer PR4-
RTL8111E-VB
8105ESW R@ LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI3+ 7
3 LAN_MDI0- TD+ TX+ RJ45_MIDI0- PR4+ PWM Mode LDO Mode 3
2 TD- TX- 15
3 14 RJ45_MIDI1- 6 RL4 0 ohm NC
CT CT PR2-
4 NC NC 13 (Pull High)
5 12 RJ45_MIDI2- 5
NC NC PR3-
6 CT CT 11 NC 0 ohm
LAN_MDI1+ 7 10 RJ45_MIDI1+ RJ45_MIDI2+ 4 RL23 (Pull Down)
LAN_MDI1- RD+ RX+ RJ45_MIDI1- PR3+
8 RD- RX- 9

1
RJ45_MIDI1+ 3 PR2+ DL1

1
X'FORM_ LFE8456E RJ45_MIDI0- 2 AZC199-02SPR7G_SOT23-3
PR1-

3
RJ45_MIDI0+ 1
UL4 PR1+

3
CL39 1000P_0402_50V7K 9
SHLD1
1 TCT1 MCT1 24 2 1 1 8111E@ 2
LAN_MDI3- 2 23 8111E@ RL11 75_0402_1% RJ45_MIDI3- 10
TD1+ MX1+ SHLD2

3
LAN_MDI3+ 3 22 RJ45_MIDI3+
TD1- MX1- CL40 1000P_0402_50V7K @

3
4 TCT2 MCT2 21 2 1 1 8111E@ 2 SANTA_130451-D
LAN_MDI2- 5 20 8111E@ RL12 75_0402_1% RJ45_MIDI2- @ AZC199-02SPR7G_SOT23-3
TD2+ MX2+

1
LAN_MDI2+ 6 19 RJ45_MIDI2+ DL2
TD2- MX2- CL41 1000P_0402_50V7K 8/30 Reserve DL1 and DL2 for ESD request

1
7 TCT3 MCT3 18 2 1 1 2
LAN_MDI1- 8 17 RL13 75_0402_1% RJ45_MIDI1-
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+
9 TD3- MX3- 16
CL42 1000P_0402_50V7K RJ45_GND 1 2 LANGND
10 15 2 1 1 2 CL36 1000P_1808_3KV7K 1 1
LAN_MDI0- TCT4 MCT4 RL15 75_0402_1% RJ45_MIDI0- CL37 CL38
11 TD4+ MX4+ 14
4
LAN_MDI0+ 12 13 RJ45_MIDI0+ 4
TD4- MX4- 220P_0402_50V6K 4.7U_0603_6.3V6K
2 2
Place CL34, CL35 colse 1 1
to LAN chip @ SUPERW ORLD_SW G150401
CL35 CL34 8111E@
0.1U_0402_25V4K 0.1U_0402_25V4K
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-LAN-RTL8105E/8111E
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 33 of 53
A B C D E
 A B C D E

1 For EMI request 1

1 2 @ RC6 10_0402_5% @ CC10 10P_0402_50V8J

@ CC2 100P_0402_50V8J 48MCLK_CR 1 2 1 2

RC2
6.19K_0402_1% UC1
2 1 1 REFE
GPIO0 17 0620 --> remove CR_LED#
0_0402_5% 2 1 RC1 USB20_N10_R 2
25 USB20_N10 DM
0_0402_5% 2 1 RC3 USB20_P10_R 3 24 48MCLK_CR < 48MHz >
25 USB20_P10 DP CLK_IN 48MCLK_CR 22

+3VS 4 3V3_IN XD_D7 23

+VCC_3IN1 5 CARD_3V3
+V1_8 6 22
V18 SP14 SD_DATA2_MS_DATA5
1 SP13 21
CC7 1U_0402_6.3V6K 7 20 MS_DATA1_SD_DATA3 0620 --> remove CARD-RADER LED
XD_CD# SP12
SP11 19
SDW P_MSCLK 8 18 SDCMD
2 SP1 SP10
9 SP2 SP9 16
SD_DATA1 10 15 MS_DATA2_SDCLK
SP3 SP8

EPAD
SD_DATA0 11 14
SP4 SP7 SDCD#
12 SP5 SP6 13

RTS5137-GR_QFN24_4X4

25
2 2

0715 --> change P/N to RTS5137 (SA000043500)

< 2 in 1 Card Reader >

0624 --> change CARDREADER conn.

JREAD @
MS_DATA1_SD_DATA3
D3 1 SDCMD
CMD 2
VSS1 3
VDD 4 MS_DATA2_SDCLK
+VCC_3IN1
CLK 5
VSS2 6 1
CC6
1

7 SD_DATA0 CC5
D0 SD_DATA1 0.1U_0402_16V4Z 1U_0402_6.3V6K
D1 8
SD_DATA2_MS_DATA5 2 2
D2 9
10 SDW P_MSCLK
WP SDCD#
CD 11

3 3
GND1 12
GND2 13
GND3 14
GND4 15

TAITW _PSDAT3-09GLAS1N14N

For EMI request

@ RC4 10_0402_5% @ CC8 10P_0402_50V8J

MS_DATA2_SDCLK 1 2 1 2

@ RC5 10_0402_5% @ CC9 10P_0402_50V8J

SDW P_MSCLK 1 2 1 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-CardReader RTS5137
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 34 of 53
A B C D E
 5 4 3 2 1

USB30@
+1.5V to +1.05V Transfer +3V 1 RT1
4.7K_0402_5%
2 USB30_POK
Close to U102.D7 Close to U102.P13
+1.5V +3V +1.5V +1.05V +3VA +3VA

10U_0603_6.3V6M
UT2 USB30@ 1A
CT2
1 5 3
VIN VOUT
9 4
VIN VOUT 8P_0402_50V8D 8P_0402_50V8D
6
USB30@ USB30_POK VCNTL
7 2 2 USB30@ 1 CT6 CT9
2 POK FB RT2 1 1 1 @ 1 1 1 @

10U_0603_6.3V6M
8 1 10K_0402_1% 0.1U_0402_16V7K 0.1U_0402_16V7K
+3V EN GND CT4 CT7

CT3
1 U3RXDP1_R 1 @ 2 RT4 U3RXDP1_R_L U3TXDP1 1 @ 2 RT5 U3TXDP1_L
APL5930KAI-TRG_SO8 RT3 0_0402_5% 0_0402_5%
2 CT5 2 2 2 CT8 2 2 LT1 USB30@ WCM-2012-121T_0805
32.4K_0402_1%
Vout=0.8(1+10K/32.4K) USB30@ 0.01U_0402_25V7K 0.01U_0402_25V7K 4 3 4 3

2
USB30@ 2 USB30@ USB30@ USB30@ USB30@ 4 3 4 3
D 1.042 ~ 1.0469 ~ 1.0519V D
Spec: 0.9975 ~ 1.05 ~ 1.1025 1
1 2
2 1
1 2
2

WCM-2012-121T_0805 LT2 USB30@

U3RXDN1_R 1 2 RT6 U3RXDN1_R_L U3TXDN1 1 2 RT7 U3TXDN1_L
+3VALW to +3V Transfer +3VALW @ 0_0402_5% @ 0_0402_5%

+3VALW Follow Vendor recommend.

2

2 USB30@
RT37 USB30@ CT42 +3V +1.05V
USB30@ 100K_0402_5% CT41 0.1U_0402_16V4Z +3VA RT9 0_0402_5% USB30@
0.1U_0402_16V7K 1 2

3
1
S
USB30@
1

G
1 2 2 QT1 LT4
RT38 47K_0402_5% 2 AO3413_SOT23 U2D_DN1 1 2 USB20_DN1_L
CT43 D 1 2
1
1

D 0.01U_0402_25V7K USB30@
2 USB30@ U2D_DP1 4 3 USB20_DP1_L
38,48 SYSON 1 4 3
G
+3V
QT2 S 2N7002_SOT23-3 @ WCM-2012-900T_0805

D10

H11
3

E11
E12

K11
K12

P13
F13
F14

L10

L13
L14
G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
P3

E3
E4
USB30@ UT1

F3

L9

L5

L8
1 2
+3V & +1.05V has power sequence timing: RT10 0_0402_5% USB30@
0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms USB30@

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U3AVDO33

U2AVDD10
22 CLK_USB30 B2
PECLKP
22 CLK_USB30# B1
+3V +3VA USB30@ PECLKN
CT29 2
+3V:200mA U3TXDP2
B6
22 PCIE_PRX_C_USBTX_P6 1 0.1U_0402_16V7K PCIE_PRX_USBTX_P6 D2
CT30 2 PCIE_PRX_USBTX_N6 PETXP
22 PCIE_PRX_C_USBTX_N6 1 0.1U_0402_16V7K D1 +1.05V:800mA A6
USB30@ USB30@ PETXN U3TXDN2
N8
LT3 U2DM2
22 PCIE_PTX_C_USBRX_P6 F2
PERXP
1 2 22 PCIE_PTX_C_USBRX_N6 F1 P8
BLM18AG601SN1D_2P PERXN U2DP2
C B8 C
U3RXDP2
2
A8
CT25 USB30@ U3RXDN2

5,13,25,32,33,38,39 PLT_RST# H2
10U_0603_6.3V6M 1 RT12 10_0402_5% 2 USB30_WAKE# PERSTB OCI2#
23,33 EC_SWI# K1 G14 1 RT13 2 10K_0402_5% +3V
USB30@ PEWAKEB OCI2B OCL1#
22 CLKREQ_USB30# K2 H13
RT15 PECREQB OCI1B
1 USB30@ 2 10K_0402_5% +3V USB30@
RT16 @
@1 2 100_0402_1% J2
RT17 AUXDET
+3V 1 USB30@ 2 10K_0402_5% J1 H14 JUSB30
USB30_SMI_R PSEL PPON2 USB30PWRON U3TXDP1_L
H1 J14 9
USB30_SMI#_IC SMI PPON1 SSTX+
0_0402_5% 1 RT18 2 USB30_SMI#_R P4 +USB_VCCA 1
USB30@ SMIB U3TXDN1_L VBUS
8
+1.05V USB20_DP1_L SSTX-
UPD720200A: +3V
RT39 1 2 10K_0402_5% P5
PONRSTB
USB30@ 3
D+
SMIB Low active USB30@ B10 U3TX_C_DP1 CT32 1 2 0.1U_0402_16V7K U3TXDP1 7
1SS355TE-17_SOD323-2 U3TXDP1 USB20_DN1_L GND
2 10
SPI_CLK_USB U3TX_C_DN1 CT33 U3TXDN1 U3RXDP1_R_L D- GND
1 2 M2 A10 1 2 0.1U_0402_16V7K 6 11 W=80mils
1 2 DT3 SPISCK U3TXDN1 SSRX+ GND
1U_0603_10V6K

SPI_CS_USB# N2 N10 U2D_DN1 4 12

SPISCB U2DM1 GND GND
CT16

CT17

CT18

CT19

CT20

CT21

CT22

CT23

CT24

CT44

1 2 1 2 2 1 2 2 2 USB30@ 1 SPI_SI_USB N1 USB30@ U3RXDN1_R_L 5 13 USB_GND USB30@

USB30_SMI#_IC SPI_SO_USB SPISI U2D_DP1 SSRX- GND
For UPD720200: M1
SPISO U2DP1
P10

CT45
SMI high active B12 U3RXDP1_R SANTA_371394-3 2
U3RXDP1
0.1U_0402_16V7K

0.01U_0402_25V7K

0.1U_0402_16V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.1U_0402_16V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

USB30@ @ 0_0603_5% 0_0603_5%

1

2 1 2 1 1 2 1 1 1 D 2 U3RXDN1_R RT42
K13 A12
GND U3RXDN1
Q57 2 1 @ 2 USB30_SMI_R K14 RT41
GND 1

.1U_0402_16V7K
@ G RT21 0_0402_5% J13

2
GND
S 2N7002_SOT23-3
3

1 @ 2 USB30_SMI#_R
RT40 0_0402_5% P12 RT22 1 2 1.6K_0402_1% USB30@ USB30@
RREF
N12
USB30@ USB30@ USB30@ USB30@ USB30@ U2AVSS
C14 USB30@
USB30@ USB30@ USB30@ USB30@ GND
N11
U2PVSS
+3V D6
U3AVSS @
N14
CLK_48M_USB XT1 USB30PWRON RT11 1
M14 2USB_EN# USB_EN# 31,38
XT2 0_0402_5%

烉烉24MHz
1
CT10

CT11

CT12

CT13

CT14

CT15

B 2 2 2 2 1 2 B
RT26 P6
100_0402_5% CSEL CSEL=0 XTAL
0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.1U_0402_16V7K

0.01U_0402_25V7K

USB30@
1 1 1 1 2 1 USB30@ CSEL=1 48MHz Clock P14
2

YT1 USB30@ GND

A1 P11
2

GND GND
1 2 A2 P9
0_0402_5%

0_0402_5%

GND GND
A3 P7
24MHZ_12PF_X5H024000DC1H GND GND
A4 P2
GND GND +USB_VCCA
12P_0402_50V8J

12P_0402_50V8J

A5 P1
GND GND
2

1 1 A7 N13
RT281

RT291
2

GND GND
0_0402_5%
RT30

USB30@ USB30@ USB30@ @ A9 N9 DT2

GND GND
CT37

CT38

0_0402_5%

USB30@ USB30@ USB30@ A11 N7 U3TXDN1_L 1 8

@ GND GND U3TXDP1_L R- VCC
A13 N3 2 7
@ 2 2 RT31 GND GND U3RXDN1_R_L R+ GND USB20_DN1_L
A14 M13 3 6
1

USB30@ USB30@ GND GND U3RXDP1_R_L T- D- USB20_DP1_L

B3 M12 4 5
1

+3V GND GND T+ D+

B4 M11
GND GND LXES4XBAA6-027_MSOP8
B5 M10
GND GND @
B7 M9
GND GND
B9 M8
GND GND
B11 M7
22 48MCLK_USB30 GND GND
B13 M6
GND GND +3V
B14 M5
GND GND
C1 M4
Place as close as possibile to C2
GND
GND
GND
GND
M3
C3 L12
UU102.N14 and UU102.M14 C10
GND
GND
GND
GND
L11 10K_0402_5%
C11 L7 +3V 2 RT43 1
GND GND

5
L6 USB30@ QT3B
GND
9/2 Change CT25 from SE093106K80 (10uF_0805) to SE000005T80
USB30_SMI#_IC 4 3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

(10uF_0603) by sourcer demand USB30_SMI# 26

2
2N7002KDWH_SOT363-6 QT3A
USB30@
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

OCL1# 1 6 USB_OC#0 25,31,38

+3V 10K_0402_5% 2N7002KDWH_SOT363-6
+3V 2 RT44 1 USB30@
A USB30@ A
UPD720200AF1-DAP-A
2

RT32 RT33
47K_0402_5% 10K_0402_5% SPI_CLK_USB 1 RT34 2
USB30@ USB30@ 0_0402_5% 2010/09/17 Add Level shift to avoid +3V leakage from +3VALW_PCH
@ 2
1

UT4
35mA CT39 CT40
Close to UU37.6
SPI_CS_USB# 1 8 USB30@ 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K
SPI_SO_USB CS# VCC 1
2 7 1 RT35 210K_0402_5%
3
SO
WP#
HOLD#
SCLK
6 SPI_CLK_USB_R USB30@
SPI_SI_USB
@ Security Classification Compal Secret Data Compal Electronics, Inc.
4
GND SI
5 Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

MX25L5121EMC-20G SOP 8P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-USB3.0 UPD720200A
USB30@ SPI_CLK_USB_R 1 RT36 2 SPI_CLK_USB AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0_0402_5% Custom 1.0
USB30@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 35 of 53
5 4 3 2 1
 A B C D E

Codec 600 mA RA2

+PVDD1 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z +5VS
Beep sound
1 1 0_0603_5% 1 1
CA57 CA44
C56 CA43
2 2 2 2
+3VS 1 2 0.1U_0402_16V4Z +DVDD_IO 10U_0603_6.3V6M 10U_0603_6.3V6M
RA19 0_0603_5%
1 1 EC Beep RA7
CA1 1 2
38 EC_BEEP#
+1.5VS 1 @ 2 CA2 47K_0402_5%
1 RA20 0_0603_5% 10U_0603_6.3V6M +3VS_DVDD 1
2 2
place close to chip
PCI Beep RA8
CA13
RA1 0.1U_0402_16V4Z 35 mA 21 PCH_SPKR 1 2 1 2 MONO_IN
+3VS 2 1 47K_0402_5%
0_0603_1% 1 1 0.1U_0402_16V4Z
+AVDD
CA8 CA7 RA3
10U_0603_6.3V6M 68 mA 10U_0603_6.3V6M 0.1U_0402_16V4Z 1 2
2 2 +5VS
0_0603_5%

1
1

39

46

25

38
1 1 1 1

9
UA1 CA3 CA4 CA5 CA6 RA12 CA18
4.7K_0402_5% 100P_0402_50V8J

PVDD1

PVDD2

AVDD1

AVDD2
DVDD_IO
DVDD
2
place close to chip

2
2 2 2 2
10U_0603_6.3V6M 0.1U_0402_16V4Z

23 LINE1_L SPK_OUT_L+ 40 SPKL+ 37

24 LINE1_R SPK_OUT_L- 41 SPKL- 37
14 LINE2_L SPK_OUT_R+ 45 SPKR+ 37
4.7U_0805_10V4Z CA23 15 44
LINE2_R SPK_OUT_R- SPKR- 37
37 MIC1_R_L 2 1
Ext. Mic 21 32 RA4 75_0402_1%
MIC1_L HP_OUT_L HP_L 37
2 1 22 33 RA5 75_0402_1% place close to chip
37 MIC1_R_R MIC1_R HP_OUT_R HP_R 37
4.7U_0805_10V4Z CA29
AZ_BITCLK_HD
2
Int. Mic 16
17
MIC2_L @ 2
MIC2_R @
SYNC 10 AZ_SYNC_HD 21 1 2 1 2
+3VS R746 10_0402_5%
INT_MIC_DATA 2 6 CA80 22P_0402_50V8J
19 INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD 21
@

2
INT_MIC_CLK RA46 3 close to Audio Codec(UA1) for EMI AZ_SYNC_HD 1 2
19 INT_MIC_CLK GPIO1/DMIC_CLK
1 FBMA-10-100505-301T 5 AZ_SDOUT_HD 21 R235
SDATA_OUT 4.7K_0402_5% @ CA81 22P_0402_50V8J
CA83 EC_MUTE#
4 PD# 8 AZ_SDIN0_HD_R 2 1 @
38 EC_MUTE# SDATA_IN AZ_SDIN0_HD 21
27P_0402_50V8J @ RA6 33_0402_5% AZ_RST_HD# 1 2

1
2
EC_MUTE# 11 47 CA82 22P_0402_50V8J
21 AZ_RST_HD# RESET# EAPD

SPDIFO 48
1

1 2 MONO_IN 12
RA45 CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20

4.7K_0402_5% SENSE_A 13 SENSE A

29 place close to chip
2

MIC2_VREFO
18 SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_RCA28 10U_0603_6.3V6M
EC control EC_MUTE# behavior: 1 2 36 CBP LDO_CAP 28 1 2
CA15
High-state / low-state 2.2U_0603_6.3V6K 35 27 AC_VREF
CBN VREF +MIC1_VREFO_R +MIC1_VREFO_L
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1%
MIC1_VREFO_L JDREF
1 1
43 PVSS2 CPVEE 34 1 2
42 CA14 2.2U_0603_6.3V6K CA17 C16 1 1
3 CA47 1 PVSS1 10U_0603_6.3V6M 3
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 @ @
2 2 @ C37 CA36
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K
ALC259-GR_QFN48_7X7 2 2
CA49 1 2 0.1U_0603_50V7K place close to chip
CA50 1 2 0.1U_0603_50V7K
DGND AGND
1 2
RA18 0_0603_5%

RA18 CLOSE TO ALC259

Sense Pin Impedance Codec Signals Function

place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out SENSE_A
37 MIC_SENSE 2 1
RA10 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A 37 NBA_PLUG
RA21 39.2K_0402_1%
10K PORT-C (PIN 23, 24)

5.1K (PIN 48)

4 4

39.2K PORT-E (PIN 14, 15)

SENSE B 20K PORT-F (PIN 16, 17) Int. MIC

Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 20) Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD CODEC ALC259
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 36 of 53
A B C D E
 A B C D E

Speaker Connector Ext. Mic RA31 2 1 +MIC1_VREFO_L

1K_0402_5% RA32 2.2K_0402_5%
2 1 MIC1_L
36 MIC1_R_L
placement near Audio Codec UA1 2 1 MIC1_R
36 MIC1_R_R
1K_0402_5%
RA22 2 1 +MIC1_VREFO_R
RA33 2.2K_0402_5%
RA30
1 SPKR+ 2 1 SPK_R1 1
36 SPKR+
0_0603_5% 1
CA25
470P_0402_50V8J 1
2
1 CA27
@ 1U_0402_6.3V6K
CA26 2 @
RA34 470P_0402_50V8J
SPKR- 2 SPK_R2
36 SPKR- 2 1
0_0603_5%
@
RA35
SPKL+ 2 1 SPK_L1
36 SPKL+
0_0603_5% 1
CA19
470P_0402_50V8J 1
2
1 CA24
@ 1U_0402_6.3V6K
CA20 2 @
RA36 470P_0402_50V8J
SPKL- 2 SPK_L2
36 SPKL- 2 1
0_0603_5%
@

2 2

HeadPhone/LINE Out JACK

JLINE
5 5
@ DA4 PJDLC05_SOT23-3
3 36 NBA_PLUG 4 4 GND 10
1 GND 9
2 LA6 1 2 HP_R_L 3 8
36 HP_R 3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
JSPK LA7 1 2 HP_L_L 2
36 HP_L 2
SPK_L1 1 KC FBM-L11-160808-121LMT 0603 1
SPK_L2 1 1
2 2
SPK_R1 3 1 FOX_JA63331-B39S4-7F
SPK_R2 3 @
4 4 3
1 CA45 CA46 CA11 @
@ DA5 PJDLC05_SOT23-3 ACES_85204-0400N 2 100P_0402_50V8J 100P_0402_50V8J
@ 2
3
1 DA6 @ 0.1U_0402_16V4Z
2 PJDLC05_SOT23-3
For EMI

3 3

Ext.MIC/LINE IN JACK
JEXMIC
5 5

36 MIC_SENSE 4 4 GND 10
GND 9
MIC1_R LA8 1 2 MIC1_L_R 3 8
3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
MIC1_L LA9 1 2 MIC1_L_L 2 2
KC FBM-L11-160808-121LMT 0603 1 1
FOX_JA63331-B39S4-7F
3 1 @
1
2 CA41 CA42 CA21
100P_0402_50V8J 100P_0402_50V8J
DA7 @ 2
PJDLC05_SOT23-3 0.1U_0402_16V4Z

For EMI
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO AMP/MIC/SPK/VR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 37 of 53
A B C D E
 A B C D E

+3VL R737
+3VL_R 2 1 0_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z R763 0_0402_5% 2 1 H_PROCHOT# 5,43
49 VR_HOT#
1 1 1 1 2 2
C436

1
C437 C438 C439 C440 C441 +3VL C442 D
For EMI 0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 H_PROCHOT#_EC 2 Q41 C518
2 2 2 2 1 1 G 2N7002_SOT23-3 47P_0402_50V8J

2
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z

22
33
96

67
S

3
9
CLK_PCI_EC U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1
R377
1 10_0402_5% BATT_TEMPA 1 2 1
@ GATEA20 1 21 C445 100P_0402_50V8J
26 GATEA20 GATEA20/GPIO00 PWM0/GPIO0F
KB_RST# 2 23 EC_BEEP# ACIN_D 1 2
26 KB_RST# EC_BEEP# 36
2 SERIRQ KBRST#/GPIO01 BEEP#/PWM1/GPIO10 FANPW M C446 100P_0402_50V8J
1 21,39 SERIRQ 3 SERIRQ# PWM Output FANPWM0/GPIO12 26 FANPW M 5
C443 LPC_FRAME# 4 27 ACOFF
21,39 LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF 44
22P_0402_50V8J LPC_AD3 5
21,39 LPC_AD3 LPC_AD3/LAD3
@ LPC_AD2 7
2 21,39 LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA
21,39 LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMPA 43
LPC_AD0 10 64
21,39 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39 +3VS
LPC & MISC 65 ADP_I
ADP_I/AD2/GPI3A ADP_I 43,44
CLK_PCI_EC 12 66 ADP_V
25 CLK_PCI_EC CLK_PCI_EC/PCICLK AD3/GPI3B ADP_V 44
PLT_RST# 13 AD Input 75 R758 10K_0402_5%
5,13,25,32,33,35,39 PLT_RST# PCIRST#/GPIO05 AD4/GPI42
ECRST# 37 76 H_PROCHOT#_EC_R 2 1H_PROCHOT#_EC 1 2
+3VL R378 EC_SCI# EC_RST#/ECRST# AD5/GPI43 R744 930@ 0_0402_5% @
26 EC_SCI# 20 EC_SCI#/GPIO0E
47K_0402_5% 38
ECRST# CLKRUN#/GPIO1D
2 1 DAC_BRIG/DA0/GPO3C 68
70 EN_DFAN1 VGATE_R 2 1 VGATE
EN_DFAN1/DA1/GPO3D EN_DFAN1 5 VGATE 5,23,49
2 1 DA Output 71 IREF R742 930@ 0_0402_5%
KSI[0..7] IREF/DA2/GPO3E IREF 44
C444 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ VGATE_RR 2 1
39 KSI[0..7] KSI0/GPIO30 DA3/GPO3F CHGVADJ 44
KSI1 56 R743 9012@ 0_0402_5%
KSO[0..17] KSI2 KSI1/GPIO31
39 KSO[0..17] 57 KSI2/GPIO32
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_MUTE# 36
KSI4 59 84 USB_EN#
KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B USB_EN# 31,35
RP7 KSI5 60 85 LID_SW #_R 2 1 LID_SW #
KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C LID_SW # 39
+3VL 1 8 EC_SMB_CK1 KSI6 61 PS2 Interface 86 H_PROCHOT#_EC_R R749 930@ 0_0402_5%
EC_SMB_DA1 KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK LID_SW #_RR
2 7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 40 2 1
+3VS 3 6 EC_SMB_CK2 KSO0 39 88 TP_DATA R748 9012@ 0_0402_5%
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 40
4 5 EC_SMB_DA2 KSO1 40
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
2 2.2K_0804_8P4R_5% KSO3 42 97 VGATE_R PH1 voltage compare function +5VS 2
KSO4 KSO3/GPIO23 SDICS#/GPXIOA00 W OL_EN
43 KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 98 W OL_EN 33,41
KSO5 PW RME_CTRL#
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/SDIMOSI/GPXIOA02 99
LID_SW #_R
PW RME_CTRL# 21
TP_CLK
45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 2 1 PH1+ 43 1 2
KSO7 46 SPI Device I/F R764 @ 0_0402_5% R379 4.7K_0402_5%
@ KSO8 KSO7/GPIO27 TP_DATA
47 KSO8/GPIO28 1 2
1 2 PLT_RST# KSO9 48 119 EC_SI_SPI_SO R381 4.7K_0402_5%
KSO9/GPIO29 SPIDI/MISO EC_SI_SPI_SO 39
C819 1U_0402_6.3V6K KSO10 49 120 EC_SO_SPI_SI SYSON 1 2
KSO10/GPIO2A SPIDO/MOSI EC_SO_SPI_SI 39
1 2 PLT_RST# KSO11 50 SPI Flash ROM 126 SPI_CLK_R 2 R19 930@
1 R5 4.7K_0402_5%
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 39
R3 100K_0402_5% KSO12 51 128 SPI_CS# 33_0402_5%
KSO12/GPIO2C SPICS# SPI_CS# 39
1 2 SUSP# KSO13 52 C19
C820 180P_0402_50V8J KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E 1 2 930@
@ KSO15 54 73 PM_PW ROK_RR 33P_0402_50V8J
KSO16 KSO15/GPIO2F GPIO40 EC_PECI R461 1 930@ 2 43_0402_1% EC_ON_R EC_ON
81 KSO16/GPIO48 H_PECI/GPIO41 74 H_PECI 5 2 1 EC_ON 40
KSO17 82 GPIO 89 FSTCHG R750 930@ 0_0402_5%
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG 44
90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# 40
91 CAPS_LED# VGA_ENBKL_RR 2 1
CAPS_LED#/GPIO53 CAPS_LED# 39
Close to EC EC_SMB_CK1 77 92 BATT_CHG_LOW _LED# R753 9012@ 0_0402_5%
43 EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW _LED# 40
EC_SMB_DA1 78 93
43 EC_SMB_DA1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55
EC_SMB_CK2 79 95 SYSON VGA_ENBKL_R 2 1
13,22 EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON 35,48 VGA_ENBKL 13
EC_SMB_DA2 80 121 VR_ON R751 930@ 0_0402_5%
13,22 EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 49
127 ACIN_R
AC_IN/GPIO59 EC_ON
SM Bus 2 1
R752 9012@ 0_0402_5%
PM_SLP_S3# 6 100 PCH_RSMRST#
23 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# 23
SLP_S5# 14 101 EC_LID_OUT#
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 22
EC_SMI# 15 102 EC_ON_R R341 330K_0402_5%
26 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05
16 GPIO0A EC_SWI#/GPXIOA06 103 +3VL 1 2
VGATE_RR 17 104 PM_PW ROK_EC
3 USB_OC#0_RR GPIO0B ICH_PWROK/GPXIOA07 BKOFF# 3
18 GPIO0C GPIO BKOFF#/GPXIOA08 105 BKOFF# 19 D21
PCH_SUSPW RDN 19 GPO RF_OFF#/GPXIOA09 106 VGA_ENBKL_RR ACIN_R 2 1 ACIN_D 2 1
23 PCH_SUSPW RDN SUS_PWR_DN_ACK/GPIO0D ACIN 23,44
25 107 R755 930@ 0_0402_5%
FAN_SPEED1 INVT_PWM/PWM2/GPIO11 GPXIOA10 SA_PGOOD
5 FAN_SPEED1 28 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 108 SA_PGOOD 46 RB751V40_SC76-2
+3VALW 29 ACIN_RR 2 1
C818 @ E51_TXD FANFB1/GPIO15 R765 9012@ 0_0402_5%
32 E51_TXD 30 EC_TX/GPIO16
support 51ON#
2 1 E51_RXD 31 110 ACIN_RR
32 E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01
ON/OFFBTN#_R 32 112 VGA_ENBKL_R 2 1 VS
ON_OFF/GPIO18 ENBKL/GPXIOD02
5

U44 0.1U_0402_16V4Z PW R_LED# 34 114 ON/OFFBTN#_RR R762 @ 0_0402_5% R759

40 PW R_LED# SUSP_LED#/GPIO19 EAPD/GPXIOD03
1 NUM_LED# 36 GPI 115 LID_SW #_RR 0_0402_5%
P

23 PM_SLP_S5# IN1 39 NUM_LED# NUM_LED#/GPIO1A EC_THERM#/GPXIOD04

4 SLP_S5# 116 SUSP# USB_OC#0_RR 2 1 0_0402_5% S9012@
O SUSP#/GPXIOD05 SUSP# 41,47,48,50
2 117 PBTN_OUT# R759 9012@
23 PM_SLP_S4# IN2 PBTN_OUT#/GPXIOD06 PBTN_OUT# 5,23
G

@ 118 USB_OC#0_R
SN74AHC1G08DCKR_SC70-5 930@ EC_PME#/GPXIOD07 USB_OC#0_R USB_OC#0
122 2 1 USB_OC#0 25,31,35
3

XCLK1 +EC_V18R R756 930@ 0_0402_5%

23 CLK_EC 2 1 123 XCLK0 V18R 124
R766 0_0402_5% R757
AGND

2 1 43_0402_1% 2 1 H_PECI
GND
GND
GND
GND
GND

R739 930@ 0_0402_5% C448 S9012@ R757 9012@ 43_0402_1%

4.7U_0805_10V4Z
1

2 1 1 KB930QF-A1_LQFP128_14X14
11
24
35
94
113

69

R760 9012@ 0_0402_5% R20 C1 Only for PWWHA USB_OC#0_RR 2 S9012@ 1 EC_PECI
100K_0402_5% 20P_0402_50V8J R767 0_0402_5%
2 1 ACIN_R 930@ 930@ R767 close U19.74
R761 9012@ 0_0402_5% 2
2

PM_PW ROK_RR 2 1
R754 9012@ 0_0402_5%
SUSP# R423 2 1 10K_0402_5%
1 2 E51_TXD PM_PW ROK_EC 2 1
4 PM_PW ROK 5,234
R349 100K_0402_5% VR_ON R462 2 1 10K_0402_5% R745 930@ 0_0402_5%

2 1H_PROCHOT#_EC
R747 9012@ 0_0402_5%
U19 S9012@ U19 9012@

40 ON/OFFBTN#
ON/OFFBTN# 2 1 ON/OFFBTN#_R Security Classification Compal Secret Data Compal Electronics, Inc.
R740 930@ 0_0402_5% 2010/09/03 2012/12/31 Title
Issued Date Deciphered Date
2 1 ON/OFFBTN#_RR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC-EC-KB930
R741 9012@ 0_0402_5% EC KB9012 A1 EC KB9012 A1 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 38 of 53
A B C D E
 A B C D E

Place the PAD under DDR DIMM.

SPI Flash (256KB) Lid SW 1
@ R21
2
0_0402_5%
+3VALW LPC Debug Port
1 2 +3VS H7 @
+3VL +3VL
R22 0_0402_5%
+3V_LID 6 5

1
1 20mils
C451 930@ U22 930@ R383 1 2 7 4
21,38 SERIRQ PLT_RST# 5,13,25,32,33,35,38
8 4 47K_0402_5% R392 0_0402_5%
0.1U_0402_16V4Z VCC VSS
2
3 21,38 LPC_AD3 8 3 LPC_AD2 21,38

2
W U21
1 7 APX9132ATI-TRL_SOT23-3 1
HOLD
21,38 LPC_AD1 9 2 LPC_AD0 21,38
SPI_CS# 1 2 3

GND
38 SPI_CS# S VDD VOUT LID_SW # 38
SPI_CLK 6 10 1
38 SPI_CLK C 21,38 LPC_FRAME# CLK_PCI_DDR 25
1 1

1
EC_SO_SPI_SI 5 2 EC_SI_SPI_SO
38 EC_SO_SPI_SI D Q EC_SI_SPI_SO 38

2
C453 C452
W 25X10BVSNIG_SO8 0.1U_0402_16V4Z 10P_0402_50V8J DEBUG_PAD R393
2 2 22_0402_5%
@

1
2
SPI_CLK 1 R394 2 1 2
10_0402_5% C454 10P_0402_50V8J C457
@ @ 22P_0402_50V8J
1 @
For EMI
8/30 Change U22 From SA00003GK00 to SA00003GM10 due to EOL of SA00003GK00
For EMI
9/03 Change U22 change to SA00003FL10

KEYBOARD CONN.
Noticed: KB Connector Pin Definition
2
Reversed with KB Membrane Pin Definition 2

For EMI

KSI[0..7]
Close to JKB
KSI[0..7] 38
KSO16 1 2
KSO[0..17] C401 100P_0402_50V8J
KSO[0..17] 38
KSO17 1 2
C402 100P_0402_50V8J
KSO2 1 2
JKB C404 100P_0402_50V8J
JKB34 1 2 +3VS KSO1 1 2
34 KSO16 R372 300_0402_5% C405 100P_0402_50V8J
33 KSO0
32 1 2
KSO17 C406 100P_0402_50V8J
31 KSO4
30 1 2
C407 100P_0402_50V8J
29 KSO2 KSO3
28 1 2
KSO1 C408 100P_0402_50V8J
27 KSO0 KSO5
26 1 2
KSO4 C409 100P_0402_50V8J
25 KSO3 KSO14
24 1 2
3 KSO5 C410 100P_0402_50V8J 3
23 KSO14 KSO6
22 1 2
KSO6 C411 100P_0402_50V8J
21 KSO7 KSO7
20 1 2
KSO13 C412 100P_0402_50V8J
19 KSO8 KSO13
18 1 2
KSO9 C413 100P_0402_50V8J
17 KSO10 KSO8
16 1 2
KSO11 C415 100P_0402_50V8J
15 KSO12 KSO9
14 1 2
KSO15 C416 100P_0402_50V8J
13 KSI7 KSO10
12 1 2
KSI2 C417 100P_0402_50V8J
11 KSI3 KSO11
10 1 2
KSI4 C418 100P_0402_50V8J
9 KSI0 KSO12
8 1 2
KSI5 C419 100P_0402_50V8J
7 KSI6 KSO15
6 1 2
KSI1 C420 100P_0402_50V8J
5 JKB4 KSI7
4 2 1 +3VS 1 2
CAPS_LED# R376 300_0402_5% C421 100P_0402_50V8J
3 CAPS_LED# 38
KSI2 1 2
2 NUM_LED# C422 100P_0402_50V8J
1 NUM_LED# 38
KSI3 1 2
ACES_88170-3400 C423 100P_0402_50V8J
@ KSI4 1 2
C424 100P_0402_50V8J
KSI0 1 2
4
C425 100P_0402_50V8J 4
KSI5 1 2
C427 100P_0402_50V8J
KSI6 1 2
C429 100P_0402_50V8J
KSI1 1 2
C431 100P_0402_50V8J
CAPS_LED# 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
C433 100P_0402_50V8J 2010/09/03 2012/12/31 Title
Issued Date Deciphered Date
NUM_LED# 1 2
C435 100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPI ROM/LID/Debug/KB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 39 of 53
A B C D E
 A B C D E

+3VL
Power Button 51_ON# 42

TP Button/Conn.

2
For debug R395

1
D
100K_0402_5% 2 Q7
38 EC_ON G 2N7002_SOT23-3

2
ON/OFFBTN# S
ON/OFFBTN# 38 LEFT

3
TOP side R396 SW 1
1 10K_0402_5% SW _L 1 3
C458
0.1U_0402_25V6 2 4 JTOUCH @

1
1 @ 1 1
@ 2 SMT1-05_4P +5VS 1
38 TP_CLK 2

6
5
SW 3 2
38 TP_DATA 3 3
1 3 SW _L 4
SW _R 4
5 5 G7 7
BTM side 2 4 For EMI request 6 6 G8 8
RIGHT 2
SMT1-05-A_4P SW 4 1 P-TW O_161021-06021_6P-T
6
5

SW _R 1 3 3
PWR/B to MB Conn. D19 @
2 4
AZ5125-02S.R7G_SOT23-3
JPOW ER @ SMT1-05_4P

6
5
3

2
ON/OFFBTN# 0816->change JTOUCH connector
1 1
2 2 D20 @
3 3

3
AZ5125-02S.R7G_SOT23-3
4 4 D83 @
G1 5
G2 6 AZ5125-02S.R7G_SOT23-3

1
ACES_85201-0405N

1
For EMI request
For ESD

2 2
POWER/SUSPEND LED Screw Hole
Vf=1.9V~2.4V H5 H6 H8 H9 H10 H11 H12 H13
If=5mA H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @ @ @ @ @ @ @
D22

1
+5VALW 1 2 2 1 PW R_LED# 38
R398 510_0402_5% YG
HT-110UYG5_YELLOW GREEN H1 H26 H17 H14
3

H_2P7x3P2N H_2P7N
@ @
H_1P0N H_3P0

1
@ @

BATT CHARGE/FULL LED

CPU MINI CARD SB
Vf=1.8V~2.0V
If=5mA(max) H20 H21 H18 H19 H15 H16
H_4P2 H_4P2x4P7 H_3P3 H_3P3 H_5P0N H_5P0N
@ @ @ @ @ @
3 D25 3

1
2 1 2 BATT_CHG_LOW _LED# 38
+5VALW 1 A R399 510_0402_5%

3 1 2 H22 H23
BATT_FULL_LED# 38
YG R404 510_0402_5% H_4P2x4P7 H_4P7 H2 H3 H4
@ @ H_2P9x3P9 H_2P9x3P9 H_2P9
HT-210UD5-UYG5_AMBER-YEL GRN @ @ @

1
ZZZ PJP1 45@ U2 HM65R3@ UV1 N12MR3@ For Codec AGND
ISPD Dummy PCB Fedical Mark PAD
3G
FD1 FD2 FD3 FD4
DAZ_PCB LA-7201P PJP1 B3 FCBGA 989P PCH N12M-GE-S-B1 533P MDC
@ @ @ @

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR&TP CON/LED/ISPD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 40 of 53
A B C D E
 A B C D E

for EMI +3VALW

Only for PWWHA DIS unmount
+3VALW TO +3VS C18
1 +5VALW TO +5VS +1.5V to +1.5VS Q31

0.1U_0402_10V6K
@ Vgs=10V,Id=9A,Rds=18.5mohm
2 +5VALW +5VS +1.5V +1.5VS
+3VALW +3VS +3VS 4.7U_0805_10V4Z
Vgs=10V,Id=9A,Rds=18.5mohm 4.7U_0805_10V4Z +5VS Vgs=10V,Id=14.5A,Rds=6mohm FDS6676AS_SO8
1 1 1 1 @
1 1 Q30 OLS@ C462 Q31 W PS3@ C464
Q29 OLS@ C460 4.7U_0805_10V4Z C461 For EMI C463

470_0805_5%

470_0805_5%
8 D S 1 8 D S 1

2
C459 1U_0402_6.3V6K 1U_0402_6.3V6K

470_0805_5%
8 D S 1 7 D S 2 7 D S 2

2
1U_0402_6.3V6K 2 2 R407 2 2 R408
7 2 6 3 6 S 3

0.1U_0402_16V4Z

0.1U_0402_16V4Z
D S 2 2 R406 D S OLS@ D
1 6 3 5 4 2 2 5 G 4 1

4.7U_0805_10V4Z
D S OLS@ D G OLS@ C822 C821 D
5 D G 4
SI4800BDY_SO8 1 R410 2 +VSB SI4800BDY_SO8 1 R411 2 +VSB

3 1

3 1
SI4800BDY_SO8 1 R409 2 1 1 47K_0402_5% @ @ 1 1 220K_0402_5%

0.01U_0402_25V7K

4.7U_0805_10V4Z
+VSB

3 1

6
47K_0402_5% 1 1

0.1U_0402_25V6
1 1
4.7U_0805_10V4Z

0.022U_0402_25V7K

C470
C466 OLS@ C467 C468 R413 OLS@ C469 R414
C465 OLS@ R412 OLS@ 200K_0402_5% Q11A OLS@ Q11B 820K_0402_5% Q12A Q12B
330K_0402_5% Q10A Q10B 2 2 @ SUSP 2N7002KDW H_SOT363-6 2 2 SUSP 2N7002KDW H_SOT363-6
2 5 2 5
2 2 OLS@ 2 OLS@ SUSP 5

2
2N7002KDW H_SOT363-6 2N7002KDW H_SOT363-6
2

4
2N7002KDW H_SOT363-6 OLS@ 2N7002KDW H_SOT363-6
1

4
38,47,48,50 SUSP# Each 250pF on CAP_MOS1 (2) will make +5VS_ODD
+1.8VS +5VALW
+3VALW Slew Rate(uS/V) increase of 100uS/V
2

+5VS +3VS
For S3 CPU Power Saving

2
R470 U46 NLS@
NLS@ +3VALW

2
470_0805_5% R457
R425 R415 470_0805_5%
0_0402_5% 1 MOS1_D MOS1_S 10 ZODD@
100K_0402_5%
1

PS3@

1
0.1U_0402_16V4Z
2 9

3 1
0.75VR_EN# 47 ON_MOS1 CAP_MOS1
1

6
D Q190 1 C496 1 1
0.1U_0402_16V4Z
2 2 SUSP 0.01U_0402_25V7K 2
3 8 C236 C249
G PS3@ Q44B @ 5_VDD GND Q53A
S 2N7002_SOT23-3 46,47 VCCPPW RGD 1 2 0.75VR_EN 5 2N7002KDW H_SOT363-6 2 2@ 2 @ 2N7002KDW H_SOT363-6 2 ODD_EN#
3

R158 100K_0402_5% PS3@ ZODD@

4 ON_MOS2 CAP_MOS2 7
4

1
6

+5VALW
1
Q44A C500 5 MOS2_D MOS2_S 6
SUSP 2 0.01U_0402_25V7K 120P_0402_50V4Z
2N7002KDW H_SOT363-6 NLS@ 2
PS3@ GND 11
1 1
0.1U_0402_16V4Z
1

38,47,48,50 SUSP# 2 R419 1

0_0402_5%
1 SLG59M232VTR_TDFN14-10_3X2
C252 C255 +5VS TO +5VS_ODD
NLS@ 2 NLS@ 2 @ +5VS
@
C499
2 0.01U_0402_25V7K
+3VS +5VS

2
C471 Vgs=-4.5V,Id=3A,Rds<97mohm
R441 0.1U_0402_16V7K
10K_0402_5% ZODD@

2
ZODD@ 1

3
S
R440 Q45 PJ28
+3VALW TO +3V_LAN

2
1
G
4 3 1 2 2
+1.5V to +1.5V_MEM_GFX 26 ODD_EN#
AO3413_SOT23
JUMP_43X79
@ +5VS_ODD

1
47K_0402_5% 2 ZODD@ D

1
+3VALW +1.5V +1.5V_MEM_GFX Q53B ZODD@

1
3 2N7002KDW H_SOT363-6 C217 3
+3VALW Vgs=10V,Id=14.5A,Rds=6mohm ZODD@ 0.01U_0402_25V7K
1 ZODD@
1
1 1 1
1

2 Q43 C484 C481 C680

RL148 CL485 Vgs=-4.5V,Id=3A,Rds<97mohm 4.7U_0805_10V4Z C679

470_0805_5%
8 D S 1 1U_0402_6.3V6K

2
100K_0402_5% @ 4.7U_0805_10V4Z 2
7 D S 2
@ 0.1U_0402_16V7K 2 2 R429 @ 2
6 D S 3
2

1
5 4
2

D G
3

S
@ RL434 @ QL52 PJ33 1U_0402_6.3V6K
2

G
1 2 2 JUMP_43X79 FDS6676AS_SO8 1 R431 2 +VSB
33,38 W OL_EN

3 1
@ 1 1 220K_0402_5%
4.7U_0805_10V4Z

+3V_LAN 6
1

47K_0402_5% AO3413_SOT23
0.1U_0402_25V6

D
2
1

@ C480 C489 R430 +0.75VS +1.05VS_VCCP

1

CL484 820K_0402_5% Q13A Q13B +5VALW

2 2
0.01U_0402_25V7K 2 VGA_PW ROK# 5 2N7002KDW H_SOT363-6

2
1
2
2

2
1 2N7002KDW H_SOT363-6 R421 R468
1

4
CL686 R422 22_0805_5% 470_0805_5%
CL685 1U_0402_6.3V6K +5VALW 100K_0402_5%
4.7U_0805_10V4Z 1

1
@ 2 R146

1
1 2 SUSP
5,9,32,47 SUSP

1
100K_0402_5% D Q189 D Q60
1

1
D D SUSP 2N7002_SOT23-3
2 2
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. 2 Q188 2 Q6 G G
50 VGA_PW ROK 38,47,48,50 SUSP#
G 2N7002_SOT23-3 G 2N7002_SOT23-3 S 2N7002_SOT23-3 S

3
S S
3

3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 41 of 53
A B C D E
 A B C D

1 2
@ PR1
1K_1206_5%
@ PD1
VIN
PL1 2 1 N3 1 2
PF1 SMB3025500YA_2P VIN B+
DC_IN_S1 1 2 DC_IN_S2 1 2 RLS4148_LL34-2 @ PR2
@ PJP1
1K_1206_5%
1 10A_125V_451010MRL
+
1 2

1000P_0402_50V7K

1000P_0402_50V7K

100P_0402_50V8J
100P_0402_50V8J
+ 2
@ PR3

1
3 1K_1206_5%

PC4
PC1

PC2

PC3
1
- 1

1
4

2
- @ PR4 @
@ PR5
SINGA_2DW -0005-B03 100K_0402_1% 2.2M_0402_5% PR38
1 2 2 1 511K_0402_1%
VL

2
N1

@ PD2

8
RB715F_SOT323-3 @ PU2B
2 5

P
45 EN0 +
1 7 O
44 ACON 3 6 2 1
VIN

G
-

1
@
@ PR6 @
LM393DG_SO8 PR35

1
PD3 34K_0402_1% 255K_0402_1% PC14

1
@ PR36

44
1000P_0402_50V7K

6251VREF
RLS4148_LL34-2 @ PC13 PR7 150K_0402_1%

2
1000P_0402_50V7K 66.5K_0402_1%

2
@

2
PC16

1
1000P_0402_50V7K

2
1

1
@ @ PR39

1
PR8 D 47K_0402_1%
PR9 @
PQ4 68_1206_5% 68_1206_5% PQ1 2 2 1
SSM3K7002FU_SC70-3 G PACIN 44
TP0610K-T1-E3_SOT23-3
S

3
PD4
2 1 N1 3 1
BATT+ VS

1
2 2

RLS4148_LL34-2
1

N1
1

PR10 PC6

1
100K_0402_1% 0.22U_0603_25V7K PC5 2 +5VALW P

8
@ PU2A
2

0.1U_0603_25V7K
3
2

P
PR11 + PQ2 @
1 O
40 51_ON# 1 2 2 DTC115EUA_SC70-3

3
G
-
22K_0402_1%
LM393DG_SO8

4
@ PJ332
+3VALW P 2 2 1 1 +3VALW
@ PJ333 JUMP_43X118
2 1 @ PJ152
+3VLP 2 1 +3VL (7A,280mils ,Via NO.= 14)
2 1 1
JUMP_43X39 OCP=7.7A 2
JUMP_43X118
(100mA,40mils ,Via NO.= 2)
@ PJ352 @ PJ153
+5VALW P 2 2 1 1 +5VALW +1.5VP 2 2 1 1 +1.5V
JUMP_43X118 JUMP_43X118
3
(7A,280mils ,Via NO.= 14) (16A,640mils ,Via NO.= 32) 3

OCP=7.9A
@ PJ72
+VSBP 2 2 1 1 +VSB @ PJ182 @ PJ402
JUMP_43X39 +1.8VSP 2 1 +1.8VS 2 1
2 1 2 1
(120mA,40mils ,Via NO.= 1) JUMP_43X118 JUMP_43X118
(1.65A,70mils ,Via NO.= 4) @ PJ403
@ PJ76 OCP=4.2A 2 1
+1.05VS_VCCPP 2 1 +1.05VS_VCCP
+0.75VSP 2 2 1 1 +0.75VS JUMP_43X118
JUMP_43X79
@ PJ452
(1A,40mils ,Via NO.= 2)
+VCCSAP 2 2 1 1 +VCCSA

JUMP_43X118
(6A,240mils ,Via NO.= 12) (12A,480mils ,Via NO.=24)

@ PJ602
2 2 1 1
JUMP_43X118

@ PJ603 ACIN
+VGA_COREP 2 2 1 1 +VGA_CORE Precharge detector
JUMP_43X118 Min. typ. Max.
4 4

(30A,1200mils ,Via NO.=60)

H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/VIN DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 42 of 53
A B C D
 A B C D

1
VMB 1

PL2
PH1 under CPU botten side :
@ PJP2 PF2 SMB3025500YA_2P
1 BATT_S1 1 2 1 2
CPU thermal protection at 95 degree C
1 BATT+
2 2
3 15A_65V_451015MRL
Recovery at 56 degree C
3 BATT_P4
4 4
5 BATT_P5
5

1
10 6 EC_SMDA PC8
GND 6 PC7

1
11 7 EC_SMCA @ PC15
GND 7 PR14 .1U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_25V7K
12 8

2
GND 8 1K_0402_1%
13 GND 9 9

SUYIN_200045MR009G171ZR

2
PH1+ 38

PD6
VL
1

PJSOT24C_SOT23-3

1
PD5 2
PJSOT24C_SOT23-3 1 PR15
3

1
PR16 19.6K_0402_1%
6.49K_0402_1% PC9
2

2
2 1 0.1U_0603_25V7K

2
+3VL

2
ADP_I 38,44
PR18
1

8.66K_0402_1%

1
PR19 PU1

1
2
1 8 PR22 2

1
1K_0402_1% VCC TMSNS1 20K_0402_1%
PH1
2 7
2

GND RHYST1
2

100K_0402_1%_NCP15W F104F03RC

2
PR20 PR21 BATT_TEMPA 38 3 6

2
OT1 TMSNS2
100_0402_1% 100_0402_1%
45 VS_ON 4 OT2 RHYST2 5 1 2
1

1
G718TM1U_SOT23-8 PR28
EC_SMB_DA1 38 88.7K_0402_1% PR27
5,38 H_PROCHOT# 100K_0402_1%

1
EC_SMB_CK1 38

2
1
D PR29
PQ7 2 10K_0402_1%
SSM3K7002FU_SC70-3 G
S

2
@ PJ334 +3VS
2 2 1 1

JUMP_43X39

PQ5
TP0610K-T1-E3_SOT23-3 Adapter Throttle Watt Recovery Watt Throttle Point Recovery Point

B+ 3 1 65W_UMA 71.25W 62.4W 1.48V 1.308V

+VSBP
3 3
0.22U_0603_25V7K
100K_0402_1%

75W_DIS 85.5W 72W 1.78V 1.5V

1

PC10
1

1
PR23

PC11 @
VL @ 0.1U_0603_25V7K 75W_QCore 85.5W 72W 1.78V 1.5V
2

2
2

PR24
2

1 2
PR25 22K_0402_1%
100K_0402_1%
1

D
PR26
1 2 2 PQ6
23,45 POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1

@ PC12
.1U_0402_16V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 43 of 53
A B C D
 A B C D

PQ208

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
APM4315KC-TRG_SO8
1 8

1
PC207

PC208

PC209
2 7
3 6
PQ203 PR215
PQ204 CHG_B+ 5
B+

2
APM4315KC-TRG_SO8P2 P3
SI4483ADY-T1-GE3_SO8 0.02_1206_1%
PL210

4
VIN 8 1 1 8 1 4 1 2
7 2 2 7 1.2UH_1231AS-H-1R2N=P3_2.9A_30%
6 3 3 6 2 3 CSIN
5 5
CSIP

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
VIN

1
1 1

PC231

PC232

PC233
2
PC211 PR236
1 2

2
VIN
1

5600P_0402_25V7K

1
47K_0402_1%

2
0.1U_0603_25V7K

6251VDD
PR210 LDO 5.075V PR226 PD9
47K_0402_1% PR212 PR237

2
ACSETIN ACOFF

PC210
191K_0402_1% 1 2
200K_0402_1% 10K_0402_1%
2

2.2U_0603_6.3V6K
PD201 1SS355_SOD323-2

1 1
PQ210 RB751V-40_SOD323-2 ACSETIN

1000P_0402_25V8J
1
PC212
DTA144EUA_SC70-3 1 PR290 2

1 1
VIN
3

1
1.26V

1
PC217
200K_0402_1%

2
PR228 PD10
PR227 14.3K_0402_1% PQ215
2 2 1 2

2
PR216 10_1206_5% DTC115EUA_SC70-3

2
10K_0402_1% 1SS355_SOD323-2

2
38 FSTCHG 2 1 PU200
1

1
PC218 PC222

3
1 24 DCIN 2 1
1

VDD DCIN 0.1U_0402_25V6

1

2
0.1U_0603_25V7K
PR213 PR217
2 2 ACSET ACPRN 23 ACPRN
PQ211 150K_0402_1% 100K_0402_1%
DTC115EUA_SC70-3 PR229 20_0402_5%
2

2
6251_EN 3 22 1 2 CSON
6

D EN CSON

1
D
PC219
3

5
6
7
8
2 0.047U_0402_16V7K PACIN 2
G 4 21 1 2 CSOP PQ201 G

1
CELLS CSOP AO4466L_SO8 PQ216
PR230 20_0402_5% S

3
S PQ212A PC213 SSM3K7002FU_SC70-3
1

2
DMN66D0LDW -7_SOT363-6 1 2 5 20 PR2312 1 20_0402_5% 2

ICOMP CSIN

2
PC220 4
PQ212B PC214 PR218 6800P_0402_25V7K
0.1U_0603_25V7K
DMN66D0LDW -7_SOT363-6 1 2 1 2 6 19 1 2

1
VCOMP CSIP
3

D PL202
10K_0402_1% PR232 2_0402_5% PR235
5 0.01U_0402_25V7K PR219 10UH_MSCDRI-104A-100M-E_4.6A_20% BATT+

3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG
CHG1 4
38,43 ADP_I ICM PHASE
100_0402_1%

1
5
6
7
8
S PC215 2 3
4

PR211 1 2 6251VREF 8 17 DH_CHG PQ202

42 6251VREF VREF UGATE PR206
22K_0402_5% PR220 AO4466L_SO8 0.02_1206_1%
PACIN 154K_0402_1% .1U_0402_16V7K PC205 4.7_1206_5%

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
42 PACIN 1 2 PR205
38 IREF 2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 @

2
CHLIM BOOT

1
2.2_0603_1% 4

1
0.01U_0402_25V7K

0.1U_0603_25V7K

PC202

PC203

PC204
PR222 PD202
1

1
6251VREF
1 2 6251aclim 10 15 6251VDDP
42 ACON ACLIM VDDP
1

RB751V-40_SOD323-2 PC206
PC216

2
PR221 24K_0402_1%
1 2 6251VDD 680P_0603_50V7K

2
3
2
1
120K_0402_1% 11 14 DL_CHG PR233 4.7_0603_5%
2

VADJ LGATE
1

2
2

PC221
PQ213 PR223 12 13 4.7U_0603_6.3V6M

1
DTC115EUA_SC70-3 GND PGND
20K_0402_1%
ACOFF 2
38 ACOFF
2

ISL6251AHAZ-T_QSOP24
3

PR224
38 CHGVADJ 1 2
3
15.4K_0402_1% 3
2

PR225
31.6K_0402_1% 6251VDD

VIN
1

PR241

1
10K_0402_1%

1
PR240 1 2 ACIN 23,38
47K_0402_1% PR242
PR246
10K_0402_1%
309K_0402_1%
CC=0.25A~3A 2

2
PACIN PR247

2
IREF=1.016*Icharge 10K_0402_1%

1
1 2 ADP_V 38
IREF=0.254V~3.048V PQ214
DTC115EUA_SC70-3

1
VCHLIM need over 95mV

1
ACPRN 2 PR243 PR248 PC223
14.3K_0402_1% 47K_0402_1% .1U_0402_16V7K

2
CHGVADJ=(Vcell-4)*9.445

2
Vin Detector
3

Vcell CHGVADJ
4V 0V
High 18.089V
4.2V 1.882V
4
Low 17.44V 4

4.35V 3.2935V
1.26 / 14.3 * 205.3 = 18.089V
CP mode
Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A
Vaclim=1.08V(65W) PR222=75k PR223=20k PR215=0.02
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vaclim=0.736V(75W) PR222=24k PR223=20k PR215=0.02 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
PWWHA LA-7201P M/B 1.0

Date: Friday, March 04, 2011 Sheet 44 of 53

A B C D
 5 4 3 2 1

2VREF_8205

D D

1
PC363
1U_0603_10V6K

2
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2

PR363 PR365
RT8205_B+ 20K_0402_1% 19.1K_0402_1%
HCB2012KF-121T50_0805
1 2 1 2 RT8205_B+
PL331

ENTRIP1
ENTRIP2
B+ 1 2 +3VLP PR337 PR357
10U_1206_25V6M

10U_1206_25V6M

@ 150K_0402_1% 150K_0402_1%
1

1
1 2 1 2 PC366
PC360

PC368

PC367
10U_1206_25V6M
1U_0805_25V7
2

2
@

4.7U_0805_10V6K

1
8
7
6
5

5
6
7
8
PU330

1
PQ331 PQ351

TONSEL
ENTRIP2

VFB2

VFB1

ENTRIP1
VREF
PC361
C AO4466L_SO8 C
25 P PAD

2
4 4
7 VO2 VO1 24 POK 23,43

PC335 8 VREG3 PGOOD 23 PC355

PR335 PR355 AO4466L_SO8
1
2
3

2 0.1U_0603_25V7K

3
2
1
0.1U_0603_25V7K BST_3V 9 22 BST_5V 1 2 1
1 2 1 2 VBST2 VBST1
0_0603_5% 0_0603_5%
PL332 UG_3V 10 21 UG_5V PL352
DRVH2 DRVH1
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% 4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
LX_3V 11 20 LX_5V +5VALWP
+3VALWP 1 2 LL2 LL1 1 2
8
7
6
5

5
6
7
8
1

1
PQ332 LG_3V 12 19 LG_5V
DRVL2 DRVL1

SKIPSEL
PR336 PR356

VREG5

330U_6.3V_M
VCLK
4.7_1206_5% 4.7_1206_5%

GND
1 1

EN0

VIN
4 42 EN0 4
2

2
PC332 + +

PC352
PR360 RT8205LARGER_QFN24_4X4

13

14

15

16

17

18
330U_6.3V_M PQ352
1

1
PC336 499K_0402_1%
2 PC356 2
680P_0603_50V7K IRF8707TRPBF_SO8 1 2
B+
1
2
3

3
2
1
IRF8707TRPBF_SO8 680P_0603_50V7K
2

2
Ipeak=5A

1
100K_0402_5%
1
Imax=3.5A VL

PR361
PC362
F=305KHz

1
1U_0402_6.3V6K
PC364
2
B Total Capacitor 150uF 4.7U_0805_10V6K
B

2
ENTRIP1 ENTRIP2 RT8205_B+ Ipeak=5A

2
Imax=3.5A
F=245KHz
6

D D
2 5 Total Capacitor 150uF
PQ360A G G PQ360B

1
DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 PC365
S S
2VREF_8205
1

0.1U_0603_25V7K

2
PR370
VL 2 1
100K_0402_1%
1

43 VS_ON

PR371
VS 1 2 2
100K_0402_1%
0.01U_0402_16V7K
42.2K_0402_1%

PQ361
1

DTC115EUA_SC70-3
PR372

PC370

3
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 45 of 53
5 4 3 2 1
 5 4 3 2 1

HCB2012KF-121T50_0805
D D
PL451
VCCSAP_B+ 1 2
B+

0.1U_0402_25V6
4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0402_25V6
Ipeak=6A

0.1U_0402_25V6

0.1U_0402_25V6
1

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1

1
1

1
2200P_0402_50V7K

10U_1206_25V6M

PC469

PC471

PC475
PC472

PC473

PC474

PC476
PC467

1
Imax=4.2A

PC463

PC464

PC466

PC468
1U_0805_25V7

2
PC465

2
2

2
2
5
6
7
8
@ @ @ @ @ @ @ F=276K

2
@

1
PR462
2
Toatal Capacitor 660u
255K_0402_1%
4

PR460 PR455 PQ451

1 2 BST_VCCSAP 1 2 AO4466L_SO8
41,47 VCCPPWRGD

3
2
1
0_0402_5% 0_0603_5%
BST_VCCSAP-1
1

@ PC460 PL452

15

14
1
.1U_0402_16V7K PU450 PC455 1.8U_D104C-919AS-1R8N_9.5A_30%
1 2 1 2 +VCCSAP

BST
EN_SKIP

TP
2

DH_VCCSAP 0.1U_0603_25V7K
2 13

1
TON DH
PR461 VOUT 3 12 LX_VCCSAP PR456 1

5
6
7
8
100_0402_1% OUT LX
PR457 +5VALW 4.7_1206_5% + PC452
1 2 4 11 1 2 PQ452
+5VALW VCC ILIM
330U_6.3V_M
14.3K_0402_1%

2
FB 5 10 1 2
FB VDD 2
PR471

1
1 2 6 9 PC462 4 PC456
+3VS PGOOD DL
1

AGND

PGND
PC461 10K_0402_1% 4.7U_0805_10V6K
DL_VCCSAP 680P_0603_50V7K PR463
4.7U_0805_10V6K

2
0_0402_5%
2

C TPS5117_TQFN14_3P5X3P5 IRF8707TRPBF_SO8 C
7

3
2
1

2
2

38 SA_PGOOD
@ PR472
10K_0402_1%
PR464
10_0402_5%
1

2 1 VCCSA_SENSE 9

1
PR465
680_0402_1%

2
+3VS

1
PR466 PR467
5.1K_0402_1%

1
9.09K_0402_1%
2

2
PR468
10K_0402_1%
PR469

2
1
D 10K_0402_1%
2 1 2
G
S PR473

1
.1U_0402_16V7K
C 0_0402_5%

100K_0402_1%
PQ453

@ PR470
2 1 2 VCCSAP_VID1 9

PC470
SSM3K7002FU_SC70-3 B
E

3
PQ454

1
B B
MMST3904-7-F_SOT323-3

VID1 +VCCSAP

1 0.8V

0 0.9V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCCSAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 46 of 53
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
@ PJ75

1
JUMP_43X79

2 2
D D
PU75
1 VIN VCNTL 6 +3VALW
PC261
Ipeak=0.5A
2 GND NC 5

1
4.7U_0805_6.3V6K Imax=0.35A

1
3 7 PC264
PR282 PR280 VREF NC Total Capacitor 44uF

2
0_0402_5% 1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
1 2
5,9,32,41 SUSP 9

2
TP
G2992F1U_SO8

@ PR279

.1U_0402_16V7K
+0.75VSP

1
0_0402_5% D

SSM3K7002FU_SC70-3
PQ260

PC263
1K_0402_1%
1 2 2
41 0.75VR_EN#

1
G

2
S PR281 PC262

3
1
10U_0805_6.3V6M

2
PC260
.1U_0402_16V7K

2
For shortage changed

PL401
HCB4532KF-800T90_1812
C 1.05VS_B+ 1 2 C
B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
10U_1206_25V6M

PC414

PC415
PC413
PR414

5
255K_0402_1% PQ401

2
1 2

PC416
PR410 2 1 4
0_0402_5%
38,41,48,50 SUSP# 1 2 PR510
0_0603_5% AON6428L_DFN8-5
1

PC410 PR405 PC405 PL402

15

14

3
2
1
1

@ PU400 0_0603_5% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%

.1U_0402_16V7K BST_1.05VS_VCCP
1 2 1 2 2 1 +1.05VS_VCCPP
EN_SKIP

TP

BST
2

2 13 DH_1.05VS_VCCP
TON DH

1
5
3 12 LX_1.05VS_VCCP PR406
OUT LX
PR407 4.7_1206_5% 1
4 VCC ILIM 11 1 2 +5VALW + PC402

1 2

2
5 VFB=0.75V 10 11K_0402_1% 330U_6.3V_M

0_0402_5%
1 2

680P_0603_50V7K
FB VDD

PR420
4
PR411 PC412 2

PC406
6 PGOOD DL 9

AON6788_DFN8-5
AGND

PGND

100_0603_1% 4.7U_0805_10V6K

2
PQ402
1 2 DL_1.05VS_VCCP
+5VALW

1
3
2
1
B TPS5117_TQFN14_3P5X3P5 B
7

8
1

PC411
4.7U_0603_6.3V6K
Ipeak=12.5A
2

Imax=8.75A
PR415
1 2
F=305KHz
41,46 VCCPPW RGD +3VS Total Capacitor 990uF
10K_0402_1%
2

@ PR416
10K_0402_1%
1

PR412 PR421
4.02K_0402_1% 10_0402_5%
1 2 2 1 VCCIO_SENSE 8
1

PR413
10K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS_VCCP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 47 of 53
5 4 3 2 1
 A B C D

HCB2012KF-121T50_0805

PL151
1.5_B+ 1 2
1
B+ 1

10U_1206_25V6M

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC166

PC163
@ PC165

PC164
5
680P_0402_50V7K
PQ151

2
@
PR164 PR165
255K_0402_1% 1 2 4
1 2
PR160
1 2 0_0603_5% AON6428L_DFN8-5
35,38 SYSON PR155
BST_1.5V 1 2
0_0402_5%

3
2
1
0_0603_5%
1

15

14
PL152
PC160 @

1
PU150 PC155 1UH_FDUE1040D-1R0M-P3_21.3A_20%
.1U_0402_16V7K BST_1.5V-1 1 2 2 1

EN_SKIP

TP

BST
+1.5VP
2

2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
3 12 LX_1.5V
OUT LX

1
PR161 PR157

AON6788_DFN8-5
1 2 4 11 1 2 PR156 1
+5VALW VCC
VFB=0.75V
ILIM
11K_0402_1%
+5VALW 4.7_1206_5%

PQ152
100_0603_5% + PC152
5 FB VDD 10
330U_6.3V_M

2
1

PC161 6 9 DL_1.5V 4
PGOOD DL

AGND

PGND
2
4.7U_0603_6.3V6K

2
2

1
PC162 PC156
TPS5117_TQFN14_3P5X3P5 4.7U_0805_10V6K 680P_0603_50V7K

3
2
1
2
DIS : UMA : 2

2
Ipeak=18A Ipeak=12A
Imax=12.6A Imax=8.4A
-------------------------------------------------
F=294KHz
PR162
1 2 Total Capacitor1050(dis)uF,
10K_0402_1% 720(uma)uF
1

PR163
10.5K_0402_1%
2

Ipeak=1.65A
ILIM = 4A
F=1MHz
PU180
+3VALW +5VALW
3 SY8033BDBC_DFN10_3X3 PL182 +1.8VSP 3
4

@ PJ181 1UH_VMPI0703AR-1R0M-Z01_11A_20%
+5VALW 2 1 10 2 LX_1.8V 1 2
PG

2 1 PVIN LX

1
JUMP_43X39
68P_0402_50V8J
9 PVIN LX 3 PJ1810
1

@ JUMP_43X39
1

1
4.7_1206_5%

PC187

PC184 8 SVIN
PR186

22U_0805_6.3VAM PR183

1
FB=0.6Volt 20K_0402_1%

2
6

22U_0805_6.3VAM

1U_0603_10V6K
22U_0805_6.3VAM
2

FB
5

PC1810
2

EN
1

2
NC

NC
TP

PC183
PC182
2

2
FB_1.8V
11

2
PR181 @
680P_0603_50V7K

1
38,41,47,50 SUSP# 1 2 EN_1.8V
1

@
PC186

0_0402_5% PC1820
PR184
1

2
2

10K_0402_1%
1

@ PR182 PC185@ 4.7U_0805_25V6-K

2

499K_0402_1% 0.1U_0402_10V7K
2

PU1800
2

6 VCNTL
@ 5 VIN VOUT 3 +1.8VSP
PR1810 9 4
VIN VOUT

1
0_0402_5%

0.01U_0402_25V7K
1

PC1830
38,41,47,50 SUSP# 1 2 8 EN @
PR1820

22U_0805_6.3V6M
7 2

GND
POK FB

1
3K_0402_1% @

2
1

PC1840
@ PC1850

2
APL5930KAI-TRG_SO8

2
0.47U_0402_6.3V6K @
2

1
4 4

@
@
PR1830
2.4K_0402_1%

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 48 of 53
A B C D
 5 4 3 2 1

1000P_0402_50V7K
8.06K_0402_1%
1

PR530

PC530
1
@ PH501 470KB_0402_5%_ERTJ0EV474J
@ PR563 NTCG
2 1 2 1
@ @
3.83K_0402_1%

2
@PR564 27.4K_0402_1%
@PR564

2
1 2

@ PC556

1
330P_0402_50V7K

330P_0402_50V7K
@ PR531 1 2
@

PC557
499K_0402_1% PC531
VCC_AXG_SENSE

1
68P_0402_50V8J
2 1 2 1 2 1
2 @ 2 1 VSS_AXG_SENSE

2
D @PR532 @ PC532
@PC532 D
422_0402_1% 680P_0402_50V7K @ PC558

ISNG
2 1 2 1 2 1 1000P_0402_50V7K
@ 1 2
PC533 @ PR533 PR534
PR576 0_0402_5% +5VALW
150P_0402_50V8J 475K_0402_1% 2.55K_0402_1%
@ PR567

0.047U_0603_16V7K
@

2
24.9K_0402_1%
PR539

PC534
16.5K_0402_1%
1

1 +1.05VS_VCCPP Connect to +5V can disable GFX portion,

NTCG
ISNG
@ @
but PR575 need to be removed.

130_0402_1%

54.9_0402_1%
.1U_0402_16V7K
2

1
2

1
PC560
2

PR538
PR537
1

49

48

47

46

45

44

43

42

41

40

39

38

37
2

GND

COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

PROG2

BOOTG

UGG

PHG

LGG
8 VR_SVID_DAT
1 36 BOOT2
8 VR_SVID_ALRT# VWG BOOT2
2 35 UGATE2
8 VR_SVID_CLK IMONG UG2
3 34 PHASE2
PGOODG PH2
VR_SVID_DAT 4 33
SDA VSSP2
VR_SVID_ALRT# 5 32 LGATE2 PR562
ALERT# LG2 0_0603_5%
VR_SVID_CLK 6 31 VDDP+ 1 2
SCLK ISL95831CRZ-T_TQFN48_6X6 VDDP +5VALW CPU_B+ 1 2
PR540 B+

10U_1206_25V6M
10U_1206_25V6M
2.2U_0603_10V6K

4.7U_0805_25V6-K
38 VR_ON 1 2 7 30 PL501
VR_ON PWM3

PC574
PC565

PC567
HCB4532KF-800T90_1812

1
0_0402_5%
29.4K_0402_1%

0.033U_0603_16V7

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC554
8 29 LGATE1 PQ505
PR541 PGOOD LG1

1
1

1
C C

PC580

PC581

PC582
+3VS 1 2
1
PR542

PC561

1.91K_0402_1% 9 IMON VSSP1 28

1
@ @

2
2

2
5,23,38 VGATE 10 27 PHASE1 UGATE2 2 1 4
VR_HOT# PH1
2
2

2
11 26 UGATE1 PR508

ISEN3/ FB2
NTC UG1 0_0603_5% AON6428L_DFN8-5
12 25 BOOT1 PL503

PROG1
ISUMN

ISUMP
VW BOOT1
COMP

3
2
1
ISEN2

ISEN1

VSEN
0.36UH_PCMC104T-R36MN1R17_30A_20%

VDD
38 VR_HOT#

RTN

VIN
FB
43P_0402_50V8J

PHASE2 4 1
PU500
+CPU_CORE
13

14

15

16

17

18

19

20

21

22

23

24
1
PC537

PR544 PH502 470KB_0402_5%_ERTJ0EV474J PC515 3 2

1 2 1 2 0.22U_0603_25V7K
+1.05VS_VCCPP

680P_0603_50V7K 4.7_1206_5%
VDD+
BOOT2 2 1 2 1

AON6788_DFN8-5
2

3.83K_0402_1%

PR516
1 2 PR515
@PR543
@ PR543 0_0603_5% PR580 PR581
499_0402_1% 2 1 PR559 ISEN2 2 1 2 1 ISEN1

PQ508
1
PR545 1 2
CPU_B+

2
PR560 LGATE2 10K_0402_1% 10K_0402_1%
27.4K_0402_1% 0_0603_5% 4
1.69K_0402_1%
1000P_0402_50V7K
8.06K_0402_1%

For Turbo mode , PH502 must be

1

1
PC516
ISEN2

PR558 PR582
changed 470K (b value = 4700)

2
1
PC539

VSUM+
ISEN1

2 1 2 1
PR546

+5VALW

3
2
1
1U_0603_10V6K
ISEN3

2
1_0603_5% 3.65K_0402_1%
1
2

1
PC548

PC540
PR583
2

2 1 PC549 VSUM- 2 1
0.22U_0603_25V7K
2

22P_0402_50V8J 1_0402_5%
VSUM+

2.61K_0402_1%
1
0.22U_0402_10V6K

0.047U_0402_25V7K

PR557
PC541 2 1
0.22U_0402_10V6K
PC550

B B
@ PR547 10P_0402_50V8J PC542 VSUM- PC562 0.22U_0402_6.3V6K CPU_B+
PR548
PC551
PC559

1 2 2 1 2 1 2 1

11K_0402_1%
1 2
1

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
499K_0402_1% 2 1

100U_25V_M
PC569
100U_25V_M

100U_25V_M
499_0402_1%

PC583

PC584

PC585

PC568

PC566
470P_0402_50V7K
PC543 PR549 PR556 PQ503 1 1 1
2

@
330P_0402_50V7K

150P_0402_50V8J 316K_0402_1% PR551 PC544 0.22U_0402_6.3V6K PH503

1
10K_0402_1%_ERTJ0EG103FA + + +
2 1 2 1 2 1
3.32K_0402_1% PR554 @
2

@ PC555 @ PR550 1.47K_0402_1% UGATE1 2 1 4

2

2
100P_0402_50V8J 2K_0402_1% VSUM- 2 2 2
2 1
PR509
.1U_0402_16V7K
2 1 2 1
PC545 330P_0402_50V7K 0_0603_5% AON6428L_DFN8-5
1

1
PC553

Reserve for slow rate 2 1 @ PC552 @PR555

@ PR555 PL504
8 VCCSENSE

3
2
1
330P_0402_50V7K 100_0402_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
PC547

PC546 1000P_0402_50V7K 2 1 2 1 PHASE1 4 1

8 VSSSENSE +CPU_CORE
2

2 1

680P_0603_50V7K 4.7_1206_5%
PC525 3 2

AON6788_DFN8-5

PR526
0.22U_0603_25V7K PR591
BOOT1 2 1 2 1 ISEN1 2 1

PQ504
PR525
0_0603_5% 10K_0402_1%

2
LGATE1 4
PR592 PR590

1
PC526
VSUM+ 2 1 2 1 ISEN2
3.65K_0402_1% 10K_0402_1%

3
2
1

2
PR593
VSUM- 2 1
1_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE/GFX
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 49 of 53
5 4 3 2 1
 5 4 3 2 1

B+ 1 2 B+_VCORE

PL601
HCB4532KF-800T90_1812

10U_1206_25VAK

10U_1206_25VAK

4.7U_0805_25V6-K
1

1
PC620

PC621

PC622
D D

2
VCORE_VDD
Ipeak=20A

5
PR620 PQ601 Imax=14A
1.5K_0402_1%
PR621
PR607
F=300kHZ
3K_0402_1%
Output capacitor=660uF

2
1 2 DH_VCORE 1 2 4
41 VGA_PW ROK
0_0603_5%
PR605 PC605 AON6428L_DFN8-5
PU600 0_0603_5% 0.1U_0603_25V7K

3
2
1
PR624 1 10 BST_VCORE 1 2 1 2
120K_0402_1% PGOOD VBST PL602
1 2 2 TRIP DRVH 9
PR622 20K_0402_1% 0.56U_PCMC104T-R56MN_25A_20%
1 2 3 8 LX_VCORE 1 2 +VGA_COREP
38,41,47,48 SUSP# EN SW PR626

.1U_0402_16V7K

5
VCORE_VDD

PC623

PC602
4 7 1 2

330U_6.3V_M
VFB V5IN +5VALW

1
0_0603_5% 1

AON6788_DFN8-5

2
DL_VCORE PR606

PR630
0_0402_5%
5 RF DRVL 6

PQ602
4.7_1206_5% +

PR625
470K_0402_1%
2

2
TP 11
PC628 4

2
RT8237 2
2.2U_0603_6.3V6K

1
1
2
C PC606 C

3
2
1
680P_0603_50V7K PR631

2
10_0402_5%
1 2

1000P_0402_50V7K
1000P_0402_50V7K
4.3K_0402_1%
15 VDD_SENSE

1
PR632

PC632
1
PC635

2
@

2
@

1
+3VS
PR625 = 470Kohm => FSW = 300KHZ
PR625 = 200Kohm => FSW = 350KHZ

2
PR625 = 100Kohm => FSW = 390KHZ PR633
20K_0402_1%
PR625 = 47Kohm => FSW = 400KHZ

1
PR634

1
100K_0402_1%

2
PQ605 PR635
@

2
1
PR641 PR640 D SSM3K7002FU_SC70-3 3K_0402_1%
20K_0402_1% 2 1 2
20K_0402_1% G GPU_VID0 13

2
B B
S

22K_0402_1%
.1U_0402_16V7K
PC633

PR636
+3VS

2
VFB(0.7)=Vout*Rbottom/(Rtop+Rbottom) @

1
1
@ PR642
100K_0402_1%
Pstate GPU_VID0 GPU_VID1 N12M-GE

SSM3K7002FU_SC70-3
@ PR643

2
1
D 3K_0402_1%

PQ606
P8/P12 0 x 0.85V 2 1 2
GPU_VID1 13
G
S

3
P0 1 x 1V @

2
PC634

22K_0402_1%
.1U_0402_16V7K

PR644
0 x

2
@
@

1
P0(cold) 1 x 1V

PR632=4.3K
PR633=20K
A A

PR641=20K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, March 04, 2011 Sheet 50 of 53
5 4 3 2 1
 5 4 3 2 1

EBUF!!!!!!!!QBHF!!!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
............................................................................................................................
2010/12/31(PVT) P36 Charger add snubber PR206,PC206 EMI command

2010/12/31(PVT) P36 Charger change boost to 2.2 ohm PR205 EMI command
D D

2010/12/31(PVT) P35 +3VALW/+5VALW add snubber PR336,PC336,PR356,PC336 EMI command

2010/12/31(PVT) P37 +1.5VP/+1.8VSP Change PR155,PR165 to 0 ohm EMI command

2010/12/31(PVT) P37 +1.5VP/+1.8VSP Change PQ151 to POK 5*6 EMI command

2010/12/31(PVT) P37 +1.5VP/+1.8VSP Reserve snubber PR156,PC156 EMI command

2010/12/31(PVT) P37 +1.5VP/+1.8VSP add PC165 for MEI EMI command

2010/12/31(PVT) P37 +VCCSA add snubber PR456,PC456 EMI command
C C
2010/12/31(PVT) P38 +1.05VS/+0.75 change PRQ401 to POK 5x6 EMI command

2010/12/31(PVT) P38 +1.05VS/+0.75 change PR405,PR510 to 0 ohm EMI command

2010/12/31(PVT) P38 +1.05VS/+0.75 change 0.75V enable PR279 tp PR282 HW command

2010/12/31(PVT) P39 +CPU_CORE change PC549,PC515,PC525 to correct rating design change

2010/12/31(PVT) P39 +CPU_CORE change PL503,PL504 to DCR 5% design change

2010/12/31(PVT) P39 +CPU_CORE change PC568 PC 566 to 5.8mmm capacitor design change

B 2010/12/31(PVT) P39 +CPU_CORE change PC551 for load line adjust design change B

2010/12/31(PVT) P39 +CPU_CORE change PR560 for program temperture design change
2010/12/31(PVT) P39 +CPU_CORE change PC505,PQ503 change to POK5X6 design change
2010/12/31(PVT) P40+VGA_CORE change PU600 to RT8237 design change

2010/12/31(PVT) P40+VGA_CORE change PR605,PR607 to 0ohm design change

2010/12/31(PVT) P40+VGA_CORE change PR601 to POK 5X6 EMI command
2010/12/31(PVT) P40+VGA_CORE change VID0 and VID1 compont chage design change
A
Security Classification Compal Secret Data Compal Electronics, Inc. A

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 51 of 53
5 4 3 2 1
 5 4 3 2 1

HW PIR (Product Improve Record)

PWWHA LA-7201P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2010/10/29
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 10/29 17 SWAP FBA_CMD2 and FBA_CMD11 Schematic error
D 2 10/29 18 SWAP FBA_CMD18 and FBA_CMD11 Schematic error D

3 10/29 21 Chane +3V_SPI to +3VS Schematic error

4 10/29 22 Add R23 for CLK_REQ_VGA# Reserve pull down for clock request

REVISION CHANGE: 0.2 TO 0.3

GERBER-OUT DATE: 2010/11/11
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 11/03 25,31 Add USB20_N9 & USB20_P9 Support Wimax
2 11/03 32 Co-Lay Giga LAN Giga LAN support
3 11/22 22 Add R584 & R564 for Panel select For HW common design
4 11/22 5 change D86 (SC100001M00) For HW common design
5 11/22 5 cancel D85 @ For HW common design
6 11/24 32 LAN 8105E-VC update to 8105E-VL For HW common design

C
PWWHA LA-7201P SCHEMATIC CHANGE LIST C
REVISION CHANGE: 0.4 TO 0.6
GERBER-OUT DATE: 2011/01/18
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 01/15 14 Change RV48 BOM structure from @ to HDMI@. For HDMI function
2 01/15 15 Add net name +IFPE_IOVDD & +IFPE_PLLVDD For HDMI function
3 01/15 15 Add LV12,CV160,CV169,CV170,CV173,LV8,CV178,CV159,CV176,CV182,CV215 For HDMI function
4 01/15 38 Add U19 BOM symbol for 9012 For EC 9012
5 01/15 19 Change R120 from 10Kohm to 47Kohm. For backlight PWM issue
6 01/15 35 Change UT2.6 & RT1 connector from +5VALW to +3V and del CT1. For LDO leakage issue
7 01/15 41 Add Q31 BOM symbol and add BOM structure PS3@. For power saving function
8 01/16 13 Change R25 BOM structure from @ to NHDMI@. For HDMI function
9 01/16 38 Delete U19.123 CLK_EC_R net name Due to duplicate net name
10 01/16 38 Change U19.104 & R745.2 & R747.2 net name from PM_PWROK_R to PM_PWROK_EC. Due to duplicate net name
11 01/18 38 Add R757 & R759 & U19 BOM symbol and add BOM structure S9012@ For EC9012 solution
B B
12 01/18 38 Add R767 and BOM structure S9012@ For EC9012 solution
13 01/19 21~29 Change U2 P/N from SA00003P440 to SA00004EE80. For PCH P/N update
14 01/19 21~29 Change U2 BOM structure from Q65R3@ to HM65R1@. For BOM structure update
15 01/19 40 Add U2 BOM symbol and BOM structure HM65R3@. For BOM structure update
16 01/19 33 Change UL3 to SP050006E00 For EMI
17 01/20 5,7,9 Change C93,R312,U10,Q14,R465,R463,C140 BOM structure to PS3@ For BOM structure update
18 01/20 41 Change Q31 BOM symbol structure from PS3@ to @ Only for PWWHA DIS unmount
19 01/20 9 Change Q46,R449,C179,C472,R420,R455,Q33 BOM structure from @ to PS3@ Only for PWWHA DIS PS3@

PWWHA LA-7201P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.6 TO 0.7
GERBER-OUT DATE: 2011/02/18
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 01/31 5 Change JFAN2.2 connect FAN_SPEED1, JFAN2.3 connect GND For FAN pin define modification
A 2 02/09 5,38 Change Q5,Q41 from SB570020110 to SB570020020 For common material A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR 1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 52 of 53
5 4 3 2 1
 5 4 3 2 1

HW PIR (Product Improve Record)

PWWHA LA-7201P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.6 TO 1.0
GERBER-OUT DATE: 2011/02/18
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 01/31 5 Change JFAN2.2 connect FAN_SPEED1, JFAN2.3 connect GND For FAN pin define modification
D 2 02/09 5,38 Change Q5,Q41 from SB570020110 to SB570020020 For common material D

3 02/17 5 Change C902,R1445,D85,D86,C900,C901,R1444 from mount to @. For unused PWM FAN

4 02/17 5 Change R24 from @ to mount. For use RPM FAN
5 02/17 40 Change R396,Q7 from 930@ to mount. For EC9012 function
6 02/17 31 Add C363 For solving ODD issue
7 02/17 31 Change SW3 from mount to @ For MP phase
8 02/17 41 Change C496,C499,C236,C249,C255 from NLS@ to @ For low cost power switch
9 02/17 41 Change R415,R419 from 47Kohm to 0ohm For low cost power switch
10 02/17 40 Change ZZZ P/N from DA60000L700 to DAZ0II00101 For MP phase
11 02/17 41 Change C252 from SE070104Z80 to SE071121J80 For low cost power switch
12 02/17 31 Change R561,R562,R457,Q53,R441,R440,C471,C217,Q45 from mount to ZODD@ For zero ODD function
13 02/18 21~29 Change U2 P/N from SA00004EE80 to SA00004EES0 For PCH B3 version
14 02/18 40 Change U2 P/N from SA00004EEA0 to SA00004EET0 For PCH B3 version
15 02/22 40 ADD UV1 BOM symbol and BOM structure N12MR3@. For N12M R3 P/N
C
16 02/22 13~16 ADD UV1 BOM structure N12MR1@. For N12M R1 P/N C

17 02/23 32,35,41 Change Q50,Q53,QT3 from SB00000EO00 to SB00000EO10 For common material
18 02/23 41 Change C465,C467 BOM structure from OLS@ to always mount For low cost power switch

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR 2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 53 of 53
5 4 3 2 1
www.s-manuals.com