CSE 401

Computer Engineering (2)

)2( ‫هندسة الحاسبات‬

4th year, Comm. Engineering

Lecture #2
Dept. of Computer & Systems Engineering
Credits to Dr. Hazem Shehata and Dr. Ahmed Abdul-Monem Ahmed for the slides
Chip Logic
• Semiconductor memory comes in packaged chips.
• Each mem. chip contains an array of memory cells.
• Design issue: number of bits of data that maybe
read/written at a time.
—One extreme: 1-word-per-chip organization: physical
arrangement of cells in the array is the same as logical
arrangement of words in memory.
– EX.: 1Mx16 memory = One 1Mx16 chip.
—Other extreme: 1-bit-per-chip organization: data is
read/written 1 bit at a time.
– Ex.: 1Mx16 memory = sixteen 1Mx1 chips s.t. chip #1 holds bit
#1 of each word, chip #2 holds bit #2 of each word, and so on.
Typical 16 Mb
DRAM (4Mx4)
 Typical 16 Mb DRAM (4M x 4)
•11 address signals are passed to define the row
address, accompanied by asserting RAS’ (row address
select)
• Then, 11 other address signals are passed to define
the column address, accompanied by asserting CAS’
(Column address select)
 Typical 16 Mb DRAM (4M x 4)
• If WE’ (write enable) is asserted:
-Bit driver of each bit line is activated; (4 lines, one for
each bit) -Voltage signal is applied to bit line
-A signal is applied to address line, allowing capacitor
to charge
• If OE’ (output enable)is asserted: -Address line is
selected, transistor turns on -Charge stored in
capacitor is fed out onto a bit line to a sense
amplifier -Sense amplifier compares capacitor
voltage to a reference value & determines if cell
contains a logic 0 or 1 -Value is presented to data
line; (4 lines, one for each bit)
Typical 16 Mb DRAM (4M x 4)
• To select a specific bit: — Select an address,
then assert RAS’ (row address select — Then,
select another address, then assert CAS’ (column
address select)
• Then assert WE’, or OE’ (write enable and
output enable)
• Reduces number of address pins — Multiplex
row address and column address — 11 pins to
address (211=2048) — Adding one more pin
doubles range of values.
Refreshing
Why does DRAM cell need refreshment?
• A DRAM cell consists of a capacitor to store one
bit of data as electrical charge.
• The capacitor leaks charge over time, causing
stored data to change.
• As a result, DRAM requires an operation called
refresh that periodically restores electrical
charge in DRAM cells to maintain data integrity
Refreshing
• Refresh circuit included on chip.
• Disable chip.
• Count through rows.
• Data is read out and written back into the same
location ➔ each cell is refreshed.
• Takes time.
• Slows down apparent performance.
Refreshing
A memory cell is automatically refreshed by:
• Accessing its row
• Reading from it
• Writing into it

• Usually, DRAM is refreshed by:

• Placing a row address on address lines &
asserting RAS’
• Use a counter to go through all row addresses,
while RAS’ is activated.
 Chip Packaging

• 8-Mbit EPROM chip, 1M x 8. • 16-Mbit DRAM, 4M x 4.

• One-word-per-chip package. • Updatable ➔ data pins in/out.
• Address: A0-A19, Data: D0-D7 • WE: Write Enable
• Vcc; power, Vss: ground, CE: chip • OE: Output Enable
enable, Vpp: programming voltage. • NC: No Connect ➔ even # of pins
 Module
Organization

• Available: 256k x 1 chips

256k x 8 memory
Module
Organization
• In this memory module of 256k 8-bit words, 18
bit address is needed & is supplied to the
module from some external source.
• The address is presented to 8 256Kx1 bit chips
each provides I/O of 1 bit.
• When larger memory is required, an array of
chips is needed.
 Module Organization (2)
• Available: 256k x 1-bit chips
1M x 8 memory
Error Correction
• Semiconductor memory is subject to errors
— Rate: 1 error/hour to 1 error/century in a 1GB memory!
— Types: hard and soft.
• Hard Failure
— Permanent physical defect.
— Mem. cells can’t store data: stuck at 0 or 1, or switching.
— Caused by harsh environments, manufacturing defects, or wear.
• Soft Error
— Random, non-destructive event that alters contents of one or
more memory cells.
— No permanent damage to memory.
— Caused by power supply problems or alpha particles.
• Detected/corrected using Hamming error correcting code.
Error-Correcting Code Function
 Error-Correcting Code Function
• When data are to be read into memory, a calculation
is performed on the data to produce a code of length
k.
• Code and data are stored. If an m bit word is to be
stored, then the size of stored word is M + K bits
• Code is used to detect and possibly correct errors. A
new set of k code is generated form k data bits and
compared with fetched code bits. This yields to:
▪ No errors are detected. The fetched data bits are sent out
▪ An error is detected, and possible to correct it. The data bit plus error correction
bits are fed into the corrector, which produce a set of M bits to be sent out.
▪ An error is detected, but it is not possible to correct it. This condition is reported
Hamming Error-Correcting Code
Data bits: 1110
B
A
1 1 0
1
0
1 0
Discrepancies
0

Parity bits
C
Chosen so that total number of 1s in each circle is even.
By checking the parity bits, discrepancies are found ➔ error
can be easily found and corrected.
Error-Correcting Codes
• A codeword consists of N bits split into M data
bits and K check (redundant) bits
— N = M + K.
• Hamming distance: Number of bit-positions in
which two codewords differ.
— Ex.: 11001001, 10100001 → Hamming distance = 3 →
3 bit errors are needed to convert one into the other.
• Note: in a code, not all 2N codewords are legal.
• Hamming distance of the whole code: minimum
Hamming distance between 2 legal codewords.
• A distance d code can:
— Detect: d – 1 errors.
— Correct: (d – 1)/2 errors if d is odd, or (d/2) – 1 errors if
d is even.
Error Detection/Correction
• Detection: parity bit.
• Distance = 2 → can detect up to 1 bit error.
• Ex.: data=1011010 → codeword=10110100 → any
codeword with a distance = 1 (such as: 10100100)
is considered illegal → single-bit errors are
detectable.
• Correction: Consider a code with 4 valid
codewords:
0000000000, 0000011111, 1111100000, 1111111111
• Distance = 5 → can correct up to 2 bit errors.
• If 0000000111 arrives, → 0000011111
• If 0000000000 becomes 0000000111 due to 3
errors → cannot be corrected properly.
Single Bit Error Correction

Design a code to correct all single bit errors.

• M = data bits, K = check bits
•N=M+K
• Rule: Choose K s.t. M + K + 1 ≤ 2K
Hamming Code

2K - 1 ≥ M + K ➔ 2K ≥ 9+K ➔ K = 4

1 0 0 1 1 0 1 0 Data bits

12 11 10 9 8 7 6 5 4 3 2 1
0 1 0 1 ?
1 0 0 1 ? 1 0 1
? 1
?

0 1
0 1 1
0 0 =?
Bit position 8
1
2
4 Bit position 8:
1: 0
2:
4: 1
Hamming Code
Hamming Code (2)
12 11 10 9 8 7 6 5 4 3 2 1
1 0 0 0
1 ?
0 1 0 1 ?
1 0 1
? 1
?

• Assume error in bit 9.

• Recompute the check bits.
• Bit 1 = 0 (error).
• Bit 2 = 1.
• Bit 4 = 1.
• Bit 8 = 1 (error).
• Error is in bit position = 1 + 8 = 9 → flip it
(correction).
Hamming SEC-DED Code

Wrong!!!
A B
1
0 0 1
0
1
1 1
0 Fix error

0 Discrepancies

C
Hamming SEC-DED Code (2)

A B
1
0 0 1
0
1
1 1
0 Fix error

0 Discrepancies

×1 C
Hamming SEC-DED Code (3)
Increase in Word Length with Error Correction
PROJECT : TASK 2

Find an idea:

• Hamming code circuit:

Ben Eater:'s take: https://youtu.be/h0jloehRKas

• Another related ideas:

List of Semester Projects for Computer
Organization (krchowdhary.com)
PROJECT : TASK 2
Guidelines:
Each project is to be done by a group of 3-5 students.
The projects are to be implemented in any of the
programming language: C, C++, Java or any
simulators.
Some projects are theoretical work.
Optional to use hardware components
Each project work carries documentation in the form of
a project power point presentation to be submitted as
electronic version.
 PROJECT : TASK 2
The project PowerPoint presentation structure is:
1. Title
2. Objective: (The objective describes the goal of the project work.)
3. Theory: (The theory is formal design comprising descriptions, essential
mathematics, formulas, drivations, etc.)
4. Design: (The design part comprises flow-charts, algorithms, tables, diagrams,
derivations, etc.)
5. Implementation: (The implementation is description of functional modules of
code, hierarchical relationship, coding with built-in documentation, list of system
requirements, like compilers, operating system, etc.)
6. Debugging-Test-run: (The Test-run and result part of the report contains detailed
method of testing, assuring that the code is fool-proof and fully debugged.)
7. Results analysis (if any): (The Analysis part should discuss other aspects, like
complexity of algorithms in terms of average and worst case complexity for time
and space, robutsness of the approach used, finer technical details, etc.)
 PROJECT : TASK 2
8.Conclusion and Future Improvements: (The conclusion and future
aspect should summarize the project in brief, what improvements can
be possible which could not be considered due to time limits,
limitations (if any in the design and implementation), various
applications of this design, etc.)
9. Bibliography: The bibliography section should provide the detailed
list of references of books, journals, websites, conferences, and others
in the standard accepted formats.
10. Video describes the details of all the above. This video will be
uploaded in YouTube channel. (link should be added in the
presentation)
• The presentation should have a front cover in the standard
form, generally used for graduate projects, giving project title,
class, name of student, guide, name of Institution, year, and
month & year of submission, all in standard acceptable formats.