Lab3: Single Cycle Processor design and simulation with EDA tool SoC

Design Course
LAB3: Single Cycle Processor Design and
Simulation with EDA Tool

Learning Objectives

After completing this lab, you should be able to:

• Design a single cycle processor.

Build testbench, write testcases and verifying the design using Vivado
tool.

Lecturer: [email protected]
Lab3: Single Cycle Processor design and simulation with EDA tool SoC
Design Course
PART 1: Single Cycle Processor Design
Introduction
An instruction set architecture is an interface that defines the hardware operations which are
available to software. Any instruction set can be implemented in many different ways. In a
basic single-cycle implementation all operations take the same amount of time - a single
cycle. A multi-cycle implementation allows faster operations to take less time than slower
ones, so overall performance can be increased. Finally, pipelining lets a processor overlap the
execution of several instructions, potentially leading to big performance gains.

In this lab you will design a pipeline cycle processor in part 1 and then verify the design in
part 2.

Description
In this part, we will design a single cycle processor which supports the following instructions:
Arithmetic: add sub and or slt
Data Transfer: lw sw
Control: beq

The data path of the processor is shown in the Fig. 1.

Figure 1: Single cycle processor

Lecturer: [email protected]
Lab3: Single Cycle Processor design and simulation with EDA tool SoC
Design Course

Figure 2: Pipeline processor

Instruction Format
R-type instructions
Register-to-register arithmetic instructions use the R-type format. op is the instruction
opcode, and func specifies a particular arithmetic operation. rs, rt and rd are source and
destination registers.
op rs rt rd shamt func
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
An example instruction and its encoding:
add $s4, $t1, $t2
000000 01001 01010 10100 00000 100000

I-type instructions
The lw, sw and beq instructions all use the I-type encoding. rt is the destination for lw, but a
source for beq and sw. address is a 16-bit signed constant.

op rs rt address
6 bits 5 bits 5 bits 16 bits

Two example instructions:

o lw $t0, –4($sp)

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Lab3: Single Cycle Processor design and simulation with EDA tool SoC
Design Course
100011 11101 01000 1111 1111 1111 1100
o sw $a0, 16($sp)
101011 11101 00100 0000 0000 0001 0000

Registers and ALUs

R-type instructions must access registers and an ALU. Our register file stores thirty-two 32-
bit values. Each register specifier is 5 bits long. You can read from two registers at a time.
RegWrite is 1 if a register should be written. Here’s a simple ALU with five operations,
selected by a 3-bit control signal ALUOp.

ALUOp Function

000 and

001 or

010 add

110 subtract

111 slt

The control signals

Operation RegDst RegWrite ALUSrc ALUOp MemWrite MemRead MemToReg

add 1 1 0 010 0 0 0

sub 1 1 0 110 0 0 0

and 1 1 0 000 0 0 0

or 1 1 0 001 0 0 0

slt 1 1 0 111 0 0 0

Lecturer: [email protected]
Lab3: Single Cycle Processor design and simulation with EDA tool SoC
Design Course
lw 0 1 1 010 0 1 1

sw X 0 1 010 1 0 X

beq X 0 0 110 0 0 X

In the table 1:

o The sw and beq are the only instructions that do not write any registers.
o lw and sw are the only instructions that use the constant field. They also depend on
the ALU to compute the effective memory address.
o ALUOp for R-type instructions depends on the instructions’ func field.
o The PCSrc control signal (not listed) should be set if the instruction is beq and the
ALU’s Zero output is true.

In the lab, a sketch of the design is provided in the file

“single_cycle_processor.v”. You are encouraged to use it to develop
your design source code.

Lecturer: [email protected]
Lab3: Single Cycle Processor design and simulation with EDA tool SoC
Design Course
PART 2: Single Cycle Processor Verification
Getting started
• Plan a check list which will list all test cases to cover all functions of your processor
• Build the testbench including all necessary components to drive the inputs and
monitor the outputs of the DUT (your processor design).
• Develop a script to make the simulation process more automatically.
• Compile and simulate the design using Vivado simulator tool.
• Check the functions of the DUT and debug issues if it happens. Using Vivado
simulator tool for debug the design on waveform
You can use the sketch files which are provided in the lab source code:
• Ram.v: RAM memory model which is used for storing and loading data by lw and sw
instructions
• Rom.v: ROM memory model which contains instructions.
• Tb.v: testbench file which is a sample for developing your testbench.

*Note:
• See the file “lab2_MIPS_instruction_Info.pdf” to understand the operation of MIPS
instructions for this lab.
• MUST use the signal names in this lab guide in your Verilog modules

Lecturer: [email protected]