Sequential Circuit

1.1. Learning Objectives

On completion of this lesson you will be able to :

♦ define sequential circuit

♦ know the different types of sequential circuit
♦ understand clock and its classification
♦ know about flip-flop and latches.

1.2. Sequential Circuits

We already know that the combinational circuits implements the

essential functions of a digital computer. "A circuit known as
In sequential logic circuit, combinational as long as its steady state outputs depend only on its
"the present values of current inputs". In these circuits, there is no ability to retain the
outputs are dependent on
information regarding the state of the circuit and any prior input level
both present values of the
inputs and the past values conditions have no effect on the present outputs because they provide no
of inputs. memory. So for the later purposes, sequential circuit is used. In
sequential logic circuit, the present values of outputs are dependent on
both present values of the inputs and the past values of inputs. A
sequential logic circuit consist of two parts.

♦ the memory elements i.e. flip-flop which is made up of an

assembly of logic gates.
♦ the combinational logic circuits needed to produce the
excitation inputs to the memory elements and to produce the
required outputs.

Sequential circuits find wide application in digital systems as counters,

registers, control logic, memories and other complex functions.

Examples,

♦ The elevator control.

♦ The traffic light system.
♦ automatic lock - which remember the combination of numbers
and also their sequence.
 Digital Systems and Computer Organization

Basic Block

A general model of a sequential circuit is shown in the following Fig.3.1.

(Inputs) I Combinational O (Output)

Circuit

Output depends on present

s tate and input.
Memory
(Present state) y Circuit Y (Next state)

Fig. 3.1 : Block diagram of sequential circuit logic.

So, from the block diagram, we can find.

Output depends on present state and input i.e.

output O = f (I, y)
next state Y = f (I, y)
present state y = f (Y)

1.3. Clock

Clock is periodic sequence of pulses. Clock can be classified as level

clocking and edge triggering.

Clock
Clock is periodic sequence of
pulses.
Level clocking Edge triggering

Purposes

The purposes of clock is to synchronize the over-all action and to

prevent the flip-flop from changing states until the right time.

a) Level clocking : The Flip-flop responds to the level (high or low) of

the clock signal. Level clocking is of two types.

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i) positive clocking

1 1

S y
y S S y y
ck ck
R y y R y y
R

Fig. 3.2(a) : Basic block of latch (SR).

ii) negative clocking

1 1
S S y y
ck ck
R R y y
0 0
Fig. 3.2 (b) : negative clocking.

b) Edge Triggering : The flip-flop responds only on the rising or

falling edge of the clock. Edge triggering is of two types. These are
as follows :
The flip-flop responds only
o n the rising or falling edge
i) positive edge triggering
o f the clock.

S S y y
ck ck
R R y y

Fig. 3.3 (a) : positive edge triggering.

ii) negative edge or falling (trailing edge)

S S y y
ck ck
R R y y

Fig. 3.3 (b) : negative edge triggering.

1.4. Types of Sequential Logic Circuits

Depending upon the timing of sequential circuit signal, the sequential

logic circuits can be divided into two classes.

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Sequential logic circuits

Synchronous Asynchronous

Fig. 3.4: Classes of sequential logic circuits.

Synchronous Sequential Circuits

A synchronous sequential A synchronous sequential circuits is one in which the contents of the
ccircuit’s is one in which the memory can change only at discrete instants time or on the of transitions
ccontents of the memory can of a clock. Since all the circuit action will take place under the control of
cchange only at discrete a clock, so these circuits are known as clocked sequential circuit.
i instant’s time or on the of
ttransitions of a clock. Advantage

They are easier to troubleshoot and design because its outputs can
change only at specific instants of time i.e. every thing is synchronized
to the clock signal transition.

Asynchronous Sequential Logic Circuits

An asynchronous sequential logic circuits is one whose outputs can

An asynchronous sequential
l logic circuits is one whose
change state at any instant of time with the change of one or more of the
ooutputs can change state at
inputs. The memory elements used in these systems are delay type
aany instant of time with the memory elements. It can be regarded as combinational circuit with feed
cchange of one or more of the back.
i inputs.
Disadvantage

It is difficult to design and troubleshoot and used only for simple

configuration.

1.5. Flip-flops (FF)

A FF is an electronic device that has two stable states. One state is

assigned the logic 1 value and the other is the logic 0. In other words, the
memory elements used in sequential circuits are the flip flop. These
circuits are binary cells capable of storing one bit of information.

Latch
A latch is a bistable circuit
that is the fundamental A latch is a bistable circuit that is the fundamental building block of a
building block of a flip-flop. flip-flop. It exists in one of the two states (e.g. 1 and 0), and in the
absence of the input, it remains in that state. It has two output y and y.

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The following Fig. 3.5 illustrate a simple FF or 1 bit memory (i.e. it can
store one bit of information y = 0 or y = 1) and since this information is
locked or latched so, this FF is known as a latch.

x1 y

x2 y
Fig. 3.5 : Simple FF or latch.

SR (Set – Reset} Latch

2.1. S-R Latch

The SR latch is a circuit with two cross-coupled NOR gates , and two
inputs labeled S for set and R for reset. The SR latch nstructed with two
cross-coupled NOR gates is shown in Fig. 5.3 . The latch has two useful
states. When output Q = 1, and Q /= 0, the latch is said to be in the set
state . When Q = 0 and Q /=1, it is in the reset state . Outputs Q and Q/
are normally the complement of each other. However, when both inputs
are equal to 1 at the same time, a condition in which both outputs are
equal to 0 (rather than be mutually complementary) occurs. If both inputs
are then switched to 0 simultaneously, the device will enter an
unpredictable or undefined state or a metastable state. Consequently, in
practical applications, setting both inputs to 1 is forbidden.

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Under normal conditions, both inputs of the latch remain at 0 unless the
state has to be changed. The application of a momentary 1 to the S input
causes the latch to go to the set state. The S input must go back to 0
before any other changes take place, in order to avoid the occurrence of
an undefined next state that results from the forbidden input condition.
As shown in the function table of Fig. 5.3 (b), two input conditions cause
the circuit to be inthe set state. The first condition (S = 1,R = 0) is the
action that must be taken by input S to bring the circuit to the set state.
Removing the active input from S leaves the circuit in the same state. After
both inputs return to 0, it is then possible to shift to the reset state by
momentary applying a 1 to the R input. The 1 can then be removed from
R, whereupon the circuit remains in the reset state. Thus, when both inputs
S and R are equal to 0, the latch can be in either the set or the reset state,
depending on which input was most recently a 1. If a 1 is applied to both
the S and R inputs of the latch, both outputs go to 0. This action produces
an undefined next state, because the state that results from the input
transitions depends on the order in which they return to 0. It also violates
the requirement that outputs be the complement of each other. In normal
operation, this condition is avoided.

D Latch
This latch has only two inputs: D (data) and En (enable). One way to
eliminate the undesirable condition of the indeterminate state in the SR
latch is to ensure that inputs S and R are never equal to 1 at the same time,
this is taken taken care in D latch as shown in Fig 5.6. . The D input goes
directly to the S input, and its complement is applied to the R input. As
long as the enable input is at 0, the cross-coupled SR latch has both inputs
at the 1 level and the circuit cannot change state regardless of the value of
D.

The D input is sampled when En = 1. If D = 1, the Q output goes to 1,

placing the circuit in the set state. If D = 0, output Q goes to 0, placing the
circuit in the reset state. The D latch receives that designation from its
ability to hold data in its internal storage. It is suited for use as a temporary
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storage for binary information between a unit and its environment. The
binary information present at the data input of the D latch is transferred to
the Q output when the enable input is asserted. The output follows
changes in the data input as long as the enable input is asserted.

Edge-Triggered D Flip-Flop
The construction of a D flip-flop with two D latches and an inverter is
shown in Fig. 5.9 . The first latch is called the master and the second the
slave. The circuit samples the D input and changes its output Q only at the
negative edge of the ynchronizing or controlling clock (designated as Clk
). When the clock is 0, the output of the inverter is 1. The slave latch is
enabled, and its output Q is equal to the master output Y . The master latch
is disabled because Clk = 0. When the input pulse changes to the logic-1
level, the data from the external D input are transferred to the master. The
slave, however, is disabled as long as the clock remains at the 1 level,
because its enable input is equal to 0. Any change in the input changes the
master output at Y, but cannot affect the slave output. When the clock
pulse returns to 0, the master is disabled and is isolated from the D input.
At the same time, the slave is enabled and the value of Y is transferred to
the output of the flip-flop at Q . Thus, a change in the output of the flip-
flop can be triggered only by and during the transition of the clock from 1
to 0.
The behavior of the master–slave flip-flop just described dictates that (1)
the output may change only once, (2) a change in the output is triggered
by the negative edge of the clock, and (3) the change may occur only
during the clock’s negative level. The value that is produced at the output
of the flip-flop is the value that was stored in the master stage immediately
before the negative edge occurred .

Characteristic Tables
A characteristic table defines the logical properties of a flip-flop by
describing its operation in tabular form. They define the next state (i.e., the
state that results from a clock transition). as a function of the inputs and
the present state. Q ( t ) refers to the present state (i.e., the state present
prior to the application of a clock edge). Q(t + 1) is the next state one
clock period later. Note that the clock edge input is not included in the
characteristic table, but is implied to occur between times t and t + 1.
Thus, Q(t) denotes the state of the flip-flop immediately before the clock
edge, and Q(t + 1) denotes the state that results from the clock transition

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The characteristic table of D FF is shown above.

Characteristic Equations
The logical properties of a flip-flop, as described in the characteristic
table, can be expressed algebraically with a characteristic equation. For
the D flip-flop, we have the characteristic equation
Q(t + 1) = D
which states that the next state of the output will be equal to the value of
input D in the present state.

JK Flip Flop

The circuit diagram of a JK flip-flop constructed with a D flip-flop and

gates is shown in Fig. 5.12 (a). The J input sets the flip-flop to 1, the K
input resets it to 0, and when both inputs are enabled, the output is
complemented. This can be verified by investigating the circuit applied to
the D input:
D = JQ /+ K_Q
When J = 1 and K = 0, D = Q / + Q = 1, so the next clock edge sets the
output to 1.
When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q /, the next clock edge complements the
output. When both J = K = 0 and D = Q, the clock edge leaves the output
unchanged. The graphic symbol for the JK flip-flop is shown in Fig. 5.12
(b). It is similar to the graphic symbol of the D flip-flop, except that now
the inputs are marked J and K .

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There are three operations that can be performed with a flip-flop: Set it to
1, reset it to 0, or complement its output. With only a single input, the D
flip-flop can set or reset the output, depending on the value of the D input
immediately before the clock transition. Synchronized by a clock signal,
the JK flip-flop has two inputs and performs all three operations

The characteristic table of JK FF is as shown in Table 5.1. The

characteristic table for the JK flip-flop shows that the next state is equal to
the present state when inputs J and K are both equal to 0. This condition
can be expressed as Q(t + 1) = Q(t), indicating that the clock produces no
change of state. When K = 1 and J = 0, the clock resets the flip-flop and
Q(t + 1) = 0. With J = 1 and K = 0, the flip-flop sets and Q(t + 1) = 1.
When both J and K are equal to 1, the next state changes to the
complement of the present state, a transition that can be expressed as
Q(t + 1) = Q / (t).

The characteristic equation for the JK flip-flop can be derived from the
characteristic table . We obtain

T Flip Flop

The T (toggle) flip-flop is a complementing flip-flop and can be obtained

from a JK flip-flop when inputs J and K are tied together. This is shown in
Fig. 5.13 (a). WhenT = 0 (J = K = 0), a clock edge does not change the
output. When T = 1 (J = K = 1), a clock edge complements the output.
The complementing flip-flop is useful for designing binary counters.
The T flip-flop can be constructed with a D flip-flop and an exclusive-OR
gate as shown in Fig. 5.13 (b). The expression for the D input in Fig. 5.13
(b). The expression for the D input is.

When T = 0, D = Q and there is no change in the output. When T = 1, D =

Q_ and the output complements. The graphic symbol for this flip-flop has
a T symbol in the input.

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The characteristic table of the T flip-flop shown above has only two
conditions: When T = 0, the clock edge does not change the state; when T
= 1, the clock edge complements the state

The characteristic equation for the T flip-flop isof the flip-flop.

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