STM32F4xx

System Peripherals
Innovative system Architecture
CORTEX-M4 Ethernet High Speed Dual Port Dual Port
CCM 168MHz 10/100 USB2.0 DMA1 DMA2
data RAM w/ FPU & MPU
64KB Master 5 Master 4 Master 2 Master 3
Master 1
FIFO/DMA FIFO/DMA FIFO/8 Streams FIFO/8 Streams

Dual Port
S-Bus
D-Bus

I-Bus

AHB1-APB2
AHB1
Dual Port
AHB1-APB1
AHB2

SRAM1
112KB

SRAM2
16KB

FSMC

Accelerator
I-Code FLASH

ART
D-Code
1Mbytes

Multi-AHB Bus Matrix

Architecture : CPU, DMA & Multi-Bus Matrix
CORTEX-M4 Ethernet High Speed Dual Port Dual Port
CCM 168MHz 10/100 USB2.0 DMA1 DMA2
data RAM w/ FPU & MPU
64KB Master 5 Master 4 Master 2 Master 3
Master 1 Dual Port
Slow Peripherals
FIFO/DMA FIFO/DMA FIFO/8 Streams FIFO/8 Streams AHB1-APB1

Dual Port
Fast Peripherals
AHB1-APB2

AHB1 GPIOs

AHB2 DCMI, Crypto,

USB Full Speed

SRAM1
112KB

SRAM2
16KB

FSMC

FLASH
ART Up to
Accelerator
1Mbytes
Multi-AHB Bus Matrix
 Real-time performance

Decompressed
MP3
Access
DMA
User decoder
to theto
transfer
interface:
Compressed
32-bit multi-AHB bus matrix audio
code
MP3
audio
DMA
audio stream
data forto
execution
output
transfers
stream
112kByte
of stage
the
(MP3) SRAM
bygraphical
core
decompression
(I2S)
to
icons block
fromSRAM
16kByte Flash
to block
display
System Architecture – Role of the ART
accelerator

PFQ FLASH
4x32-bit buffer
-M4 F
8x16-bit buffer
E
with FPU & MPU T
C I-32-bit I1- 32-bit
Up to 128-bit
168MHz H I2- 32-bit
I3- 32-bit
D-32-bit

I4- 32-bit
BC
64 rows of

BC 128-bit-I
8 rows of
128-bit -D
Branch Cache stores the 64 LRU
Branch Cache stores 8 rows of branches and feeds the CPU
128-bit data (literals) without latency in case of a Hit.
System Architecture - Bootloader

BOOT Mode
Selection Pins Boot Mode Aliasing
BOOT1 BOOT0

x 0 Flash memory Main Flash memory is selected as boot space

0 1 System memory System memory is selected as boot space

1 1 Embedded SRAM Embedded SRAM is selected as boot space

 The Bootloader supports

 USART1(PA9/PA10)
 USART3(PC10/PC11 or PB10/PB11)
 CAN2(PB5PB13)
 USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade)
Note
 The DFU/CAN may work w/ different value of external quartz in the range of 4-26 MHz, and the
USART uses the internal HSI
 This Bootloader uses the same USART, CAN and DFU protocols as for STM32F2xx/STM32F10x
System Architecture - Boot mode through I-D code bus
 STM32F4xx allows to execute from 3 different memory space mapped on the I-Code/D-Code
busses  Faster code execution than System bus

 This is done by SW in SYSCFG_MEMRMP register, 2 bits are used to select the physical remap
and so, bypass the BOOT pins.
 00: Main Flash memory mapped at 0x0000 0000
 01: System Flash memory mapped at 0x0000 0000
 10: FSMC (NOR/SRAM bank1 NE1/NE2) mapped at 0x0000 0000
 11: Embedded SRAM (112kB) mapped at 0x0000 0000

BOOT/REMAP in Main BOOT/REMAP in BOOT/REMAP in System

REMAP in FSMC
Flash memory Embedded SRAM memory

0x2001 C000 - 0x2001 FFFF SRAM2 (16kB) SRAM2 (16kB) SRAM2 (16kB) SRAM2 (16kB)

0x2000 0000 - 0x2001 BFFF SRAM1 (112kB) SRAM1 (112kB) SRAM1 (112kB) SRAM1 (112kB)

0x1FFF 0000 - 0x1FFF 77FF System memory System memory System memory System memory

0x1000 0000 - 0x1000 FFFF CCM Data RAM (64KB) CCM Data RAM (64KB) CCM Data RAM (64KB) CCM Data RAM (64KB)

0x0810 0000 - 0x0FFF FFFF Reserved Reserved Reserved Reserved

0x0800 0000 - 0x080F FFFF FLASH (1MB ) FLASH (1MB ) FLASH (1MB ) FLASH (1MB )

0x0010 0000 - 0x07FF FFFF Reserved Reserved Reserved FSMC NOR/SRAM 2 Bank1 (Aliased)

System memory (30KB)

0x0000 0000 - 0x000F FFFF FLASH (1MB ) Aliased SRAM1 (112kB) Aliased FSMC NOR/SRAM 1 Bank1 (Aliased)
Aliased
Flash Features Overview
 Flash Features:
 Up to 1MB (sectors 16kB, 64kB and 128kB)
 Endurance: 10k cycles by sector / 20 years retention
 32-bit Word Program time: 12µs(typ)
 Flash interface (FLITF) Features:
 128b wide interface with prefetch buffer and data cache, instruction cache
 Option Bytes loader
 Flash program/Erase operations
 Types of Protection:
 Readout Protection: Level 1 and Level 2 (JTAG Fuse)
 Write Protection (sector by sector)
 The Information Block consists of:
 30 kB for System Memory : contains embedded Bootloader.
 16 B for Small Information block (SIF): contains 8 option bytes + its complementary
part (write/read protection, BOR configuration, IWDG configuration, user data)
 512 Bytes OTP: one-time programmable
Flash Operations
Relation between CPU clock frequency and Flash memory read time

HCLK clock frequency (MHz)

Wait states(WS)
(LATENCY) Voltage range Voltage range Voltage range Voltage range
2.7 V - 3.6 V 2.4 V - 2.7 V 2.1 V - 2.4 V 1.8V - 2.1 V

0WS(1CPU cycle) 0 < HCLK <= 30 0 < HCLK <= 24 0 < HCLK <= 18 0 < HCLK <= 16

1WS(2CPU cycle) 30 < HCLK <= 60 24 < HCLK <= 48 18 < HCLK <= 36 16 < HCLK <= 32

2WS(3CPU cycle) 60 < HCLK <= 90 48 < HCLK <= 72 36 < HCLK <= 54 32 < HCLK <= 48

3WS(4CPU cycle) 90 < HCLK <= 120 72 < HCLK <= 96 54 < HCLK <= 72 48 < HCLK <= 64

4WS(5CPU cycle) 120 < HCLK <= 150 96 < HCLK <= 120 72 < HCLK <= 90 64 < HCLK <= 80

5WS(6CPU cycle) 150 < HCLK <= 168 120 < HCLK <= 144 90 < HCLK <= 108 80 < HCLK <= 96

6WS(7CPU cycle) 144 < HCLK <= 168 108 < HCLK <= 126 96 < HCLK <= 112

7WS(8CPU cycle) 126 < HCLK <= 144 112 < HCLK <= 128

Note: Latency when VOS bit in PWR_CR is equal to „1‟

Flash Protections

Level 1
RDP ≠ 0xCC
RDP ≠ 0xAA
•Readout protection
•BLOCKED access to memory from
SRAM, system memory and JTAG
•Remove readout protection possible
after full erase of the memory and its
blank verification

Level 2 Level 0
RDP=0xCC RDP=0xAA
•JTAG fuse •No readout protection
•No un-protection possible •Full access to memory from
•JTAG disabled SRAM, system memory and
•System memory disabled JTAG
•User settings protected
CRC Features
 CRC-based techniques are used to verify data transmission or storage integrity

 Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

X32+ X26+ X23 + X22 + X16+ X12 + X11+ X10 + X8 + X7 + X5 + X4 + X2 + X + 1

 Single input/output 32-bit data register

 CRC computation done in 4 AHB clock
cycles (HCLK) AHB Bus
32-bit (read access)
 General-purpose 8-bit register (can be
used for temporary storage) Data register (Output)

CRC computation (polynomial: 0x4C11DB7)

32-bit (write access)
Data register (Input)
DMA Features
 Dual AHB master bus architecture, one dedicated to memory accesses and
one dedicated to peripheral accesses.

 8 streams for each DMA controller, up to 8 channels (requests) per stream (2

DMA controllers in STM32F4xx family). Channel selection for each stream is
software-configurable.

 4x32-Bits FIFO memory for each Stream (FIFO mode can be enabled or
disabled).

 Independent source and destination transfer width (byte, half-word, word):

when the source and destination data widths are different, the DMA
automatically packs/unpacks data to optimize the bandwidth. (this feature is
available only when FIFO mode is enabled)

 Double buffer mode (double buffer mode can enabled or disabled).

 Support software trigger for memory-to-memory transfers (available for the

DMA2 controller streams only)
DMA Features
 The number of data to be transferred can be managed either by the DMA
controller or by the peripheral

 Independent Incrementing or Non-Incrementing addressing for source and

destination. Possibility to set increment offset for peripheral address.

 Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst

is software-configurable, usually equal to half the FIFO size of the peripheral

 Each stream supports circular buffer management.

 5 event flags logically ORed together in a single interrupt request for each stream

 Priorities between DMA stream requests are software-programmable

DMA1 Controller
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Ch0 SPI3_RX -- SPI3_RX SPI2_RX SPI2_TX SPI3_TX -- SPI3_TX

Ch1 I2C1_RX -- TIM7_UP -- TIM7_UP I2C1_RX I2C1_TX I2C1_TX

Ch2 I2S2_EXT_ I2S2_EXT_T I2S3_EXT_T

TIM4_CH1 -- TIM4_CH2 TIM4_UP TIM4_CH3
RX X X

Ch3
I2S3_EXT_ TIM2_UP I2S2_EXT_ TIM2_CH2 TIM2_UP
I2C3_RX I2C3_TX TIM2_CH1
RX TIM2_CH3 RX TIM2_CH4 TIM2_CH4

USART3_R USART3_T USART2_R USART2_T

Ch4 UART5_RX UART4_RX UART4_TX UART5_TX
X X X X

TIM3_CH4 TIM3_CH1
Ch5 -- -- -- TIM3_CH2 -- TIM3_CH3
TIM3_UP TIM3_TRIG

Ch6 TIM5_CH3 TIM5_CH4 TIM5_CH4 TIM5_UP

TIM5_CH1 TIM5_CH2 -- --
TIM5_UP TIM5_TRIG TIM5_TRIG

Ch7
USART3_T
-- TIM6_UP I2C2_RX I2C2_RX DAC1 DAC2 I2C2_TX
X

OR OR OR OR OR OR OR OR

High Priority Request Low Priority Request

DMA1
DMA2 Controller
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Ch0
TIM8_CH1/2 TIM1_CH1/2
ADC1 -- -- ADC1 -- --
/3 /3

Ch1 -- DCMI ADC2 ADC2 -- -- -- DCMI

Ch2
ADC3 ADC3 -- -- -- CRYP_OUT CRYP_IN HASH_IN

Ch3
SPI1_RX
SPI1_RX -- SPI1_TX -- SPI1_TX -- --

USART1_R USART1_R USART1_T

Ch4 -- -- SDIO -- SDIO
X X X

USART6_R USART6_R USART6_T USART6_T

Ch5 -- -- -- --
X X X X

Ch6 TIM1_CH4/_
TIM1_TRIG TIM1_CH1 TIM1_CH2 TIM1_CH1 TIM1_UP TIM1_CH3 --
TRIG/_COM

Ch7
TIM8_CH4/_
-- TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 -- --
TRIG/_COM

SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR

High Priority Request Low Priority Request

DMA2
Transfer size and Flow controller
 Either the DMA or the Peripheral determine the amount of data to transfer

 DMA is the flow controller: (to most applied)

 Number of data items to be transferred is determined by the DMA through the value
in register DMA_SxNDTR.
 DMA_SxNDTR register: from 1 to 65535 bytes/half-words/words and decrements
 Number of data items is relative only to Peripheral side
 in Memory-to-Memory mode, the source memory is considered as peripheral

 Peripheral is the flow controller: SDIO only

 The number of transfers is determined only by the peripheral.
 Used when the transfer size is unknown to the DMA
 When transfer is complete, the peripheral sends End of Transfer Signal to DMA
when number of transfers is reached.

 DMA_SxNDTR register can be read when transfer is ongoing to know the

remaining number of transfers.
FIFO: Data Packing/Unpacking
 When FIFO mode is enabled (direct mode disabled) the DMA manage the data format
difference between source and destination (data Packing and Unpacking).
 Supported operations:
 8-bit / 16-bit  32-bit / 16-bit (Packing)
 32-bit / 16-bit  8-bit / 16-bit (Unpacking)
 This feature allows to reduce software overhead and CPU load.

Data Packing Example (8-bit  32-bit) Data Unpacking Example (32-bit  16-bit)
T1

T1
A1 T1 A1 B1
T1 A1 B1 C1 D1
T2 A1 B1 C1 D1 A1 B1 C1 D1 A1 B1 C1 D1
B1 T2
C1 D1
A2 B2 C2 D2
T3 A2 B2 C2 D2 T2 A2 B2 C2 D2 T2 A2 B2 C2 D2
T3
C1 A2 B2
T4

D1 T4
C2 D2
T5

A2
T6 DMA FIFO DMA FIFO
B2
T7  Source data width = 8-bit  Source data width = 32-bit
 Destination data width = 32-bit  Destination data width = 16-bit
C2
 8 transfers are performed from source to DMA FIFO.  2 transfers are performed from source to DMA FIFO.
T8  2 transfers are performed from DMA FIFO to destination.  4 transfers are performed from DMA FIFO to destination.
D2
Circular & Double Buffer modes
 Circular mode:
 All FIFO features and DMA events (TC, HT, TE) are available in this mode.
 The number of data items is automatically reloaded and transfer restarted
 This mode is NOT available for Memory-to-Memory transfers .

 Double Buffer mode: (circular mode only)

 Two Memory address registers are available (DMA_SxM0AR & DMA_SxM1AR)
 Allows switch between two Memory buffers to be managed by hardware.
 Memory-to-Memory mode is not allowed
 A flag & control bit (CT) is available to monitor which destination is being used for data
transfer.
 TC flag is set when transfer to memory location 0 or 1 is complete.

DMA_SxM0AR

DMA_SxM1AR Memory location 1 Memory location 0

DMA_SxPAR
CT = 1
CT TC HT
CT = 0
Peripheral Data Register
RESET Sources
 System RESET VDD /VDDA
 Resets all registers except some RCC
registers and Backup domain RPU
Externa
 Sources l RESET Filter SYSTEM RESET
NRST
 Low level on the NRST pin WWDG
RESET
(External Reset) PULSE IWDG RESET
GENERATOR Software RESET POR/PDR
 WWDG end of count condition (min 20µs) Power RESET RESET
Low power
 IWDG end of count condition management RESET BOR
RESET
 A software reset (through NVIC)
 Low power management Reset

 Power RESET  Backup domain RESET

 Resets all registers except the Backup  Resets in the Backup domain: RTC registers +
domain Backup Registers + RCC BDCR register
 Sources  Sources
 Power On/Power down Reset  BDRST bit in RCC BDCR register
(POR/PDR)
 POWER Reset
 BOR
 Exit from STANDBY
Power Supply
 VDD = 1.8 V to 3.6 V. External Power Supply for I/Os and
VDDA domain
the internal regulator. The supply voltage can drop to 1.7
VREF- A/D converter
when the PDR_ON is connected to VSS and the device VREF+ D/A converter
Temp. sensor
VDDA
operates in the 0 to 70°C. Reset block
VSSA PLLs

 VDDA = 1.8 V to 3.6 V : External Analog Power supplies for

ADC, DAC, Reset blocks, RCs and PLLs.
PDR_ON Reset Controller
 VCAP = Voltage regulator external capacitors (also 1.2V
VDD domain VCore (1.2V)
domain
supply in Regulator bypass mode) FLASH Memory

 VBAT = 1.65 to 3.6 V: power supply for Backup domain I/O Rings

when VDD is not present. Core

VSS STANDBY circuitry Memories
(Wake-up logic,
 Power pins connection: IWDG)
Digital
VDD peripherals
 VDD and VDDA must be connected to the same power
source VCAP Voltage Regulator
Low voltage detector
 VSS, VSSA must be tight to ground Backup domain
 2.4V ≤ VREF+ ≤ VDDA when VDDA ≥ 2.4 VBAT
RTC and BKP reg
LSE crystal 32K osc
RCC BDCR
 VREF+ = VDDA when VDDA < 2.4 BKP SRAM
Voltage Regulators (1/2)
 2 voltage regulators are embedded
 A Main linear voltage regulator supplies all the digital circuitries
(except for the Standby circuitry and Backup domain). The regulator
output voltage (VCORE) is 1.2 V (typical) and can supply up to 200mA.
 Low voltage regulator exclusively for the backup RAM (in VBAT mode)

 The Main Voltage regulator has three different modes

 Run and Sleep modes (200mA max)
 Low power mode for STOP mode (5mA max)
 Regulator OFF in STANDBY/VBAT mode.

 Regulator bypass mode

 It allows to supply externally a 1.2 V voltage source through VCAP_1 and
VCAP_2 pins, in addition to a second external VDD supply source.
Voltage Regulators (2/2)

 In order to achieve a tradeoff between performance and power

consumption, „VOS‟ dedicated bit in „PWR_CR‟ register, allows to
controls the main internal voltage regulator output voltage

Condition Max AHB clock frequency

VOS bit in PWR_CR register equal to „0‟ 144 MHz
VOS bit in PWR_CR register equal to „1‟ 168 MHz

 The voltage scaling allows to optimize the power consumption when

the device is clocked below the maximum system frequency.
Voltage Regulator Bypass
 Available only on CSP64 and BGA176 packages.
 CSP by bonding option
 BGA dedicated pin “Bypass-Reg”

 Power consumption gains, but…

 Need to control the 1.2V logic circuitry “by hand”
 PA0 pin dedicated to reset the 1.2V logic.
 VDD should always be higher than VDD12
 If VDD12=1.08V supply slope faster than VDD=1.8V supply
 can just connect PA0 to NRST
 Otherwise reset sequence should be controlled externally
 PA0 should be asserted low until VDD12 =1.08V.
 Standby mode not allowed
Power supply monitoring POR, PDR, PVD
VDD
 Integrated POR / PDR circuitry:
 For devices operating from 1.8 to 3.6 V, VPOR POR
there is no BOR and the reset is released VPDR PDR
when VDD goes above POR level and
Temporization
asserted when VDD goes below PDR level tRSTTEMPO

 POR and PDR have 40mV hysteresis

Reset
 Programmable Voltage Detector
 Enabled by software
 Monitor the VDD power supply by comparing it to
a threshold VPDR = VPOR = 1.8V
 Threshold configurable from 1.9V to 3.1V by step VDD
of 100mV
 Generate interrupt through EXTI Line16 (if
enabled) when VDD < Threshold and/or VDD > PVD Threshold 100mV
hysteresis
Threshold.

Can be used to generate a warning message PVD

and/or put the MCU into a safe state Output
Brown Out Reset (BOR)
 During power on, the Brown out reset (BOR) keeps the device under
reset until the supply voltage reaches the specified VBOR threshold.
VDD
 No need for external reset circuit

 BOR have a typical hysteresis of 100mV VBORH VBORH

100mV hysteresis
VBORL VBORL

Temporization
tRSTTEMPO

Reset

 BOR Levels are configurable by option bytes:

 BOR OFF: 2.1 V at power on and 1.62 V at power down

 BOR LOW (DEFAULT) : 2.4 V at power on and 2.1 V at power down

 BOR MEDIUM: 2.7 V at power on and 2.4 V at power down

 BOR HIGH: 3.6 V at power on and 2.7 V at power down

Supply monitoring and Reset circuitry

At startup:

 POR/PDR - Always ON (or CSP64 bounding option)

 Brown Out Reset (BOR) - Always ON (can be switched off after
option byte loading)
 Programmable Voltage Detection (PVD) – ON/OFF.
 PVD enable/disable bit is controlled by software via a dedicated bit
(PVDE).
Backup Domain
 Backup Domain
 RTC unit and 4KB Backup RAM
 LVR for the backup RAM (with switch off option)
 VBAT independent voltage supply VBAT
power switch
Backup Domain

 Automatic switch-over to VBAT when VDD goes below PDR

level RCC BDCR 32KHz OSC
VDD reg (LSE)
 No current sunk on VBAT when VDD present
Wakeup
 Prevent from power line down Wakeup Pin 1
Logic
IWDG

 1 Wakeup pin and 2 RTC Alternate functions pins (RTC_AF1 and

RTC_AF2) RTC_AF1 RTC + 80 Bytes Data

 Backup SRAM RTC_AF2

 4 kB of backup SRAM accessible only from the CPU
 Can store sensitive data (crypto keys) Backup SRAM (4Kbytes)

 Backup SRAM is powered by a dedicated low power

regulator in VBAT mode. Its content is retained even in
Standby and VBAT mode when the low power backup
regulator is enabled.
 The backup SRAM is not mass erased by an tamper event.
STM32F4xx Low power modes features
 The STM32F4xx features 3 low power modes
 SLEEP (core stopped, peripherals running) ~2mA @2MHz (38mA @120MHz)
 STOP (clocks stopped, RAM, registers kept) ~1mA current consumption
 STANDBY (only backup domain kept, return via RESET)
 VBAT mode (like in STANDBY mode).

 The STM32F4xx features options to decrease the consumption during low

power modes
 Peripherals clock stopped automatically during sleep mode (S/W)
 Flash Power Down mode
 LVR and Backup RAM disable option

 The STM32F4xx features many sources to wakeup the system from

low power modes:
 Wakeup pin (PA0) / NRST pin
 RTC Alarm (Alarm A and Alarm B)
 RTC Wakeup Timer interrupt
 RTC Tamper events
 RTC Time Stamp Event
 IWDG Reset event
Wakeup time from Low Power Modes

Low power Conditions Wakeup

mode time in
µs
Sleep mode 1 Typ
Stop mode regulator in Run mode 13 Typ
Stop mode regulator in low power mode 17 Typ
Stop mode regulator in low power mode and Flash in Deep 110 Typ
power down mode
Standby mode 375 Typ
STM32F4 - clock features
Four oscillators on board
 HSE (High Speed External Osc) 4..26MHz (can be bypassed by and ext. Oscillator)
 HSI (High Speed Internal RC): factory trimmed internal RC oscillator 16MHz +/- 1
 LSI (Low Speed Internal RC): 32kHz internal RC used for IWDG, optionally RTC and AWU
 LSE (Low Speed External oscillator): 32.768kHz osc (can be bypassed by an external Osc)
 precise time base with very low power consumption (max 1µA).
 optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode.

Two PLLs
 Main PLL (PLL) clocked by HSI or HSE used to generate the System clock (up to 168MHz),
and 48 MHz clock for USB OTG FS, SDIO and RNG. PLL input clock in the range 1-2 MHz.
 PLLI2S PLL (PLLI2S) used to generate a clock to achieve HQ audio performance on the
I2S interface.

More security
 Clock Security System (CSS, enabled by software) to backup clock in case of HSE clock
failure (HSI feeds the system clock) – linked to Cortex NMI interrupt
 Spread Spectrum Clock Generation (SSCG, enabled by software) to reduce the spectral
density of the electromagnetic interference (EMI) generated by the device
STM32F4 - clock scheme
32.768KHz HSE
/2, to 31
OSC32_IN RTCCLK
LSE
OSC32_OUT OSc
LSI ~32KHz IWDGCLK
/8 SysTick

RC TIM5 IC4 HCLK up

16MHz
CSS to 168MHz

HSI RC PCLK1
up to 42MHz
HSI
4 -26 MHz
If (APB1 pres
OSC_OUT HSE /M HSE SYSCLK AHB Prescaler APB1
TIMxCLK
Prescaler =1) x1
/1,2…512 TIM2..7,12..14
OSC_IN Osc 168 MHz /1,2,4,8,16 Else x2
PLLCLK
max

PCLK2
up to 84MHz
VCO /P
APB2 If (APB2 pres =1)
PLL48CLK (USB FS, SDIO & RNG) TIMxCLK
Prescaler x1 Else
/Q TIM1,8..11
/1,2,4,8,16 x2
xN
/R

PLL VCO /P

/Q
HSI
xN
HSE PLLI2SCLK MACRXCLK
MCO1 /1..5 /R I2SCLK MACRMIICLK
PLLCLK
LSE MACTXCLK USB HS
PLLI2S
ULPI clock

SYSCLK
HSE

2, 20
MCO2 /1..5 PLLCLK

/
PLLI2S

Ext. Clock Ethernet USB2.0

I2S_CKIN PHY PHY
Watchdogs
 Independent Watchdog (IWDG)
VCORE voltage domain

 Dedicated low speed clock (LSI) Prescaler Status Reload Key

Register Register Register Register
 HW and SW way of enabling
 IWDG clock still active if main clock fails 12-bit
reload value
 Still functional in Stop/Standby LSI 8-bit
(38KHz) PRESCALER

 Wake-up from stop/standby 12-bit

down counter
IWDG
Reset
VDD voltage domain
 Min-max Timeout values 125us …32.7s

 Window Watchdog (WWDG) T[6:0] CNT down counter

 Configurable Time Window

 Can detect abnormally early or late W[6:0]

application behavior 3Fh

 Conditional Reset
Refresh Refresh time
 WWDG Reset flag not allowed Window
T6 bit
 Timeout value @42MHz (PCLK1): 97.52us Reset

… 49.93ms