Data Representation in

Computer Systems

• Fixed-Number (Integer) Arithmetic

• Floating-Points Representation
• Floating-Points Arithmetic
 Review Questions

2.1 Represent the following decimal numbers in both binary

sign/magnitude and two’s complement using 16-bits binary
system:

(a) +512 (b) –29

2.2 Represent the following two’s complement values in

decimal:

(a) 11010112 (b) 01011012

2.3 Convert the following 8-bit two’s complement value to 16-bits

binary system:

(a) 110011002 (b) 001011102

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.368.. 2
 Review Questions

2.4 Assume numbers are represented in 8-bits two’s

complement representation. Show the calculation of the
following:
(a) 6 + 13 (c) 6 – 13
(b) –6 + 13 (d) –6 – 13

2.5 Find the following differences using twos complement

arithmetic:

(a) 1110002 (b) 110011002 (c) 111100001111

– 1100112 – 1011102 – 1100 1111 0011

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.368. 3
Data Representation in
Computer Systems

• Fixed-Number (Integer) Arithmetic ❑ Multiplication

• Floating-Points Representation ❑ Division
• Floating-Points Arithmetic
A Multiplication Algorithm and Hardware

▪ Multiplication must cope with overflow because we frequently

want a 32-bit product as the result of multiplying two 32-bit
numbers.

▪ In the next slides, assume that we are multiplying only positive

number (unsigned) with the 1st version of highly optimized
multiplication hardware.

5
 32-bit multiplicand starts at right
half of multiplicand register

Multiplicand
Shift left
64 bits

Multiplier
64-bit ALU Shift right
32 bits

Product
Control test
Write
64 bits

Product register is initialized at 0

Figure: First version of Multiplication Hardware.

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.184. 6
 Start

Multiplier0 = 1 1. Test Multiplier0 = 0

Multiplier0

1a. Add multiplicand to product and

place the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

Figure:
The Multiplication Algorithm
using the Hardware. No: < 32 repetitions
32nd repetition?

Yes: 32 repetitions

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The
Done
Hardware/Software Interface (5th Edition). United States: Elsevier, p.185. 7
 Start

Example 14:
Multiplier0 = 1 1. Test Multiplier0 = 0
Using 4-bit numbers, Multiplier0

multiply of 210 x 310 .

Product (P) 1a. Add multiplicand to product and
2x3=? place the result in Product register

00102 x 00112
Multiplier (MP)

Multiplicand (MC) 2. Shift the Multiplicand register left 1 bit

Steps:
3. Shift the Multiplier register right 1 bit
1 – Test multiplier (0 or 1)
If 1 then 1a: P = P + MC
If 0 then no operation Max bit = Number of
2 – Shift MC left iteration.
32nd repetition?
No: < 32 repetitions

3 – Shift MP right f
All bits done? → Based on
Yes: 4-bits
32 repetitions
If still <max bit, repeat
If = max bit, stop
number system used.
Done
8
210 x 310 = _______10
Iteration Step Multiplier (MP) Multiplicand (MC) Product (P)

0 Initial value 0011 0000 0010 0000 0000

1a: P = P + MC 0000 0010
0011
1 2: Shift MC left 0000 0100
3: Shift MP right 0001
1a: P = P + MC 0000 0110
0001
2 2: Shift MC left 0000 1000
3: Shift MP right 0000
1: No Operation
0000 Answer:
3 2: Shift MC left 0001 0000 0000 0110
3: Shift MP right 0000 = 610
1: No Operation
0000
4 2: Shift MC left 0010 0000
9
3: Shift MP right 0000
Exercise 2.2:

In 4-bit binary arithmetic, find the multiplication of 510 with 410 using
the 1st version of highly optimized multiplication hardware.

10
Solution 2.2:
Iteration Step Multiplier (MP) Multiplicand (MC) Product (P)
0 Initial value

1 2: Shift MC left
3: Shift MP right

2 2: Shift MC left
3: Shift MP right

3 2: Shift MC left
3: Shift MP right

4 2: Shift MC left
3: Shift MP right
11
 Aside:

◼ The multiplier (MP) must always in positive number.

◼ Do an additive inverse to the multiplicand (MC) and the MP.

◼ Examples:

Linda Null and Julia Lobur (2003). The Essentials of Computer Organization and Architecture. United States: Jones and Bartlett Publishers. p.53. 12
Example 15:

Using a 4-bit binary arithmetic, multiply 210 with (–310) using the 1st
version of highly optimized multiplication hardware.

Solution:

→
▪ Do an additive inverse to the multiplicand (MC) and the MP:

▪ Perform the multiplication as usual.

13
(- 210) x 310 = _______10
Iteration Step Multiplier (MP) Multiplicand (MC) Product (P)

0 Initial value 0011 1111 1110 0000 0000

1 2: Shift MC left

3: Shift MP right

2 2: Shift MC left

3: Shift MP right

3 2: Shift MC left

3: Shift MP right

4 2: Shift MC left
14
3: Shift MP right
Exercise 2.3:

In 6-bit binary arithmetic, find the multiplication of 2110 with 1410

using the 1st version of highly optimized multiplication hardware.

15
Solution 2.3:
Iteration Step Multiplier (MP) Multiplicand (MC) Product (P)
0 Initial value 001110 0000 0001 0101 0000 0000 0000

1 2: Shift MC left
3: Shift MP right

2 2: Shift MC left
3: Shift MP right

3 2: Shift MC left
3: Shift MP right

4 2: Shift MC left
3: Shift MP right
16
Iteration Step Multiplier (MP) Multiplicand (MC) Product (P)

2: Shift MC left
5
3: Shift MP right

2: Shift MC left
6
3: Shift MP right

17
 (d) Division

◼ More complex than multiplication but is based on the same

general principles.
◼ An operation that is even less frequent and even more quickly.
◼ It even offers the opportunity to perform a mathematically
invalid operations in dividing by 0.

◼ Two operands called Quotient

dividend and divisor, the Divisor Dividend .
result as quotient with ...
secondary result called ... .
remainder. Remainder

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.360. 18
 ◼ Another way to express the relationship between the
components:

where the remainder is smaller than the divisor.

◼ Infrequently, programs use the divide instruction just to get the

remainder, ignoring the quotient.

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.193. 19
 (d) Division
Unsigned Integer

◼ The following figure shows an example of the long division of

unsigned binary integers of 14710 divided by 1110.

(13)
(11) (147)

(4)
William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.348. 20
 (d) Division
Signed Integer: Two’s Complement

◼ Make both dividend and divisor positive and perform division.

◼ Make the sign of the remainder match to the dividend, no
matter what the signs of the divisor and quotient.

◼ The rules:

◼ Negate the quotient if dividend and divisor were of opposite

signs.
Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.193. 21
A Division Algorithm and Hardware

▪ Binary division is restricted to 0 or 1, thereby simplifying binary

division.

▪ In the next slides, assume that both the dividend and divisor
are positive number; Hence the quotient and remainder are
non-negative.

▪ Since iteration of the algorithm needs to move the divisor to

the right one digit, we start the divisor placed in the left half of
the 64-bit Divisor Register.

23
 32-bit divisor starts at left half of divisor register

Divisor
Shift right Quotient register is
initialized to be 0
64 bits

Quotient
64-bit ALU Shift left
32 bits

Remainder Control
Write test
64 bits

Remainder register is initialized with the dividend at right

Figure: First version of Division Hardware.

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.190. 24
 Start

1. Subtract the Divisor register from the

Remainder register and place the
result in the Remainder register

Remainder –> 0 Remainder < 0

Test Remainder

2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
setting the new rightmost bit to 1 the Divisor register to the Remainder
register and place the sum in the
Remainder register. Also shift the
Quotient register to the left, setting the
new least significant bit to 0

Figure: 3. Shift the Divisor register right 1 bit

The Division Algorithm
using the Hardware.
No: < 33 repetitions
33rd repetition?

Yes: 33 repetitions

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Done
Hardware/Software Interface (5th Edition). United States: Elsevier, p.191. 25
 Start

Example 16: 1. Subtract the Divisor register from the

Remainder register and place the
result in the Remainder register
Using 4-bit numbers,
divide 710 by 210 .
Remainder –> 0 Remainder < 0
Test Remainder
Quotient (Q)
7/2=?
01112 / 00102
2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
setting the new rightmost bit to 1 the Divisor register to the Remainder
register and place the sum in the
Remainder register. Also shift the
Dividend (DD) Divisor (D) Quotient register to the left, setting the
new least significant bit to 0

Steps:
1 – Remainder (R) = R – D
2 – test new R 3. Shift the Divisor register right 1 bit
Max bit + 1 =
2a - If >=0 then Shift left Q (add 1 at LSB)
2b - If <0 then R = D + R, Shift left Q (add 0 at LSB) Number of iteration.
3 – shift D right 33rd repetition? f
No: < 33 repetitions

All bits done? → Based on 4-bits

Yes: 33 repetitions
If still <(max bit + 1), repeat number system used
If = (max bit + 1), stop Done
26
 Divisor start at left half
7 / 2 = ____ of divisor register !

Quotient
Iteration Steps (Q) Divisor (D) Remainder (R)
0 Initial value 0000 0010 0000 0000 0111
1 :R=R–D 1110 0111
1

3 : D = Shift right
R=R–D
1 :R=R–D
= R + (–D)
2
0000 0111 (7)
3 : D = Shift right
+ 1110 0000 (2’s for D)
1 :R=R–D
1110 0111
3

3 : D = Shift right
27
 Divisor start at left half
7 / 2 = ____ of divisor register !

Quotient
Iteration Steps (Q) Divisor (D) Remainder (R)
0 Initial value 0000 0010 0000 0000 0111
1 :R=R–D 1110 0111
2b: R < 0; R = D+R 0000 0111
1
Q : Shift Left (+0) 0000
3 : D = Shift right 0001 0000
1 :R=R–D 1111 0111
2b: R < 0; R = D+R 0000 0111
2
Q : Shift Left (+0) 0000
3 : D = Shift right 0000 1000
1 :R=R–D 1111 1111
2b: R < 0; R = D+R 0000 0111
3 Q : Shift Left (+0) 0000
3 : D = Shift right 0000 0100
28
Try to complete the table for the remaining iterations:
R = 0000 01112; Q = 00002; D = 0000 01002

Quotient
Iteration Steps (Q) Divisor (D) Remainder (R)
1 :R=R–D 0000 0011
2a: No Operation
4
Q : Shift Left (+1) 0001
3 : D = Shift right 0000 0010
1 :R=R–D 0000 0001
2a: No Operation
5
Q : Shift Left (+1) 0011
3 : D = Shift right 0000 0001

Answer: 7 / 2 = 3 remainder 1
29
Exercise 2.5:

Using a 4-bit binary arithmetic, find the division of (–710) by 210 with
the 1st version of highly optimized division hardware.

30
Exercise 2.6:

Using a 4-bit binary arithmetic, find the division of the following

numbers with the 1st version of highly optimized division hardware.
a) 610 by 310
b) 610 by (– 310)
c) (–1210) by 510

31
Data Representation in
Computer Systems

• Fixed-Number (Integer) Arithmetic

• Floating-Points Representation ❑ The IEEE-754 Floating-Point
• Floating-Points Arithmetic Standard
2.4 Floating-Point Representation

◼ The signed magnitude, one’s complement, and two’s

complement representation that we have just presented deal
with integer values only.
◼ Without modification, these formats are not useful in scientific
or business applications that deal with real number values.
◼ Floating-point representation solves this problem.
◼ Known as reals in mathematics.

33
 The IEEE-754 Floating-point Standard
(IEEE) Institute of Electrical and Electronic Engineers

◼ The floating-point model (non-standard) described before is for

simplicity and conceptual understanding.
◼ This standard is officially known as IEEE-754 (1985):

Floating-points

Single Precision Double Precision

(32 bits) (64 bits)

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.331. 34
 MIPS (Millions of Instructions Per Second)

Overview

◼ Floating-point → Computer arithmetic that represents numbers

in which the binary point is not fixed:

◼ A standard scientific notation for reals in normalized form.

◼ General form:

where S = Sign, e’ = Normalized exponent.

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.197. 35
 MIPS (Millions of Instructions Per Second)

(a) Single Precision

◼ The representation of a MIPS 32-bit floating-point number:

◼ The sizes of exponent and fraction give MIPS computer

arithmetic an extraordinary range:
o Smallest fraction:
o Largest number:

◼ This is called single-precision = 1 word.

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.198. 36
 ◼ Unfortunately, single precision floating-point still possible for
numbers to be too large:

o Overflow → the exponent is too large.

o Underflow → the negative exponent is too large.

◼ Solution:

One way to reduce these problems, need another format that

has larger exponent → Double precision floating-point.

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.198. 37
 (b) Double Precision

◼ The representation of a double precision floating-point number

takes two MIPS words → 64 bits.

o Smallest fraction:
o Largest number:

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.198. 38
 The IEEE-754 Floating-point Standard
Representation

◼ This standard has greatly improved both the ease of porting

floating-point programs and the quality of computer arithmetic.
◼ To pack even more bits into the significand, IEEE 754 makes the
leading 1-bit of normalized binary numbers implicit.

◼ Significant : 1 + fraction

o Single precision : 24 bits

0 has no leading 1, it
o Double precision : 53 bits is given the reserved
exponent value 0.
Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.198. 39
 ◼ The representation of normalized floating-point in IEEE
standard:

Sign (S): plus (0) or minus (1)

Normalized exponent (e’)

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.199. 40
 The IEEE-754 Floating-point Standard
Normalized & Unnormalized

◼ In IEEE standard normalization (used in computers), a floating

point number is said to be normalized if there is only a single
non-zero before the radix point.

◼ Examples:

41
Exercise 2.11:

Complete the table with the normalized binary number and its
exponent respectively using single precision floating-point.

Binary Values Normalized as Exponent (e’)

(a) 1101.101
(b) 0.00101
(c) 1.0001
(d) 10000011.0

42
Biased Notation

◼ Placing the exponent before the fraction simplifies sorting of

floating-point numbers using integer comparison instructions.
◼ However, using 2’s complement in the exponent field makes a
negative exponent look like a big number.

◼ Example: IEEE-754 Single Precision (32 bits)

1.02 x 2–1
Problem: e’ = –1

1 bit 8 bits 23 bits

0 11111111 00000000000000000000000
Sign Exponent significand / fraction
43
 Bias values, B = (2n – 1) – 1 :

Sign (S): plus (0) or minus (1) → In single precision is 127

Biased Exponent (EB)
→ In double precision is 1023
Bit of Exponent (n)

EB = e’ + Bias
◼ Example: = (–1) + 127
= 12610 = 01111 11102
1.02 x 2–1

1 bit 8 bits 23 bits

0 01 1 1 1 1 1 1 01 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign Biased
Exponent
Exponent significand / fraction
44
 / Single-Precision / Single word

/ Double-Precision / Double words

Figure: IEEE-754 floating-point format.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.331. 45
Exercise 2.12:

Complete the table with the biased exponent (EB) and binary
representation for each number using the type of floating-point
respectively.

Exponent (e’) Biased Exponent (EB)

Single Precision Double Precision
(Dec) (Bin) (Dec) (Bin)
(a) 3
(b) –3
(c) 0
(d) 7
46
 The IEEE-754 Floating-point Standard
Conversion of Decimal to Binary Floating-point

◼ To convert a decimal number to single or double precision

floating point:

o Step 1: Normalized.

o Step 2: Determine sign bit.

o Step 3: Determine biased exponent.

o Step 4: Determine significand (fraction)

47
Example 20:

Convert 10.410 to single precision floating-point.

◼ Step 1: Normalized from the bit value.

1010 → 10102 10.410 = 1010.01102 x 20

= 1.01001102 x 20+3
0.4 x 2 = 0.8
0.8 x 2 = 1.6 = 1.01001102 x 23
0.6 x 2 = 1.2
0.2 x 2 = 0.4
.....
(Repetitive Multiplication)

◼ Step 2: Determine sign bit (S). →S=0

48
 EB = e’ + bias
◼ Step 3: Determine the biased = 3 + 127
exponent, EB → = 13010 = 1000 00102

◼ Step 4: Determine fraction.

❑ Drop the leading 1 of the fraction;
1.01001102 x 210000010 → 0100110
❑ Expand (padding) to 23 bits; = 1.01001102 x 20+3
01001100000000000000000
= 1.01001102 x 23
❑ Complete the representation;
1 bit 8 bits 23 bits

0 10000010 01001100000000000000000
Sign Biased Exponent significand / fraction
49
Exercise 2.13:

Convert (– 0.7510) to single precision floating-point.

1 bit 8 bits 23 bits

0 01111110 10000000000000000000000
Sign Biased Exponent significand / fraction

50
Exercise 2.14:

Convert the following number to single precision floating-point.

(a) (– 33.62510)
(b) 0.0312510

51
 Exercise 2.15:

Complete the table with all sign (S), exponent (e’) and fraction (F)
values if single precision floating-point applied.
(Decimal) (Binary)

Binary Values EB S EB Fraction

(a) -1.11
(b) +1101.101
(c) -0.00101
(d) +100111.0
(e) +0.0000001101011

52
Exercise 2.16:

Convert the following number to double precision floating-point.

(a) (– 0.7510)
(b) 10.410

53
 The IEEE-754 Floating-point Standard
Conversion of Binary Floating-point to Decimal

◼ To convert a single or double precision floating point to decimal

number:

o Step 1: Extract value of sign.

o Step 2: Extract value of biased exponent & bias value.

o Step 3: Extract value of fraction.

o Step 4: Apply the basic equation.

54
 Example 21:

What is the decimal number represented by this single precision

float?

1 bit 8 bits 23 bits

1 10000001 01000000000000000000000

Solution:

◼ Step 1: Extract value of sign. →S=1

◼ Step 2: Extract value of biased exponent, EB → 10000001 = 12910

Bias value, B → (2n – 1 – 1) = 27 – 1 = 128 – 1 = 12710
Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.202. 55
 S=1
→ 01 x 20 Fraction = 0.25
→ 0.1 x 2–1 EB = 129
→ 1.0 x 2–2 B = 127

◼ Step 3: Extract value of fraction. → 1 x 2–2

◼ Step 4: Apply the basic equation.

= (– 1)1 x (1 + 0.25) x 2129 –127 EB = e’ + bias

→ e’ = EB – B
= (– 1) x (1.25) x 22
= (– 1.25) x 4
= – 5.010
Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.202. 56
Exercise 2.17:

What is the decimal number represented by this double

precision float?

1 bit 11 bits 52 bits

0 01111111110 00100000000000000...0

57
Data Representation in
Computer Systems

• Fixed-Number (Integer) Arithmetic

• Floating-Points Representation
• Floating-Points Arithmetic ❑ Addition
❑ Multiplication
 2.5 Floating-Point Arithmetic
Overview

◼ For addition and subtraction, it is necessary to ensure that both

operands have the same exponent value.
◼ This may require shifting the radix point on one of the operands
to achieve alignment.
◼ Multiplication and division are more straightforward.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.334. 59
 Addition
Flows

Biased Exponent ranges:

Single precision: -126 ~ 127
Double precision: - 1022 ~ 1023

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The
Hardware/Software Interface (5th Edition). United States: Elsevier, p.205. 60
◼ Assume 4 decimal digits for fraction and 2 decimal digits for
exponent.

o Step 1: Align the decimal point of the number that has

the smaller exponent.
o Step 2: Add the fraction.
o Step 3: Normalize the sum.
o Step 4: Round the fraction.
(If the fraction does not fit in the space reserved for it,
it has to be rounded off)
o Step 5: Normalize it (if need be) .

61
 Add these two decimal floating-point
numbers. Assume that we can store only
four decimal digits of the significand and
Example 22:
two decimal digits of the exponent.

(9.99910 x 101) + (1.61010 x 10–1) = _____10

Solution:
◼ Step 1: Align the decimal ◼ Step 2: Add the fraction.
point of the number that has
the smaller exponent.
9.9990 x 101
1.61010 x 10–1
+ 0.0161 x 101
= 1.61010 x 10–1 x 102
10.0151 x 101
= 0.016110 x 101

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.203. 62
 ◼ Step 3: Normalize the sum.
10.0151 x 101 → 1.00151 x 102

◼ Step 4: Round the fraction (to 4 decimal digits for fraction).

1.00151 x 102 → 1.0015 x 102

◼ Step 5: Normalize it (if need be).

No need as its normalized

Answer = 1.0015 x 102

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.203. 63
 Example 23:

Add these two binary floating-point numbers.

0.510 + (– 0.437510) = _____ 2

Solution: (Convert to binary)

0.5 x 2 = 1.0 0.4375 x 2 = 0.875

0.875 x 2 = 1.75
0.75 x 2 = 1.5
0.5 x 2 = 1.0

(– 0.01112 x 20)x 2– 2
(0.12 x 20) x 2– 1

(1.02 x 2–1) + (– 1.112 x 2–2)

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.204. 64
 ◼ Step 1: Align the decimal ◼ Step 3: Normalize the sum.
point of the number that has
the smaller exponent. 0.001 x 2–1 x 2–3 → 1.0 x 2–4
– 1.112 x 2–2
= – 1.112 x 2–2 x 21
◼ Step 4: Round the fraction
= – 0.1112 x 2–1 (to 4 decimal digits for
fraction).
◼ Step 2: Add the fraction.
1.0 x 2–4 → 1.0000 x 2–4
1.000 x 2–1
+ – 0.111 x 2–1
0.001 x 2–1

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.204. 65
 ◼ Step 5: Normalize it (if need be).

No need as its normalized Answer = 1.0000 x 2–4

This sum in decimal is then:

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The Hardware/Software Interface (5 th Edition). United States: Elsevier, p.204. 66
Exercise 2.18:

Add these two binary floating-point numbers.

0.601562510 + 0.7812510 = _____ 2

67
Exercise 2.19:

Add the following binary numbers as represented in a

normalized single precision format.

1 1 1 1 0 1 0 1 0 0 ….. 0 0 0

0 1 0 1 0 0 1 1 0 0 ….. 0 0 0

68
 Multiplication
Flows

Patterson, D.A. and Hennessy, J.L. (2014). Computer Organization and Design: The
Hardware/Software Interface (5th Edition). United States: Elsevier, p.209. 69
◼ Assume 4 decimal digits for fraction and 2 decimal digits for
exponent.

o Step 1: Add the exponent of the 2 numbers.

o Step 2: Multiply the fraction.
o Step 3: Normalize the product.
o Step 4: Round the fraction.
(If the fraction does not fit in the space reserved for it,
it has to be rounded off)
o Step 5: Normalize it (if need be) .
o Step 6: Set the sign of the product.

70
Example 24:

Multiply these two decimal floating-point numbers.

Assume 4 decimal digits for significand and 2 decimal digits for
exponent.
= _____10

Solution:

◼ Step 1: Add the exponent of ◼ Step 2: Multiply the fraction.

the 2 numbers. 9.200
10 + (–5) = 5 x 1.110
0 000
If bias considered → 92 00 → 10.212000
920 0 = 10.2120 x 105
5 + 127 = 132 9200 .

10212000
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◼ Step 3: Normalize the product.
10.2120 x 105 x 101 → 1.02120 x 106

◼ Step 4: Round the fraction (to 4 decimal digits for fraction).

1.02120 x 106 → 1.0212 x 106

◼ Step 5: Normalize it (if need be).

No need as its normalized

◼ Step 6: Set the sign of the product.

+1.0212 x 106

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Example 25:

Multiply these two binary floating-point numbers.

Assume 4 binary digits for significand and 2 binary digits for
exponent.
= _____ 2

Solution:

◼ Step 1: Add the exponent of ◼ Step 2: Multiply the fraction.

the 2 numbers. 1.110
(–1) + (–2) = –3 x 1.000
0 000
If bias considered → 00 00 → 1.110000
000 0 = 1.110000 x 2–3
(–3) + 127 = 124 1110 .

1110000
73
◼ Step 3: Normalize the product.

Already normalized

◼ Step 4: Round the fraction (to 4 decimal digits for fraction).

1.110000 x 2–3 → 1.1100 x 2–3

◼ Step 5: Normalize it (if need be).

No need as its normalized

◼ Step 6: Set the sign of the product.

–1.1100 x 2–3
Exercise 2.20:

Given two numbers 0.510 and –0.437510.

(a) Multiply the numbers.
(b) Converting to decimal to check the results.
Show your workings.

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 2.6 Summary

◼ This module presented the essentials of data representation

and numerical operations in digital computers.
◼ Student should master the techniques described for base
conversion and memorize the smaller hexadecimal and binary
numbers.
◼ This knowledge will be beneficial to student throughout
remainder of this subject.
◼ Knowledge of hexadecimal coding will be useful if you are ever
required to read a core (memory) dump after a system crash or
if do any serious work in the field of data communications.

Linda Null and Julia Lobur (2003). The Essentials of Computer Organization and Architecture. United States: Jones and Bartlett Publishers. p.83. 76