Very large scale integration(VLSI) Manual Fall 2021

LAB-2 (Tutorial)
IMPLEMENTATION OF MOORE AND MELAY
FSM MACHINE

Engineer. Ali Sabir

Engineer. Hamza Atiq
Prof. Rashad M. Ramzan Dr. Hassan Saif

Electrical Engineering Department

National University of Computer &
Emerging Sciences (FAST-NU)
Islamabad-44000, Pakistan
M USMAN KIANI
18i-0807
Bs EE

2.1 AIM
This lab session will deal with the construction of synchronous sequential circuits using Hardware
Description Language (HDL) and Xilinx ISE 14.2i to analyse its behaviour. Sequential circuits are often
used to control the operation of physical systems. We will introduce the techniques for designing such
circuits by means of a simple example and will also learn to write he HDL code for the given example.

2.2 OBJECTIVE
After completing this lab, you will be able to:
• Design a Moore and Melay FSM machine.
• Analyze the Sequential behavior of digital circuits.
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Very large scale integration(VLSI) Manual Fall 2021

• Learn the complete procedure to design any synchronous sequential circuit

• Verilog specification of sequential circuits

2.3 Theory

2.3.1 Introduction
The general class of circuits in which the outputs depend on the past behaviour of the circuit, as well as on
the present values of inputs. They are called sequential circuits. In most cases a clock signal is used to control
the operation of a sequential circuit; such a circuit is called a synchronous sequential circuit. The alternative,
in which no clock signal is used, is called an asynchronous sequential circuit. Synchronous circuits are easier
to design and are used in a vast majority of practical applications.
Synchronous sequential circuits are realized using combinational logic and one or more flip-flops. The
general structure of such a circuit is shown in Figure 8.1. The circuit has a set of primary inputs, W, and
produces a set of outputs, Z. The stored values in the flip-flops are referred to as the state, Q, of the circuit.
Under control of the clock signal, the flip-flops change their state as determined by the combinational logic
that feeds the inputs of these flip-flops. Thus the circuit moves from one state to another. To ensure that only
one transition from one state to another takes place during one clock cycle, the flip-flops have to be of the
edge-triggered type. They can be triggered either by the positive (0 to 1 transition) or by the negative (1 to 0
transition) edge of the clock. We will use the term active clock edge to refer to the clock edge that causes the
change in state.
The combinational logic that provides the input signals to the flip-flops has two sources: the primary
inputs, W, and the present (current) state of the flip-flops, Q. Thus changes in state depend on both the
present state and the values of the primary inputs.
Figure 2.1 indicates that the outputs of the sequential circuit are generated by another combinational circuit,
such that the outputs are a function of the present state of the flip-flops and of the primary inputs.

Although the outputs always depend on the present state, they do not necessarily have to depend directly on
the primary inputs. Thus the connection shown in blue in the figure may or may not exist. To distinguish
between these two possibilities, it is customary to say that sequential circuits whose outputs depend only on
the state of the circuit are of Moore type, while those whose outputs depend on both the state and the primary
inputs are of Mealy type. These names are in honour of Edward Moore and George Mealy, who investigated
the behaviour of such circuits in the 1950s.

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Fig 2.1 Block diagram of Melay Machine

Fig 2.2 Block diagram of Moore Machine

2.3.2 SPECIFICATION of the FSM MACHINE

Consider an application where the speed of an automatically-controlled vehicle has to be regulated as

follows. The vehicle is designed to run at some predetermined speed.
However, due to some operational conditions the speed may exceed the desirable limit, in which case the
vehicle has to be slowed down. To determine when such action is needed, the speed is measured at regular
intervals. Let a binary signal w indicate whether the speed exceeds the required limit, such that w = 0 means
that the speed is within acceptable range and w = 1 indicates excessive speed. The desired control strategy is
that if w = 1 during two or more consecutive measurements, a control signal z must be asserted to cause the
vehicle to slow down.
Thus, z = 0 allows the current speed to be maintained, while z = 1 reduces the speed. Let a signal Clock
define the required timing intervals, such that the speed is measured once during each clock cycle. Therefore,
we wish to design a circuit that meets the following specification:

1. The circuit has one input, w, and one output, z.

2. All changes in the circuit occur on the positive edge of the clock signal.
3. The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1.
Otherwise, the value of z is equal to 0.

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2.3.3 Moore State Diagram

The first step in designing a finite state machine is to determine how many states are needed and which
transitions are possible from one state to another. There is no set procedure for this task.
Figure 2.2 below shows the possible state diagram of the circuit

Figure 2.2 Moore FSM state transition diagram

2.3.4 State assignment table

The state table in Figure 2.1 defines the three states in terms of letters A, B, and When implemented in a
logic circuit, each state is represented by a particular valuation (combi-nation of values) of state variables.
Each state variable may be implemented in the form of a flip-flop. Since three states have to be realized, it is
sufficient to use two state variables. Let these variables be y1 and y2.

Table 2.1 State table for Moore FSM

2.3.4 Derivation of next state and out-put expression

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Very large scale integration(VLSI) Manual Fall 2021

(a) (b)

Figure 2.3 (a) Karnaugh-map Plot, (b) Boolean equations

2.3.5 Implementation of fsm machine

Figure 2.4 Circuit Implementation

2.3.6 Melay State Diagram
The first step in designing a finite state machine is to determine how many states are needed and
which transitions are possible from one state to another. There is no set procedure for this task.
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Very large scale integration(VLSI) Manual Fall 2021

Figure 2.2 Melay FSM state transition diagram

Only two states are needed because we have allowed the output value to depend on the present value
of the input as well as the present state of the machine. The diagram indicates that if the machine is
in state A, it will remain in state A if w = 0 and the output will be 0. This is indicated by an arc with
the label w = 0/z = 0. When w becomes 1, the output stays at 0 until the machine moves to state B at
the next active clock edge. This is denoted by the arc from A to B with the label w = 1/z = 0. In state
B the output will be 1 if w = 1, and the machine will remain in state B, as indicated by the label w =
1/z = 1 on the corresponding arc. However, if w = 0 in state B, then the output will be 0 and a
transition to state A will take place.

The state table in Figure 9.3 defines the 2 states in terms of letters A and B. When implemented in a
logic circuit, each state is represented by a particular valuation (combination of values) of state
variables. Each state variable may be implemented in the form of a flip-flop. Since two states have
to be realized, it is sufficient to use 1 state variables. Let these variables be y .

Table 2.2 State table for Melay FSM

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Very large scale integration(VLSI) Manual Fall 2021

2.3.7 Implementation of Melay FSM Machine

Figure 2.2 Melay FSM Circuit Diagram

PRE-LAB:

1. How would you decide the no of flip-flops needed to implement the machine?

Answer
2. Do we have choices of selecting different types of flip-flops?

Answer

3. Why would we do with the don’t care states?

Answer

2.5 SOFTWARE tools Requirement

Equipment:
Computer with ISE 14.7 Software Specifications:
 HP Computer i7 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk 
Software: ISE

2.6 Procedure:
1. Double click the project navigator and select the option File-New project.
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Very large scale integration(VLSI) Manual Fall 2021

2. Give the project name.

3. Select Verilog module.
4. Type your Verilog coding.(described in sec 8.6 )
5. Check for syntax.
6. Choose behavioral simulation and simulate it by Xilinx ISE simulator.
7. Synthesize your design..
8. Write a test bench and observe the waveform .
IN-LAB TASK
2.7.1 Verilog Code

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2.7.2 Test Fixture

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Very large scale integration(VLSI) Manual Fall 2021

2.7.3 ISM Result

1. Write verilog code for Moore FSM which will detect the code 010 in order to unlock the
door.

Verilog Code

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Very large scale integration(VLSI) Manual Fall 2021

Test Bench

Waveform

2. Simulate the above code and verify your truth table by giving different inputs

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Very large scale integration(VLSI) Manual Fall 2021

Verilog Code

Test Bench

Waveform

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Very large scale integration(VLSI) Manual Fall 2021

POST LAB TASK

1. Convert the last two digit of your number into binary(e.g. Roll number= xyz15, 15=1101,
output would be one when your system detect the sequence 1101) that will be your sequence
otherwise your output will be zero. Draw the state transition diagram of Moore FSM and write
their verilog also create their testbench in order to verify their functionality and show the
waveform with explanation.

Moore State machine

Verilog code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:59:53 11/05/2021
// Design Name:
// Module Name: mooremachine
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
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Very large scale integration(VLSI) Manual Fall 2021

//
//////////////////////////////////////////////////////////////////////////////////
module mooremachine( clk, reset, seq_in, detector_out );

input clk;
input reset;
input seq_in;
output reg detector_out;

parameter s0= 2'b00, s1= 2'b01, s2= 2'b11, s3= 2'b10;

reg [2:0] current_state, next_state;

always @(posedge clk, posedge reset)

begin
if(reset == 1)
current_state <= s0;
else
current_state <= next_state;
end

always @(current_state, seq_in)

begin
case(current_state)

s0: begin
if (seq_in == 1)
next_state = s1;
else
next_state = s0;
end

s1: begin
if (seq_in == 1)
next_state = s2;
else
next_state = s0;
end

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s2: begin
if (seq_in == 1)
next_state = s3;
else
next_state = s0;
end

s3: begin
if (seq_in == 1)
next_state = s1;
else
next_state = s0;
end

default: next_state = s0;

endcase
end

always @(current_state)
begin
case(current_state)
s0 : detector_out = 0;
s1 : detector_out = 0;
s2 : detector_out = 0;
s3 : detector_out = 1;

default : detector_out = 0;
endcase
end

endmodule

Test Bench
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`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:01:45 11/05/2021
// Design Name: mooremachine
// Module Name: C:/Users/ICD_Lab/newmoore/mooretestbench.v
// Project Name: newmoore
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mooremachine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module mooretestbench;

// Inputs
reg clk;
reg reset;
reg seq_in;

// Outputs
wire detector_out;

// Instantiate the Unit Under Test (UUT)

mooremachine uut (
.clk(clk),
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.reset(reset),
.seq_in(seq_in),
.detector_out(detector_out)
);

initial begin
clk = 0;
forever #5 clk = ~clk;

end

initial begin
seq_in = 0;
reset = 1;

#30
reset = 0;
#40

seq_in = 1;
#10
seq_in = 1;
#10
seq_in = 1;

end

endmodule

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Very large scale integration(VLSI) Manual Fall 2021

Plot

2. Smiling Snail:
Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail
smiles whenever the last four digits it has crawled over are 1101. Draw the state transition
diagram, Draw the state transition diagram of Melay FSM and write their verilog also create
their testbench in order to verify their functionality and show the waveform with
explanation.

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Very large scale integration(VLSI) Manual Fall 2021

MELAY MACHINE

VERILOG CODE

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:25:59 11/07/2021
// Design Name:
// Module Name: Melaymachine
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Melaymachine(
input clk,
input reset,
input in,
output reg out

);
reg[1:0] state;
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Very large scale integration(VLSI) Manual Fall 2021

parameter s0 = 2'd0, s1 = 2'd1, s2 = 2'd2, s3 = 2'd3;

always @(posedge clk or negedge reset)

if (reset == 0) begin state = s0; out = 0;
end
else begin
case (state)
s0: if(in == 0) begin out = 0 ; state = s0;
end
else begin out = 0 ; state = s1;
end

s1: if(in == 0) begin out = 0 ; state = s0;

end
else begin out = 0 ; state = s2;
end

s2: if(in == 0) begin out = 0 ; state = s3;

end
else begin out = 0 ; state = s2;
end

s3: if(in == 0) begin out = 0 ; state = s0;

end
else begin out = 1 ; state = s1;
end

default : state = s0 ;
endcase
end
endmodule

TESTBENCH

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:56:33 11/07/2021
// Design Name: Melaymachine
// Module Name: C:/Users/ICD_Lab/melay/TestMELAY.v
// Project Name: melay
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Melaymachine
//
// Dependencies:
//
// Revision:
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Very large scale integration(VLSI) Manual Fall 2021

// Revision 0.01 - File Created

// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module TestMELAY;

// Inputs
reg clk;
reg reset;
reg in;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

Melaymachine uut (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);

initial begin
// Initialize Inputs
clk = 0;
forever #5 clk = ~clk;
end

initial begin
reset = 0;
in = 0;

// Wait 100 ns for global reset to finish

#20;

reset = 1;
#20
in = 1;
#10
in = 1;
#10
in = 0;
#10
in = 1;

// Add stimulus here

end

endmodule

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PLOT

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