Verilog

1. Explain what is Slack?

2. Explain what is the use of defparam?
3. How to find out longest path?
4. What are the different types of skews used?
5. What is front end and back end design?
6. What is the full form of RTL?
7. What is the difference between RTL and HDL?
8. Draw the state diagram to detect a sequence?
9. Draw the state diagram of a traffic light controller?
10. What is the difference between Big Endean format and Little Endean format?
11. What do you mean by concurrent statement?
12. Define component instantiation?
13. What is the difference between variable and signal?
14. List some sequential statements?
15. Define a test bench?
16. What are the advantages of test benches?
17. What is the difference between behavioral simulation and timing simulation?
18. Does frequency of operation depend on critical path in a circuit? Justify?
19. What are different types of scaling? Which one is used and why?
20. What are the different design styles in VLSI?
21. What is entry delay and exit delay?
22. What is the difference between testing and verification?
23. What are set up time & hold time constraints? What do they signify?
24. Which timing constraint is critical for estimating maximum clock frequency of a circuit?
25. What’s the critical path in a circuit?
26. How to implement Half-adder and full-adder in RTL?
27. What is the significance of FPGA in modern day electronics?
28. What is LUT?
29. What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
30. What is the significance of contamination delay in sequential circuit timing?
31. What do conditional assignments get inferred into?
32. What logic is inferred when there are multiple assign statements targeting the same wire?
33. What is slice? What is CLB?
34. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
35. Design a 4:1 Mux using 2:1 Mux's.

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36. What is metastable state? How does it occur?
37. Design D Latch from SR flip-flop.
38. Define Clock Skew, Negative Clock Skew, Positive Clock Skew? What is race condition? How it occurs? How
to avoid it.
39. What does Pipelining do?
40. Difference between blocking and non-blocking statement?
41. How to do Handshake between designs.
42. Define Glitch.
43. Difference between Intra and Inter assignment delay
44. Difference between Task and Function.
45. Difference between reg and wire.
46. Difference between Verilog Full case and Parallel case
47. Can a task called a function?
48. What does if else statements synthesized to and what does case statements synthesized into?
49. Difference between Case equality and case inequality.
50. Define specify block?
51. Why delays are required in Verilog, what are they?
52. What are the probable ways to avoid metastability?
53. What are the timing checks in Verilog?
54. Design a circuit that detects three consecutive '1's using Mealy and Moore FSM.
55. Define clock jitter.
56. Implement inverter using 2-to-1 multiplexer.
57. What is the difference between the following lines of code?
reg1<= #10 reg2 ;
reg3 = # 10 reg4 ;
58. What is the difference between unary and logical operators?
59. What is the significance Timescale directive?
60. What is delta simulation time?
61. What you mean by inferring latches?
62. How to avoid latches in your design?
63. Why latches are not preferred in synthesized design?
64. What is sensitivity list?
65. If you miss sensitivity list what happens?
66. What is general structure of Verilog code you follow?
67. What are system tasks?
68. What does `timescale 1 ns/ 1 ps’ signify in a Verilog code?

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69. What do you mean parallel block? // fork and join
70. What do you mean by logic synthesis?
71. What is force and release?
72. When running gate-level simulation, the output of a block is generating an "X". How do you debug it? What
could be causing the "X"?
73. What you will do, when you have to instantiate the module for multiple times in Verilog?
74. Explain how Verilog is different to normal programming language?
75. Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

a = 0;

a <= 1;

$display(a);

end

76. What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;

77. How will you represent string in Verilog?

78. Difference between case and casex and casez
79. Difference between == and ===
80. Difference between >> and >>>
81. How do I prevent selected parameters of a module from being overridden during instantiation?
82. Difference between Verilog and system Verilog function
83. How do I model Analog and Mixed-Signal blocks in Verilog?
84. How can I pass parameters to my simulation?
85. How will you mention rise time, fall time and turn off time delay in Verilog?
86. What are the synthesizable constructs?
87. Difference between $monitor, $display & $strobe?
88. Can you tell me some of system tasks and their purpose?
89. What is pli? why is it used?
90. What is Synthesis?
91. What is Netlist?
92. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list?

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93. Difference between parameter and `define
94. What is a compiler directive like ‘include’ and ‘ifdef’?
95. What are the scheduling semantics in Verilog?
96. Difference between initial and always, how will you generate clock
97. What is the use of $fdisplay, $readmemh and $writememb?
98. What are the ways you can generate clk?
99. What is the default time scale taken by tool when didn’t declaration in RTL? //100ps/10fs

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Answers
1. Explain what is Slack?
Ans. It is the difference between Required arrival time of the signal to its actual arrival time.
It has three types:
a) Zero Slack: Design is critically working at the desired frequency
b) Positive Slack: Design is meeting the timing and still it can be improved.
c) Negative Slack Design has not achieved the specified timing at the specified frequency.
2. Explain what is the use of def-param?
Ans. Defparam overrides the parameter value at compile time. Mostly in a stimulus module or top module when
we want to modify or override any parameter value in the design module then we can use defparam to change it.
3. How to find out longest path?
Ans. A max path between two end points is the path with the largest delay (also referred to as the longest path).
Similarly, a minpath is the path with the smallest delay (also referred to as the shortest path).
4. What are the different types of skews used?
Ans. Clock skew is a phenomenon in synchronous digital circuit systems in which the same sourced clock
signal arrives at different components at different times due to gate or, in more advanced semiconductor
technology, wire signal propagation delay.
The different types of skews are:
a) Positive skew: It occurs when the receiving register receives the clock tick later than the transmitting
register.
b) Negative skew: It is the opposite of positive skew; the transmitting register gets the clock tick later than the
receiving register.
c) Zero clock skew: It refers to the arrival of the clock tick simultaneously at transmitting and receiving
register.
5. What is front end and back end design?
Ans. Front end design is nothing but the when a design engineer is able to do RTL and Verification of the
design is said to be front end design. Back end design is the next process after front end design where we need
to implement it in a hardware, there is few things that happens before implementing such as floor-planning,
layout, physical verification, STA (Static Timing Analysis) and Tape-out.
6. What is the full form of RTL?
Ans. RTL stands for Register Transfer Level.
7. What is the difference between RTL and HDL?
Ans.
RTL stands for Register Transfer Level
HDL stands for Hardware Description Language

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We write our RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level
description in the same HDL language or whatever your target device/process will take.
8. Draw the state diagram to detect a sequence?
Ans.
For 1011 mealy FSM,
State Diagram State Table

Present State Next State Output

(PS) (NS)
X=0 X=1 X=0 X=1
S0 S0 S1 0 0
S1 S2 S1 0 0
S2 S0 S3 0 0
S3 S2 S1 0 1

9. Draw the state diagram of a traffic light controller?

Ans.

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10. What is the difference between Big Endean format and Little Endean format?
Ans. Big-endian and little-endian are terms that describe the order in which a sequence of bytes are stored in
computer memory. Big-endian is an order in which the "big end" (most significant value in the sequence) is
stored first (at the lowest storage address). Little-endian is an order in which the "little end" (least significant
value in the sequence) is stored first.
11. What do you mean by concurrent statement?
Ans. concurrent statement defines one of the interconnected blocks or processes that describe the overall
behavior or structure of a design. Concurrent statements in a design
execute continuously, unlike sequential statements
12. Define component instantiation?
Ans. The process of creating objects from a module template is called instantiation, and the objects are called
instances.
13. What is the difference between variable and signal?
Ans. Variable can be a register which is used to store a value. We can use keyword ‘reg’. Signals can be just
passing a value from one point to another. We can use keyword ‘wire’.

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14. List some sequential statements?
Ans. The sequential statements are:
a) if statement
b) case statement
c) for statement
d) repeat statement
e) while statement
f) forever statement
g) unnamed block statement
h) fork - join statements
i) wait statement
j) event triggered statement
k) delay statement
l) disable statement
m) assign - deassign statements
n) force - release statements
15. Define a test bench?
Ans. Test bench are nothing but the stimulus block to check the result of the design by instancing the design
module and connecting it with reg and wire. Usually in test bench, we mention our input registers values and
suppose we have clock or reset values then we mention them in it to finally get out output register values.
16. What are the advantages of test benches?
Ans. Without a test bench when we execute a design we won’t be able to get any waveform signals since the
inputs are not given. To give the signals manually we have to force drive the value of each variables which can
be time consuming. Using a Test bench, we can give all the desired inputs of the design and save time. Another
advantage is that we can use multiple test cases for our design module if they want to store different sequence of
input into the design.
17. What is the difference between behavioral simulation and timing simulation?
Ans. Timing simulation takes into account the delays associated with the actual synthesis and logic placement.
It is a more accurate picture of how robust your design is. While the behavioral simulation has to account for
clocked delays like registers it is naive about routing delays. Generally, behavioral simulation is good for
checking logic. Of course it's only as good as your test bench. If you are doing serious work, then formal
methods are better for catching events or conditions that you might not have thought about. For designs using a
high percentage of resources timing simulation is more important and worth the extra step. Sometimes you don't
have access to the innards of IP and a timing simulation is the only route to fixing problems.
18. Does frequency of operation depend on critical path in a circuit? Justify?

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Ans. It’s a check of the timing, by allocating unit delays to all the gates, ie frequencies are not considered here.
Meaning Frequency of the operation does not depend on the critical path in a circuit.
19. What are different types of scaling? Which one is used and why?
Ans. Device scaling is an important part of the very large scale integration (VLSI) design to boost up the
success path of VLSI industry, which results in denser and faster integration of the devices. As technology node
moves towards the very deep submicron region, leakage current and circuit reliability become the key issues.
Both are increasing with the new technology generation and affecting the performance of the overall logic
circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with
scaling of the devices. There are various scaling methods used for VLSI circuits. Most common are voltage
scaling, load scaling, technology scaling and transistor sizing (width scaling).
20. What are the different design styles in VLSI?
Ans. The different design styles in VLSI are:
a) Field Programmable Gate Array (FPGA)
b) Gate Array Design
c) Standard-Cells Based Design
d) Full Custom Design

21. What is entry delay and exit delay?

Ans.
Entry delay: Paths that start at an input pad and end on the data input of a sequential logic cell (the D input to a
D flip-flop, for example). We might call this an entry path (or input-to-D path) to a pipelined design.
Exit delay: Paths that start at a sequential logic cell output and end at an output pad. This is an exit path ( clock-
to-output path) from the pipeline.
22. What is the difference between testing and verification?

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Ans.
Verification Testing
 Verifies correctness of design.  Verifies correctness of hardware.
 Performed by simulation, hardware  Two-parts:
emulation or formal methods. a) Test generation: software process
 Performed “once” prior to manufacturing. executed “once” during design.
b) Test application: electrical tests
applied to hardware.
 Test application performed on EVERY
manufactured device.

23. What are set up time & hold time constraints? What do they signify?
Ans.
Set up time constraint signifies how late the input signal can arrive before the active edge of the flip-flop.
Smaller the set up time, the better.
Hold time on the other hand signifies how long the value at the input needs to be held stable after the the active
edge. Again the smaller the hold time, the better.
24. Which timing constraint is critical for estimating maximum clock frequency of a circuit?
Ans. For estimating maximum clock frequency, set up time is critical.
25. What’s the critical path in a circuit?
Ans. Critical paths are timing-sensitive functional paths. because of the timing of these paths is critical, no
additional gates are allowed to be added to the path, to prevent increasing the delay of the critical path. Timing
critical path are those path that do not meet your timing. What normally happens is that after synthesis the tool
will give you a number of path which have a negative slag. The first thing you would do is to make sure those
path is not false or multicycle since it that case you can just ignore them.
26. How to implement Half-adder and full-adder in RTL?
Ans.
module halfadder(sum,cout,a,b);
input a,b;
output sum,cout;
xor(sum,a,b);
and(cout,a,b);
endmodule

module Fulladder(sum,cout,a,b,cin);

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input a,b,cin;
output cout,sum;
wire w1,w2,w3;
haldadder h1 (w1,w2,a,b);
haldadder h2 (sum,w3,cin,w1);
or(cout,w2,w3);
endmodule

27. What is the significance of FPGA in modern day electronics?

Ans. FPGAs are particularly useful for prototyping application-specific integrated circuits (ASICs) or
processors. An FPGA can be reprogrammed until the ASIC or processor design is final and bug-free and the
actual manufacturing of the final ASIC begins. Intel itself uses FPGAs to prototype new chips. Main FPGA
applications are: Medical, video & image processing, telecom & datacom, server & cloud and defense and
space. FPGA chips are used in both wired and wireless communications.
28. What is LUT?
Ans. LUT stands for Look Up Table, in general terms is basically a table that determines what the output is for
any given input(s). The LUT in an FPGA holds a custom truth table, which is loaded when the chip is powered
up.
29. What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
Ans. When there are multiple procedural assignments made to the same reg variable in a sequential always
block, then the last assignment is picked up for logic synthesis.
30. What is the significance of contamination delay in sequential circuit timing?
Ans. The contamination delay of the data path in a sequential circuit is critical for the hold time at the flip flop
where it is exiting. Contamination delay is also called tmin and Propagation delay is also called tmax in many
data sheets.
31. What do conditional assignments get inferred into?
Ans. Conditionals in a continuous assignment are specified through the “? :” operator. Conditionals get inferred
into a multiplexer. For example, assign wire1 = (sel==1'b1) ? a : b; // where a is 1 and b is 0

32. What logic is inferred when there are multiple assign statements targeting the same wire?
Ans. It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become
an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one
source. However, it is legal to drive a three-state wire by multiple assign statements.
33. What is slice? What is CLB?
Ans. A CLB is the fundamental component of an FPGA, allowing the user to implement virtually any logical
functionality within the chip. This is achieved by the usage of two sets of similar components within a block,

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known as slices. There are two different types of slices, referred to as SLICEM and SLICEL, and each CLB can
contain either a SLICEM and SLICEL or two SLICELs.
one CLB = 2 slices, one slice = 4 LUTs + 8 FF. Therefore, one CLB = 8 LUTs + 16FF.
34. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
Ans.
SoC: SoC is known as a system on a chip or system on a chip. It is an integrated circuit that assimilates all
components of electronic system or computer.
ASIC: Application Specific Integrated Circuit (ASIC) is one type of integrated circuit (IC) that’s customized
for the specific use and relatively planned for general-purpose use.
Full custom chip: It is a methodology for designing integrated circuits by specifying the layout of each
individual transistor and the interconnections between them.
FPGA: A Field-Programmable Gate Array(FPGA) is a semiconductor device containing programmable logic
components called "logic blocks", and programmable interconnects. The FPGA configuration is generally
specified using a hardware description language (HDL), similar to that used for an application-specific
integrated circuit (ASIC).
35. Design a 4:1 Mux using 2:1 Mux's.
Ans.

Select Line Output

a b Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

36. What is metastable state? How does it occur?

Ans. A metastable state is one in which the output of a Flip-Flop inside of your FPGA is unknown, or non-
deterministic. When a metastable condition occurs, there is no way to tell if the output of your Flip-Flop is
going to be a 1 or a 0. A metastable condition occurs when setup or hold times are violated. Metastability is bad.
It can cause your FPGA to exhibit very strange behavior.
Most metastable conditions occur in one of two ways:
• You are sampling a signal external to the FPGA
• You are crossing clock domains.
37. Design D Latch from SR flip-flop.

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Ans.

38. Define Clock Skew, Negative Clock Skew, Positive Clock Skew? What is race condition? How it occurs? How
to avoid it.
Ans.
Clock skew: It is a phenomenon in synchronous digital circuit systems in which the same sourced clock signal
arrives at different components at different times due to gate or, in more advanced semiconductor technology,
wire signal propagation delay.
Negative skew: It is the opposite of positive skew; the transmitting register gets the clock tick later than the
receiving register.
Positive skew: It occurs when the receiving register receives the clock tick later than the transmitting register.
Race Condition: A Verilog race condition occurs when two or more statements that are scheduled to execute in
the same simulation time-step, would give different results when the order of statement execution is changed, as
permitted by the IEEE Verilog Standard. When there is 1 or more input change at any time may create race
condition. The only wave to avoid it is by using program block, clocking block, handshaking method and using
non-blocking assignment.
39. What does Pipelining do?
Ans. Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided
into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from
one end and exit from another end. Pipelining increases the overall instruction throughput.
40. Difference between blocking and non-blocking statement?

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Ans.
Blocking Statements: A blocking statement must be executed before the execution of the statements that
follows it in a sequential block
Non-Blocking Statements: A non-blocking statement allow you to schedule assignment without blocking the
procedural flow.
41. How to do Handshake between designs.
Ans. The most common simple handshake for a single clock domain would be the valid/ready handshake. The
advantage of this scheme is that you can send one data per clock cycle without any down time. If valid is still
high the next cycle after valid/ready was high, then this is considered a second packet.
42. Define Glitch.
Ans. Glitches are nothing but the unintended outputs that can occur when monitoring the output.
43. Difference between Intra and Inter assignment delay
Ans.
Inter delay: An inter-assignment delay statement has delay value on the left-hand side of the assignment
operator.
Intra delay: Intra assignment are those delay statements where the execution of the entire statement or
assignment got delayed.
44. Difference between Task and Function.
Ans. The Task and Function difference are:
• A function must execute in one simulation time unit; a task can contain time-controlling statements.
• A function cannot enable a task; a task can enable other tasks and functions.
• A function must have at least one input argument; a task can have zero or more arguments of any type.
• A function returns a single value; a task does not return a value.
45. Difference between reg and wire.
Ans. Reg is use to stored and pass the values but wire it can only pass the values.
46. Difference between Verilog Full case and Parallel case
Ans. The difference between Verilog Full case and Parallel case is:
"full" case statement: It is a case statement in which all possible case-expression binary patterns can be
matched to a case item or to a case default. If a case statement does not include a case default and if it is
possible to find a binary case expression that does not match any of the defined case items, the case statement is
not "full."
"parallel" case statement: It is a case statement in which it is only possible to match a case expression to one
and only one case item. If it is possible to find a case expression that would match more than one case item, the
matching case items are called "overlapping" case items and the case statement is not "parallel."
47. Can a task called a function?
Ans. Yes, Task can call a function.

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48. What does if else statements synthesized to and what does case statements synthesized into?
Ans. Both statement constructs essentially generate muxes. The if-elsif-else construct infers a priority routing
network and the case construct, on the other hand, infers a big ol' mux.
49. Difference between Case equality and case inequality.
Ans.
Case equality: It is represented as “===”, returns 0 or 1.
Case inequality: It is represented as “!==”, returns 0 or 1.
50. Define specify block?
Ans. The Specify block was designed to define a delay across a module. It starts with specify and ends with the
endspecify keyword. Inside the block the user can specify: specparam declaration, path declaration or system
timing check.
Simplified Syntax
specify
specparam declaration;
path declaration;
system timing check;
endspecify
51. Why delays are required in Verilog, what are they?
Ans. They allow a degree of realism to be incorporated into the modeling process. The time taken for changes
to propagate through a module may lead to race conditions in other modules. Some designs, such as high speed
microprocessors, may have very tight timing requirements that must be met.
There are different types of delays depending on the design approach, such as :
Gate-Level Modeling: Propagation Delay, Rise Delay, Fall Delay, Turn-off Delay
Dataflow Modeling: Regular Assignment Delay, Net Declaration Delay, Implicit Continuous Assignment,
Inertial delay, Transport delay
Behavioral Modeling: Inter Assignment Delay, Intra Assignment Delay, Zero Delay
52. What are the probable ways to avoid metastability?
Ans. By adding Double flop.
53. What are the timing checks in Verilog?
Ans. Timing checks are used to verify that timing constraints are upheld, and are especially important in the
simulation of high-speed sequential circuits such as microprocessors. All timing checks must be contained
within specify blocks. Verilog contains many timing-check system tasks, but the three most common tasks are
$setup, $hold and $width. The $setup and $hold tasks are used to monitor the setup and hold constraints during
the simulation of a sequential circuit element and $width task is used to check the minimum width of a positive
or negative-going pulse.
54. Design a circuit that detects three consecutive '1's using Mealy and Moore FSM.

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Ans.

55. Define clock jitter.

Ans. Deviation of a clock edge from its ideal location. It is typically caused by clock generator circuit, noise,
power supply variation, interference from nearby circuits etc.
56. Implement inverter using 2-to-1 multiplexer.
Ans.

57. What is the difference between the following lines of code?

reg1<= #10 reg2 ;
reg3 = # 10 reg4 ;

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Ans. The difference between the above line codes are reg1 is have non-blocking assignment and reg3 is have
blocking assignment. Both are having intra assignment delay.
58. What is the difference between unary and logical operators?
Ans. The difference between unary and logical operators are:
Unary operators are those operators which requires only one operand. For e.g. ++(increment operator), - -
(decrement),etc.
Logical operators are those operators which typically deal with Boolean values. Some of the examples are
and(&&), or(||), not(!).
Unary operators are used to perform mathematical operation on like increment an operand by 1 or decrement it
whereas logical operators are used to perform some logical operation which deals with Boolean values
59. What is the significance Timescale directive?
Ans. Defines time units and simulation precision (smallest increment).
Syntax: 'timescale TimeUnit / PrecisionUnit
TimeUnit = specifies the unit of measurement for times and delays.
PrecisionUnit = specifies the precision to which delays are rounded off during simulation
60. What is delta simulation time?
Ans. Delta Time is a simulation time cycle It is used to order sequential events during simulation. More than
one event can occur during a delta time.
61. What you mean by inferring latches?
Ans. A latch is inferred within a combinatorial block where the net is not assigned to a known value. Assign a
net to itself will still infer a latch. Latches can also be inferred by missing signals form a sensitivity list and
feedback loops.
62. How to avoid latches in your design?
Ans. Suppose when we are using the “if statement”, we have to make sure that we include “else statement”
otherwise latches may form extra, similar when using the “case statement”, we need to include the “default
statement”.
63. Why latches are not preferred in synthesized design?
Ans. Latch is more sensitive to noise means that whenever there is change in the input output will change, that
will give race condition in the output. So a latch can cause glitches and ambiguous timing in a design, which
makes timing analysis of the design more difficult. In addition, a latch can cause significant stability and
reliability problems in a design because the behavior of the combinational loops in the latch often depends on
the relative propagation delays of the combinational loop's logic, causing the combinational loop to behave
differently under different operation conditions.
64. What is sensitivity list?
Ans. The sensitivity list indicates that when a change occurs to any one of elements in the list change,
begin…end statement inside that always block will get executed.

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65. If you miss sensitivity list what happens?
Ans. If a signal is in the sensitivity list of a process, the process will "wake up" and be evaluated whenever the
value of that signal changes. If it is not in the sensitivity list, a signal can change, but a process will not be re-
evaluated to determine what the new outputs should be.
66. What is general structure of Verilog code you follow?
Ans. We have a top module, stimulus and DUT (Design Under Test)
67. What are system tasks?
Ans. Verilog provides systems to do certain operations using system task. All system tasks appear in the form $.
Operations such as displaying on the screen, monitoring values of nets, stopping, and finishing are done by
system tasks.
68. What does `timescale 1 ns/ 1 ps’ signify in a Verilog code?
Ans. Here it means the time unit is given as 1ns and time precision is given as 1ps, so it will start from 1000ps
69. What do you mean parallel block? // fork and join
Ans. A parallel block can execute statements concurrently, and delay control can be used to provide the
assignments' time-ordering. Statements are launched in parallel by wrapping them within the fork and join
keywords.
70. What do you mean by logic synthesis?
Ans. Logic synthesis is the process of converting a high-level description of design into an optimized gate-level
representation. Logic synthesis uses a standard cell library which have simple cells, such as basic logic gates
like and, or, and nor, or macro cells, such as adder, muxes, memory, and flip-flops.
71. What is force and release?
Ans. The force statement will override all other assignments made to the variable until it is released using the
release keyword. For example:
reg a,b,c;
initial begin
force c=a&b;
…
release c; //if release keyword not mention then we won’t be able to get the c value.
End

72. When running gate-level simulation, the output of a block is generating an "X". How do you debug it? What
could be causing the "X"?
Ans. One of the main challenges in gate level simulation is the “x” propagation debug. X corruption may be
caused by a number of reasons such as timing violations, uninitialized memory and non-resettable flops. There
are uninitialized flops in design which by architecture are guaranteed to not cause any problems (if they settle to

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 Verilog
any value at start). Thus, there is a need to find out all such flops in the design (which are reviewed with
designers) and initialize them to some random value (either 0 or 1) so as to mimic silicon.
73. What you will do, when you have to instantiate the module for multiple times in Verilog?
Ans. Use the generate statement to instantiate the module multiple times.
74. Explain how Verilog is different to normal programming language?
Ans. Verilog, just like VHDL, is meant to describe hardware. Instead, programming languages such as C or
C++ provide a high level description of software programs, that is, a series of instructions that a microprocessor
executes. Verilog is a hardware definition language. Programming languages are generally understood to be
languages for telling existing hardware what to do, not for reconfiguring said hardware.
75. Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
Ans. Value for a is 0.
76. What is the difference between the following two lines of Verilog code?
i. #5 a = b;
ii. a = #5 b;
Ans.
For the first code #5 a = b; inter delay assignment is happening, variable a is executed only after 5ns.
For the second code a =#5 b; intra delay assignment is happening, value of b will store in variable ‘a’ after 5ns.
77. How will you represent string in Verilog?
Ans. There is no string data type is Verilog, so use the following to declare a register to hold a string.

reg[n*8:0] string;
Where the maximum length of the string is n characters. It takes 8 bits to store each character.
78. Difference between case and casex and casez
Ans.
case statement: It considers x or z as it is. So a case expression containing x or z will only match a case item
containing x or z at the corresponding bit positions. If no case item matches, then default item is executed.
casez statement: It considers z as don’t care.
casex statement: It considers both x and z as don’t care.
79. Difference between == and ===
Ans. Say you have to signals "a" and "b".
i. a == b

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 Verilog
ii. a === b
The 1st case is logical equality and will only evaluate to a 1 if both a and b are equal to logic values of 0 or 1. If
a or b are either X or high-Z, then the expression evaluates to 0 (false).
The 2nd case is case equality and takes into account all 4 logic states, 0/1X/high-Z. So if both a or b are an
unknown value X, the expression evaluates to 1 (true).
80. Difference between >> and >>>
Ans.
logical right shift (>>) always fill the vacated bit positions with zeroes.
arithmetic right shift (>>>) - shift right specified number of bits, fill with value of sign bit if expression is
signed, otherwise fill with zero
For example:
a = 5'b10100;
b = a >>> 2; //b == 5'b11101, cause sign bit was `1`
c = a >> 2; //c == 5'b00101
81. How do I prevent selected parameters of a module from being overridden during instantiation?
Ans. By using localparam
82. Difference between Verilog and system Verilog function
Ans.
Verilog Function SystemVerilog Function
 A function does not consumes time , that is it  Void Function : In SystemVerilog task that
cannot contain delays , blocking statements. does not consume time is written as void
 A function cannot call a task (As task function , void represents it is function that
contains delays). does not return a value which was not
 A function must return a value ,value must be possible in verilog function.
used in assignment statement.But it returns  Void function can be called from task as well
only single value (output or inout are not as function.
used with functions)A function is  If you want to ignore the return value of
function, simply cast it to “void” type.
synthesizable.
Default values to the arguments. Not only
you can pass arrays and queues, you can also
use them as return type in functions and
output/input in tasks.

83. How do I model Analog and Mixed-Signal blocks in Verilog?

Ans. AMS circuit models are typically written in Verilog-A, Verilog-AMS, VHDL-AMS, or SystemVerilog
language. Verilog-AMS and VHDL-AMS are behavioral modeling languages derived from Verilog and VHDL

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 Verilog
languages for digital design in order to support analog and mixed-signal modeling; Verilog-A is just a subset of
Verilog-AMS for defining analog-only systems. SystemVerilog, originally developed as a language for digital
design and verification, has also been recently extended to support analog and mixed-signal behavioral
modeling using real number modeling (RNM) paradigm.

84. How can I pass parameters to my simulation?

Ans. By using instance declaration parameter value or by using defparam
85. How will you mention rise time, fall time and turn off time delay in Verilog?
Ans.
rise: The time taken for the output of a gate to change from some value to 1 is called rise delay.
fall: The time taken for the output of a gate to change from some value to 0 is called fall delay
turn-off: The time taken for the output of a gate to change from some value to high impedance is called turn-off
delay
In verilog we can mention it like this
Syntax: Gate #(<rise>, <fall>, <turn_off>) o1 (output, inputs)
or #(1,2,3) o1 (out, a, b); // rise delay=1; fall delay=2; turn-off=3
86. What are the synthesizable constructs?
Ans. The synthesizable constructs are module, instantiation, always, assign, primitives, ports, parameter,
functions and task, loop, verilog operators, Blocking and Non-Blocking assignments, if-else, case, casex, casez,
Compiler directives, Bits and part select.

87. Difference between $monitor, $display & $strobe?

Ans.
$display: It is the main system task for displaying values of variables or strings or expressions. The format of
$display is similar to printf in C. A $display task inserts a new line at the end of the string by default. If it has
no arguments, then it produces a newline.
$monitor: It is used to monitor a signal when its value changes. The format is similar to $display task is used in
$monitor task. Unlike $display, $monitor need to be invoked only once. Only one monitoring statement can be
active at a time. If there are more than one $monitor statement in simulation, the last $monitor statement will be
the active statement. The earlier $monitor statement will be overridden.

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 Verilog
$strobe: It displays once every time they are executed. The only difference between $display and $strobe is that
$strobe displays the parameters at the very end of the current simulation time unit rather than exactly when it is
executed.
88. Can you tell me some of system tasks and their purpose?
Ans. The different types of system tasks are:
$display: It is the main system task for displaying values of variables or strings or expressions.
$monitor: It is used to monitor a signal when its value changes
$strobe: It displays once every time they are executed.
$time, $stime, $realtime: These return the current simulation time as a 64bit integer, a 32bit integer, and a real
number, respectively.
$reset: It resets the simulation back to time 0
$stop: It halts the simulator and puts it in interactive mode where the user can enter commands.
$finish: It terminates the simulation.
$write: It becomes useful if you want to print a set of values or all on a single line
$random: It generates a random integer every time it is called.
$dumpfile: These can dump variable changes to simulation viewer like Edaplayground. The dump files are
capable of dumping all the variables in simulation. This is convenient for debugging, but can be very slow.
$dumpvar: It dumps all the variables in the design.
$dumpon: It initiates the dump
$dumpoff: It stop dumping
89. What is pli? why is it used?
Ans. Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs
with programs written in C language. It also provides mechanism to access internal databases of the simulator
from the C program. PLI is used for implementing system calls which would have been hard to do otherwise (or
impossible) using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel
and hardware related features of Verilog and sequential flow of C - using PLI.
90. What is Synthesis?
Ans. Conversion of HDL code to gate level netlist.
91. What is Netlist?
Ans. Netlist describes the logical functionality of the circuit/system in terms of its structure, based on logic
gates (including compound gates and cells from the standard cell library).
92. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list?
Ans. Yes, in a pure combinational circuit it is necessary to mention all of the inputs in the sensitivity list, as not
doing so may create different result in pre-synthesis and post-synthesis simulation, as during the synthesis, the
tool considers all the input in the sensitivity list, whereas, simulation tool only considers the given inputs in the
sensitivity list.

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 Verilog
93. Difference between parameter and `define
Ans.
parameter: It is a data type in verilog. It is used to declare constants which are not modified during runtime,
where as we can use defparam statement for updating the parameter.
'define: It is a macro that can be used to define any variable, function or exprassion under a name. U can use
the macro for a given data in our code with ' identifier
94. What is a compiler directive like ‘`include’ and ‘`ifdef’?
Ans.
`include: This compiler directive lets you insert the entire contents of a source file into another file during
Verilog compilation.
`ifdef: This directive checks that a macro has been defined, and if so, compiles the code that follows.
95. What are the scheduling semantics in Verilog?
Ans.
A simulation timeslot is divided into ordered regions to provide a predictable interaction between design
constructs.

Active Region is for executing process statement.

Inactive Region is for executing process statements postponed with a “#0”procedural delay
NBA region is for updating non-blocking assignments.
Monitor region is for executing $monitor and $strobe and for calling user routines registered or execution
during this read-only region.

96. Difference between initial and always, how will you generate clock
Ans.
Initial Block will run a single time and by creating forever loop we can generate the clock.

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 Verilog
initial begin
clk = 0;
forever #5 clk = ~clk;
end
Always Block will keep on running on the given statement.
initial clk =0;
always #5 clk = ~clk;

97. What is the use of $fdisplay, $readmemh and $writememb?

Ans. These are used in file handling io operations
$fdisplay: Similar to $display, writes out to file instead
$readmemh: Backdoor read, example $readmemh(“load_mem.hex”, memory); //Load to memory from file.
$writememb: Backdoor write, example $writememb(“load_mem.bin”, memory); //Fetch from memory and
written to file.
98. What are the ways you can generate clk?
Ans. The different ways we can generate clock is by using forever loop and always construct.

99. What is the default time scale taken by tool when didn’t declaration in RTL? //100ps/10fs
Ans. By default it is considering as `timescale 1ns/1ns.
Syntax for time scale: `timescale <time_unit>/<time_precision>
So if we want 100ps/10fs then, it is `timescale 100ps/10fs

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