Design and Verification of AMBA AHB-Lite Protocol Using Verilog HDL
Design and Verification of AMBA AHB-Lite Protocol Using Verilog HDL
APB (Advanced Peripheral Bus) mainly used as an ancillary or general purpose register based
peripherals such as timers, interrupt controllers, UARTs, I/O ports, etc. It is connected to the system
bus via a bridge, helps reduce system power consumption. It is also easy to interface to, with little logic
involved and few corner- cases to validate.
AHB (Advanced High Performance Bus) is for high performance, high clock frequency system
modules with suitable for medium complexity and performance connectivity solutions. It supports
multiple masters.
AHB-Lite is the subset of the full AHB specification which intended for use where only a single bus
master is used and provides high-bandwidth operation.
III. AHB-LITE PROTOCOL SYSTEM
AMBA AHB-Lite protocol is designed for high-performance synthesizable designs.It is a transport interface that
provides a simplex transport mechanism and ensureshigh speed data transfer capacity. AHB-Lite implements
the features required for high-performance, high clock frequency systems including: [1]
Burst Transfers
Single-Clock Edge Operation
Non-Tristate Implementation
Wide Data Bus Configurations, 64, 128, 256, 512, And 1024 Bits.
The most common AHB-Lite slaves are memory devices, interfaces and high bandwidth peripherals. Although
low-bandwidth peripherals can be incorporated as AHB-Lite slaves, for system performance reasons they
typically reside on the AMBA Advanced Peripheral Bus (APB). Bridging between this higher level of bus and
APB is done using AHB-Lite slave, also known as an APB bridge.
Figure 2shows a single master AHB-Lite system design consisting of one master and three slaves. The bus
interconnect logic consists of one address decoder and a slave-to-master multiplexor. The decoder monitors the
address from the master so that the appropriate slave is selected and the multiplexor routes the corresponding
slave output data back to the master. The main component types of an AHB-Lite system are:
Master
Slave
Decoder
Multiplexor
AHB-Lite Master: It provides address and control information to initiate read and write operations
AHB-Lite Slave: The slave responds to the transfers initiated by masters in the system. The slaveuses
the HSELxselect signal from the decoder to control when it responds to a bustransfer.
Decoder: It is used to decode the address of each transfer and provides a select signal for theslave that
is involved in the transfer. It also provides a control signal to the multiplexor.
Multiplexor: A single centralized multiplexor is required in all AHB-Lite implementations that usetwo
or more slaves.A slave-to-master multiplexor is required to multiplex the read data bus and
responsesignals from the slaves to the master. The decoder provides control for the multiplexor.
3.1 OPERATIONS OF AHB-LITE:
The master starts a transfer by driving the address and control signals. These signals provide information about
the address, direction, width of the transfer, and indicate ifthe transfer forms part of a burst. Transfers can
be:[11].
single
incrementing bursts that do not wrap at address boundaries
Wrapping bursts that wrap at particular address boundaries.
TABLE I. Transfer Types
The write data bus moves data from the master to a slave, and the read data bus movesdata from a slave to the
master.Every transfer consists of: [2]
Address phase one address and control cycle
Data phase one or more cycles for the data.
A slave cannot request that the address phase is extended and therefore all slaves mustbe capable of sampling
the address during this time. However, a slave can request thatthe master extends the data phase by using
HREADY. This signal when LOW, causeswait states to be inserted into the transfer and enables the slave to
have extra time toprovide or sample data.
The slave uses HRESP to indicate the success or failure of a transfer
Table II. Transfer Responses
HRESP HREADY
0 1
0 Transfer pending Successful transfer completed
1 ERROR response, first cycle Error response, second cycle
V. AHB-LITE ADVANTAGES
The advantage of using the AHB-Lite protocol is that the bus master does not have to support the following
cases [15]:
Losing ownership of the bus. The clock enable for the master can be derived from the HREADY signal
on the bus.
Early terminated bursts. There is no requirement for the master to rebuild a burst due to early
termination, because the master always has access to the bus.
Split or Retry transfer responses. There is no requirement for the master to retain the address of the last
transfer to be able to restart a previous transfer.
VI. SIMULATION RESULTS
Simulation is being carried out on NCSim which is trademark of Cadence, using Verilog as hardware
verification language. The test cases are run for multiple operations. The different test case patterns are used to
verify the AHB-Lite slave.
To perform various transactions like write and read operations between master and slave, the concatenated input
format and their values passed to invoke a function. Simulation is carried out in ModelSim (from Mentor
Graphics) tool and Verilog is used as programming language.
A. Single Burst
Fig.5 shows a write transfer using a four-beat incrementing burst, with a wait state added for the first transfer. In
this case, the address does not wrap at a 16-byte boundary and the address 100 is followed by a transfer to
address 104.
Fig.6 shows a read transfer using a four-beat incrementing burst, with a wait state added for the first transfer. In
this case, the address does not wrap at a 16-byte boundary and the address 108 is followed by a transfer to
address 112.
C. Four-Beat Wrapping Burst (WRAP 4)
Fig.7 shows a write transfer using a four-beat wrapping burst, the burst is a four-beat burst of word write
transfers, the address wraps at 16-byte boundaries, and the transfer to address 108 is followed by a transfer to
address 92.
Fig. 8 shows a read transfer using a four beat wrapping burst, the burst is a four-beat burst of word read
transfers, the address wraps at 16-byte boundaries, and the transfer to address 92 is followed by a transfer to
address 76.
D. Undefined Length Burst
The first burst is a write consisting of two halfword transfers starting at address 0x20. These transfer addresses
increment by two. Fig 9 shows incrementing bursts of undefined length of write transfer.
The second burst is a read consisting of three word transfers starting at address 0x5C. These transfer addresses
increment by four. Fig 10 shows incrementing bursts of undefined length of read transfer.
VII. CONCLUSION
In this paper a general definition for AHB-LITE protocol which has high performance represents asignificant
advance in the capabilities of the ARM AMBA bus on-chip interconnect strategy, byproviding a solution that
reduces latencies and increases the bus bandwidth. AHB-Lite fullycompatible with the current AHB
specification.Each of the major AHB-Lite transfers like Single (non-sequential) transfer and sequential transfers
(wrap and increment burst of 4 bit data size) have been verified with individual test cases. All these test cases
are run and verified using Mentor Graphics ModelSim simulator.
ACKNOWLEDGEMENT
The authors would like to thank the entire semiconductor team at CYIENT for their immense support and
motivation. Without their guidance this paper would not have seen the light of day. A special thanks to Mr. Ram
Gollapudi for allowing the authors to use the companies valuable resources to complete the project.
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