MICROCONTROLLERS

Handbook

8051 and ARM7 microcontroller

Register details and Instruction sets
Microcontrollers MIT Manipal

8051 Microcontroller
8051- pin diagram

Structure of Internal RAM of 8051:

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Special Function Registers (SFRs) of 8051

PSW - PROGRAM STATUS WORD Register

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TCON - Timer Control (SFR) [Bit-Addressable As TCON.7 to TCON.0]

TMOD - Timer Mode Control (SFR) [NOT Bit-Addressable]

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ISR - Interrupt Service Routine address

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DAC 0800 Pin Diagram

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ADC 0808/0809 Pin diagram

LCD Pin Diagram

Commands for LCD

Code (Hex) Command to LCD
38 2 lines and 5X7 matrix
01 Clear display screen
02 Return home
04 Shift cursor left
06 Shift cursor right
05 Shift display right
07 Shift display left
08 Display off, cursor off
0A Display off, cursor on
0C Display on, cursor off
0E Display on, cursor no blinking
80-8F Force cursor to 1st line first position - 16th position
C0-CF Force cursor to 2nd line first position - 16th position

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8051 Assembly Instruction Set

Arithmetic Instructions Logical Instructions

CODE DESCRIPTION MC CODE DESCRIPTION MC
ADD A, #n A A + n 1 ANL A, #n A A AND n 1
ADD A, Rr A  A + Rr 1 ANL A, Rr A  A AND Rr 1
ADD A, addr A  A + [addr] 1 ANL A, addr A  A AND [addr] 1
ADD A, @Rp A  A + [Rp] 1 ANL A, @Rp A  A AND [Rp] 1
ADDC A, #n A A + n + C 1 ANL addr, A [addr]  [addr] AND A 1
ADDC A, Rr A  A + Rr + C 1 ANL addr, #n [addr]  [addr] AND n 2
ADDC A, addr A  A + [addr] + C 1 ORL A, #n A A OR n 1
ADDC A, @Rp A  A + [Rp] + C 1 ORL A, Rr A  A OR Rr 1
SUBB A, #n A A - n - C 1 ORL A, addr A  A OR [addr] 1
SUBB A, Rr A  A - Rr - C 1 ORL A, @Rp A  A OR [Rp] 1
SUBB A, addr A  A - [addr] - C 1 ORL addr, A [addr]  [addr] OR A 1
SUBB A, @Rp A  A - [Rp] - C 1 ORL addr, #n [addr]  [addr] OR n 2
INC A AA+1 1 XRL A, #n A A X-OR n 1
INC Rr Rr  Rr + 1 1 XRL A, Rr A  A X-OR Rr 1
INC addr [addr]  [addr] + 1 1 XRL A, addr A  A X-OR [addr] 1
INC @Rp [Rp]  [Rp] + 1 1 XRL A, @Rp A  A X-OR [Rp] 1
INC DPTR DPTR  DPTR + 1 2 XRL addr, A [addr]  [addr] X-OR A 1
DEC A AA-1 1 XRL addr, #n [addr]  [addr] X-OR n 2
DEC Rr Rr  Rr -1 1 CLR A A  00 1
DEC addr [addr]  [addr] - 1 1 CPL A A 1’s compliment of A 1
DEC @Rp [Rp]  [Rp] - 1 1 RL A A0  A7  A6 …  A0 1
MUL AB BA  A X B (B – Higher) 4 RLC A C  A7  A6 …  A0  C 1
DIV AB BA  A / B (B – Remainder) 4 RR A A0  A7  A6 …  A0 1
DA A ADEC  ABIN 1 RRC A C  A7  A6 …  A0  C 1
SWAP A ALN AHN 1
NOP PC  PC + 1 1

DATA TRANSFER INSTRUCTIONS BRANCH INSTRUCTIONS

CODE DESCRIPTION MC CODE DESCRIPTION MC
MOV A, #n An 1 ACALL sadd [SP]  PC + 2; PC  sadd 2
MOV A, Rr A  Rr 1 LCALL ladd [SP]  PC + 3; PC  ladd 2
MOV A, addr A  [addr] 1 CJNE A, add, If (A ≠ [add]); PC  PC + 3 + 2
radd radd
MOV A, @Rp A  [Rp] 1 CJNE A, #n, If (A ≠ n); PC  PC + 3 + 2
radd radd
MOV Rr, A Rr  A 1 CJNE Rr, #n, If (Rr ≠ n); PC  PC + 3 + 2
radd radd
MOV Rr, #n Rr  n 1 CJNE @Rp, #n, If ([Rp] ≠ n); PC  PC + 3 + 2
radd radd
MOV Rr, addr Rr  [addr] 2 DJNZ Rr, radd If (Rr-1 ≠ 0); PC  PC + 2 + 2
radd

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CODE DESCRIPTION MC CODE DESCRIPTION MC

MOV addr, A [addr]  A 2 DJNZ add, radd If ([add]-1 ≠ 0); PC  PC + 3 2
+ radd
MOV addr, #n [addr]  n 2 AJMP sadd PC  sadd 2
MOV addr, Rr [addr]  Rr 2 LJMP ladd PC  ladd 2
MOV addr1, [addr1] [addr2] 2 SJMP radd PC  PC + 2 + radd 2
addr2
MOV addr, @Rp [addr] [Rp] 1 JMP @A+DPTR PC  A + DPTR 2
MOV @Rp, A [Rp]  A 1 JC radd If (C=1); PC  PC + 2 + radd 2
MOV @Rp, #n [Rp]  n 1 JNC radd If (C=0); PC  PC + 2 + radd 2
MOV @Rp, addr [Rp]  [addr] 2 JB b, radd If (b=1); PC  PC + 3 + radd 2
MOV DPTR, #nn DPTR  nn 2 JNB b, radd If (b=0); PC  PC + 3 + radd 2
MOVX A, @Rp A  [Rp]^ 2 JBC b, radd If (b=1); PC  PC + 3 + radd; 2
b0
MOVX A, @DPTR A  [DPTR]^ 2 JZ radd If (A=00); PC  PC + 2 + 2
radd
MOVX @Rp, A [Rp]^  A 2 JNZ radd If (A>00); PC  PC + 2 + 2
radd
MOVX @DPTR, A [DPTR]^  A 2 RET PC  [SP] 2
MOVC A, A  [A+DPTR] 2 RETI PC  [SP]; Enable Interrupts 2
@A+DPTR
MOVC A, @A+PC A  [A+PC] 2 BOOLEAN INSTUCTIONS
PUSH addr SP  SP + 1; [SP]  [addr] 2 CLR C C0 1
POP addr [addr]  [SP]; SP  SP - 1 2 CPL C C 1’s compliment of C 1
XCH A, Rr A   Rr 1 SETB C C1 1
XCH A, addr A   [addr] 1 CLR b b0 1
XCH A, @Rp A   [Rp] 1 CPL b b 1’s compliment of b 1
XCHD A, @Rp ALN   [Rp]LN 1 SETB b b1 1
MOV C, b Cb 2
BOOLEAN INSTUCTIONS MOV b, C bC 2
ANL C, \ b C  C AND (NOT b) 2 ANL C, b C  C AND b 2
ORL C, \b C  C OR (NOT b) 2 ORL C, b C  C OR b 2

ARM7 Microcontroller
ARM 7 Operating mode

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Microcontrollers MIT Manipal

ARM Register Organization

ARM7 CPSR/SPSR/Flag Register

ARM7 Assembly Instruction Set

Data Movement Instruction

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 Arithmetie Insirwetions
ADD Basic addition Fg: ADD RO, R1, R2, RORI +R2
ADC Add with Carry Fg: ADC R0, R1, R2; RO R I + R2 + Carry
SUB Basic subtraction Fg: SUB Ro, R1, R2; RO RI - R2
SBC Subtract with borrow (carry) Eg: SBC RO, R1, R2; RO R I R2 ICarry

RSB Reverse subtraction Eg: RSB RO, R1, R2; ROR2 - R1

RSC Reverse subtraction with carryY Eg: RSC RO, R1, R2; Ro R2 RI - ICarry
Note: Nomaly Arithmenic instructions do net alfect flags. Ywe want flags to be affected we must write S as a post
Eg: ADDS RO, RI, R2
Note: In ARM, subraction
produces an inverted carry
hat mesif there wws a borrow, Cary flag beromes 0 and ý No borrew then cary flag becomes I.

Logic Instructions

1 AND AND Eg: AND RO, R1, R2; RO ER1 AND R2

2 ORR OR Eg: ORR RO, R1, R2; RO R I OR R2

3 EOR Ex-OR Eg: EOR RO, R1, R2; RO R I XOR R2

BIC AND with complement Eg:BIC RO, R1,R2; RO ERI AND (NOT) R2
Sameas instruction 109 of8051 instruction set
Eg: CMP RO, R1;
Performs RO R1, Does not store the result but
S CMP Ordinary Compare
affects the flags.
Compare with Negated value
Eg: CMN RO, R1;
Performs RO + R1, Does not store the result but
CMN
affects the flaqs.
Eg: TST RO, R1;
Performs RO AND RI, Does not store the result but
TST Logical AND, Only affects flags affects the flags. Same instruction was in there in
8086 also0.
Eg: TEQ RO, R1;
Logical xOR, Only affects flags Performs RO XOR R1, Does not store the result but
8 TEQ
affects theflaqs.
Note: AND, ORR,EOR and BICinstructions donot alfectflag
we wanu flags to be affected we must write S as a postfix.
Eg: ANDS RO, RI, R2
Note: CMP, CMN, TST and TEQ instructions will not store the resul.

Theywill onBy affect thhe flags.

Second Operand: Using a Shifted Register

LSL Shifts left by the specified amount (multiplies by powers of two)

LSR Shifts right by the specified amount (divides by powers of two)

ASR Shifts right (divides by powers of two) and preserves the sign bit, for 2's
complement operations.
ROR Similar to an ASR but the bits wrap around as they leave the LSB and appear as the
MSB.
RRX This operation uses the CPSR C lag as a 33rd bit. Rotates right by 1 bit

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 Mulipty Instructions (Produce 32
bit result of32 bit multiplication)
Eg: MUL RO, R1, R2;
ROR1 x R2
MUL Ordinary Multiplication
MLA RO, R1, R2, R3;
ROR1
x R2 + R3

2 MLA Multiply and accumulate Eg:

will be afjected.
Note: Normally these instrucrions will not affect the flags. Ifwe put Spostfax then flags
Eg: MULSwill affect theflags.
tueO.
Note: lhese msruction operate on signed as well as unsigned numbers depending upon how the programmer mlerpreis
Long Multiply Instructions (Produce 64 bit result of 32 bit multriplicatiom)
R3;
Eg: UMULL RO, R1, R2,
Performs R2 x R3.
Produces 64 bit result.
UMULL Unsigned Long Multiply
RO gets Lower 32 bits, R1 gets Higher 32 bits.
Will treat operands and resut as unsigned numbers.
Eg: SMULL RO, R1, R2, R3;
2 SMULL Signed Long Multiply
Same as above but will treat numbers as Signed.
Eg: UMLAL RO, R1, R2, R3;
Performs (R2 x R3) + (R1, R0)
It multiplies R2 x R3. Then adds this 64 bit number
Unsigned Long Multiply and with the 64 bit number formed by combining R1
3 UMLAL (higher 32 bits) and RO (lower 32 bits).
Accumulate
Produces 64 bit result.
RO gets Lower 32 bits, R1 gets Higher 32 bits.
Will treat operands and resut as unsigned numbers.
Signed Long Multiply and Eg: SMLAL RO, R1, R2, R3;
SMLAL Same as above but will treat numbers as Signed.
Accumulate
Note: Normalytheseinstructionswillnoi afjectthe flags.fwe pu Spostfax then flags wilbeafected.
Eg: UMULLS willaffecstheflags.
Load and Sore instructions
Eg: LDR RO, [R1]:
RO gets data pointed by R1 (32 bits)
LDR Load Register Pls refer all addressing modes exaples for various
methods ofgiving source address.
2 LDRB Load Byte into register
Eg: LDRB RO, [R1];
RO gets byte data pointed by R1 (8 bits)
Remaining bits in RO become 0.
Eg: LDRH RO, [R1]:
3 LDRH Load halfword into register RO gets haf word pointed by R1 (16 bits)
Remaining bits in R0 become 0.
4 LDRSB Load signed byte Same as above but signed

LDRSH Load signed halfword Same as above but signed

Eg: STR RO,[R1];

Data rom RO gets stored at the location pointed by
STR Store Register R1 (32 bits)
Pis refer all addressing modes exaples for various
methods of giving source address.
Eg: STR B RO, [R1];
STRB Store Byte from register Data from RO gets stored at the location pointed by
RI (8 bitsS
Eg: STR H RO, [R1];
STRH Store halfword from register Data from RO gets stored at the location pointed by
R1(16 bits)
Store signed byte Same as above but signed
STRSB
-

10 STRSH Store signed halfword Same as above but signed

Multiple Byte Load- Store; Any Subset ofcurrentbank of registers can be transferred to
memory or Fetched from memory. The base register Rn detemines the source or destination
address.

LDM<mode> Rn, f<registers>}

STM<mode> Rn, f<registers>}
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For Example
LDMIA Rn!, {R1-R3

Addresing
mode
Description Start address End address Rn!

A Rn+4*N
increment after Rn Rn+4N -
4
18 increment before Rn+4 Rn +4 N Rn+4N
DA Rn 4 N
decrement after Rn 4N+4 Rn
DB decrement before Rn 4 * N Rn-44 Rn 4*N

N is the Number of Registers to load.

Addressing modes for stack operations

LDM Push = STM
Addressing mode Description Pop =

LDMFA LDMDA STMFA STMIB

FA full ascending
LDMFD LDMIA STMFD STMDB
FD full descending
EA LDMEA LDMDB STMEA STMIA
empty ascending
LDMED LDMIB STMED STMDA
ED empty descending

valid item.
Full ascending (FA): Stack grows up. SP points to the highest address containing a

Stack grows up. SP points to the first empty location above stack
Empty ascending (EA):

the lowest address containing a valid

Full descending (FD): Stack grows down. SP points to

data

Stack grows down. SP points to the first location below the stack.
Empty descending (ED):

Memory Instructions in Functions

Instructions Explanation
LDMFD SP, (list ofregisters) Pop the stack and assign values to registers
inascending order. Update sp.
STMFD SP! (list ofregisters Push the registers on the stack in descending8
order. Update sp.
Branch Instructions

Semantics Example Explanation

to label .foo
b labe b.foo Jump unconditionally
beq latbel beq .foo Branch to .foo if the last flag setting
instruction has resulted in an equality
and (Z flag is 1)
Branch to .foo if the last flag setting
bnelabe bne .foo
instruction has resulted in an inequality
and (Z flag is 0)

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 Semant1cs Example|
Explanation function at .foo
bl label bl.foo (1) Jump unconditionally to the
(2)Save the next PC (PC +4) in the Ir register

Semantics Example Explanation address

bx reg bx r2 (1) Jump unconditionally to the
contained in register, r2
Branch Conditions

Number|Suffix Meaning Flag State

0 eq equal Z=1
ne
notequal Z=0
2 cs/hs carry set/unsigned higher or equal C=1
3 cc/locary clear/ unsignedlower C=0
mi negative/ minus N=1
pl positive or zero/ plus N=0
6 VS
overflow V=1
VC no overflow V=0
hi unsigned higher (C=1) A(Z =0)
ls unsigned lower or equal_ (C =0) V (Z=1)
10 ge Signed greater than or equal N 0
11 signed less than N 1
12 gt s1gned greater than (Z 0) A(N= 0)
13 | le signed less than or equal (Z= 1) v (N= 1)
14 al always
15 reserved

Swap Instructions

SWP swap a word between memory and a register tmp = mem32[Rn

mem32[Rn] = Rm
Rd tmp
SWPB swap a byte between memory and a
register tmp = mem8[Rn]
mem8[Rn = Rm
Rd tmp

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