Memoria ROM
Memoria ROM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity rom512_28b is
port (
clk : in std_logic;
en : in std_logic;
);
end rom512_28b;
x"000001", --SuperLAN-2U
x"000009", --powerpipes?
x"00000C", --Cisco
x"00000D", --FIBRONICS LTD.
x"00000E", --Fujitsu
x"00000F", --Next
x"000010", --Hughes
x"000011", --Tektrnix
x"000013", --Camex
x"000014", --Netronix
x"000017", --Oracle
x"00001A", --AMD
x"00001D", --Cabletron
x"000020", --DIAB
x"000021", --SC&C
x"000024", --Olicom
x"000029", --Imc
x"00002A", --Trw
x"00003C", --Auspex
x"00003D", --AT&T
x"00003E", --Simpact
x"000044", --Castelle
x"000046", --ISC-BR
x"000048", --Epson
x"000053", --COMPUCORP
x"000055", --AT&T
x"00005A", --SK (Schneider & Koch in Europe and Syskonnect outside of Europe)
x"00005B", --Eltec
x"00005D", --Rce
x"00005F", --Sumitomo
x"000062", --Honeywell
x"000063", --HP
x"000066", --Talaris
x"000069", --SGI
x"00006A", --COMPUTER CONSOLES INC.
x"00006B", --MIPS
x"00006C", --Private
x"00006D", --Case
x"000073", --Dupont
x"00007A", --Ardent
x"00007D", --Cray
x"00007F"
);
begin
if rising_edge(clk) then
else null;
end if;
else
null;
end if;
end process;
end behavioral;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity testbench is
component rom512_28b IS
port (
clk : in std_logic;
en : in std_logic;
end component;
begin
----------------------------------------
-- CLOCK
Clock_gen: process
begin
end loop;
wait;
----------------------------------------
Stimulus: process
begin
wait;
end process;
en => en_in,