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Memoria ROM

The document describes a ROM component with 512 entries of 28-bit data. It includes the entity, architecture, and testbench for the ROM component. The architecture defines the ROM memory and outputs the data based on the address and clock.

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0% found this document useful (0 votes)
36 views8 pages

Memoria ROM

The document describes a ROM component with 512 entries of 28-bit data. It includes the entity, architecture, and testbench for the ROM component. The architecture defines the ROM memory and outputs the data based on the address and clock.

Uploaded by

raxuxgamer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Código:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

USE IEEE.STD_LOGIC_ARITH.ALL;

entity rom512_28b is

port (

clk : in std_logic;

en : in std_logic;

addr : in std_logic_vector(7 downto 0);

data : out std_logic_vector(23 downto 0)

);

end rom512_28b;

architecture behavioral of rom512_28b is

type memoria_rom is array (0 to 127) of std_logic_vector (23 downto 0);

signal ROM : memoria_rom := (

x"000000", --Officially Xerox

x"000001", --SuperLAN-2U

x"000002", --BBN (was internal usage only, no longer used)

x"000003", --XEROX CORPORATION

x"000004", --XEROX CORPORATION

x"000005", --XEROX CORPORATION

x"000006", --XEROX CORPORATION

x"000007", --XEROX CORPORATION

x"000008", --XEROX CORPORATION

x"000009", --powerpipes?

x"00000A", --OMRON TATEISI ELECTRONICS CO.

x"00000B", --MATRIX CORPORATION

x"00000C", --Cisco
x"00000D", --FIBRONICS LTD.

x"00000E", --Fujitsu

x"00000F", --Next

x"000010", --Hughes

x"000011", --Tektrnix

x"000012", --INFORMATION TECHNOLOGY LIMITED

x"000013", --Camex

x"000014", --Netronix

x"000015", --Datapoint Corporation

x"000016", --DU PONT PIXEL SYSTEMS .

x"000017", --Oracle

x"000018", --Webster Computer Corporation Appletalk/Ethernet Gateway

x"000019", --APPLIED DYNAMICS INTERNATIONAL

x"00001A", --AMD

x"00001B", --Novell (now Eagle Technology)

x"00001C", --JDR Microdevices generic, NE2000 drivers

x"00001D", --Cabletron

x"00001E", ---TELSIST INDUSTRIA ELECTRONICA

x"00001F", --Cryptall Communications Corp.

x"000020", --DIAB

x"000021", --SC&C

x"000022", --Visual Technology

x"000023", --ABB Automation AB, Dept. Q

x"000024", --Olicom

x"000025", --RAMTEK CORP.

x"000026", --SHA-KEN CO., LTD.

x"000027", --JAPAN RADIO COMPANY

x"000028", --PRODIGY SYSTEMS CORPORATION

x"000029", --Imc

x"00002A", --Trw

x"00002B", --CRISP AUTOMATION, INC


x"00002C", --NRC - Network Resources Corporation - MultiGate Hub1+, Hub2, etc

x"00002D", --CHROMATICS INC

x"00002E", --SOCIETE EVIRA

x"00002F", --TIMEPLEX INC.

x"000030", --VG LABORATORY SYSTEMS LTD

x"000031", --QPSX COMMUNICATIONS, LTD.

x"000032", --GPT Limited (reassigned from GEC Computers Ltd)

x"000033", --EGAN MACHINERY COMPANY

x"000034", --NETWORK RESOURCES CORPORATION

x"000035", --SPECTRAGRAPHICS CORPORATION

x"000036", --ATARI CORPORATION

x"000037", --Oxford Metrics Ltd

x"000038", --CSS LABS

x"000039", --TOSHIBA CORPORATION

x"00003A", --CHYRON CORPORATION

x"00003B", --Hyundai/ # Hyundai/Axil Sun clones

x"00003C", --Auspex

x"00003D", --AT&T

x"00003E", --Simpact

x"00003F", --Syntrex Inc

x"000040", --APPLICON, INC.

x"000041", --ICE CORPORATION

x"000042", --METIER MANAGEMENT SYSTEMS LTD.

x"000043", --MICRO TECHNOLOGY

x"000044", --Castelle

x"000045", --FORD AEROSPACE & COMM. CORP.

x"000046", --ISC-BR

x"000047", --NICOLET INSTRUMENTS CORP.

x"000048", --Epson

x"000049", --Apricot Ltd.

x"00004A", --ADC CODENOLL TECHNOLOGY CORP.


x"00004B", --APT

x"00004C", --NEC Corporation

x"00004D", --DCI CORPORATION

x"00004E", --AMPEX CORPORATION

x"00004F", --Logicraft 386-Ware P.C. Emulator

x"000050", --RADISYS CORPORATION

x"000051", --Hob Electronic Gmbh & Co. KG

x"000052", --Optical Data Systems

x"000053", --COMPUCORP

x"000054", --Schneider Electric

x"000055", --AT&T

x"000056", --DR. B. STRUCK

x"000057", --SCITEX CORPORATION LTD.

x"000058", --Racore Computer Products Inc

x"000059", --Hellige GMBH

x"00005A", --SK (Schneider & Koch in Europe and Syskonnect outside of Europe)

x"00005B", --Eltec

x"00005C", --TELEMATICS INTERNATIONAL INC.

x"00005D", --Rce

x"00005E", --U.S. Department of Defense (IANA)

x"00005F", --Sumitomo

x"000060", --KONTRON ELEKTRONIK GMBH

x"000061", --Gateway Communications

x"000062", --Honeywell

x"000063", --HP

x"000064", --Yokogawa Digital Computer Corp

x"000065", --Network General

x"000066", --Talaris

x"000067", --SOFT * RITE, INC.

x"000068", --Rosemount Controls

x"000069", --SGI
x"00006A", --COMPUTER CONSOLES INC.

x"00006B", --MIPS

x"00006C", --Private

x"00006D", --Case

x"00006E", --Artisoft, Inc.

x"00006F", --Madge Networks Ltd. Token-ring adapters

x"000070", --HCL LIMITED

x"000071", --ADRA SYSTEMS INC.

x"000072", --MINIWARE TECHNOLOGY

x"000073", --Dupont

x"000074", --RICOH COMPANY LTD.

x"000075", --Bell Northern Research (BNR)

x"000076", --ABEKAS VIDEO SYSTEM

x"000077", --Interphase [Used in other systems, e.g. MIPS, Motorola]

x"000078", --Labtam Australia

x"000079", --Networth Incorporated [bought by Compaq, used in Netelligent series]

x"00007A", --Ardent

x"00007B", --Research Machines

x"00007C", --AMPERE INCORPORATED

x"00007D", --Cray

x"00007E", --NetFRAME multiprocessor network servers

x"00007F"

);

begin

process (clk) begin

if rising_edge(clk) then

if (en = '1') then

data <= ROM(conv_integer(addr));

else null;

end if;
else

null;

--data <= (others =>'0');

end if;

end process;

end behavioral;

Testbench:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use ieee.std_logic_unsigned.all;

USE IEEE.STD_LOGIC_ARITH.ALL;

entity testbench is

end entity testbench;

architecture BENCH of testbench is

signal CLK_in : std_logic;

signal en_in : std_logic;

signal addr_in : std_logic_vector(7 downto 0);

signal data_out : std_logic_vector(23 downto 0);


signal Stop : BOOLEAN;

constant Period: TIME := 10 NS;

component rom512_28b IS

port (

clk : in std_logic;

en : in std_logic;

addr : in std_logic_vector(7 downto 0);

data : out std_logic_vector(23 downto 0)); --Vector Salida

end component;

begin

----------------------------------------

-- CLOCK

Clock_gen: process

begin

while not Stop loop

CLK_in <= '0';

wait for Period/2;

CLK_in <= '1';

wait for Period/2;

end loop;

wait;

end process Clock_gen;

----------------------------------------

Stimulus: process

begin

en_in <= '1';


addr_in <= conv_std_logic_vector(15,8);

wait for Period;

en_in <= '1';

addr_in <= conv_std_logic_vector(12,8);

wait for Period;

en_in <= '1';

addr_in <= conv_std_logic_vector(100,8);

wait for Period;

Stop <= TRUE;

report "Stimulus finished";

wait;

end process;

DUT: rom512_28b port map (

clk => CLK_in,

en => en_in,

addr => addr_in,

data => data_out);

end architecture BENCH;

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