DIGITAL SYSTEMS III

Chapter 5
AVR Serial Communication

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CONTENTS

1. AVR Serial Communication Concepts

2. AVR USART
3. AVR TWI/ I2C
4. AVR SPI

The contents of this presentation is confidential. ©VUT

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AVR Serial Communication - Basic Concepts

▪ The ATmega168 provides three primary forms of serial interface:

▪ synchronous/asynchronous serial,
▪ SPI master/slave synchronous, and
▪ a byte-oriented two-wire interface like the Philips I2C (Inter-Integrated Circuit) standard

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Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART)
▪ A common component of many AVR parts is a built-in USART (universal synchronous/ asynchronous receiver-
transmitter), also referred to as a UART (universal asynchronous receiver-transmitter).
▪ This function can be used to implement an RS-232 or RS-485 interface or used without external interface logic for
chip-to-chip communications.
▪ The baud rate is determined by the frequency of the clock used with the microcontroller, with 9,600 being a typical
speed. Higher rates are possible with a fast external crystal.
▪ The USART can also be used in SPI (serial peripheral interface) mode, in addition to the dedicated SPI logic found
in AVR devices.

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Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART)
▪ The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial
communication device. The main features are:
▪ Full Duplex Operation (Independent Serial Receive and Transmit Registers)
▪ Asynchronous or Synchronous Operation
▪ Master or Slave Clocked Synchronous Operation
▪ High Resolution Baud Rate Generator
▪ Odd or Even Parity Generation and Parity Check Supported by Hardware
▪ Data Over Run Detection
▪ Framing Error Detection
▪ Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
▪ Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
▪ Multi-processor Communication Mode
▪ Double Speed Asynchronous Communication Mode

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USART - Clock Generation

▪ The clock generation logic generates the base clock for the Transmitter and Receiver.
▪ The USART supports four modes of clock operation:
▪ Normal Asynchronous,
▪ Double Speed Asynchronous
▪ Master Synchronous
▪ Slave Synchronous mode.
▪ The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous
operation.
▪ Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA Register.
▪ When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls
whether the clock source is internal (Master mode) or external (Slave mode).
▪ The XCK pin is only active when using Synchronous mode.

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USART - The Baud Rate Generator (Internal Clock Generation )

▪ Internal clock generation is used for the asynchronous and the synchronous master modes of operation.
▪ The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable
prescaler or baud rate generator.
▪ The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted
down to zero or when the UBRRL Register is written.
▪ A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (=
fosc/(UBRR+1)).
▪ The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode.
▪ The baud rate generator output is used directly by the receiver’s clock and data recovery units.
▪ However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits

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USART - The Baud Rate Generator (Internal Clock Generation )

Signal description:
• txclk - Transmitter clock (Internal Signal).
• rxclk - Receiver base clock (Internal Signal).
• xcki - Input from XCK pin (Internal Signal).
Used for synchronous slave operation.
• Xcko - Clock output to XCK pin (Internal
Signal). Used for synchronous master
operation.
• fosc - XTAL pin frequency (System Clock).

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USART Initialization

▪ The USART has to be initialized before any communication can take place.
▪ The initialization process normally consists of setting the baud rate, setting frame format and enabling the
Transmitter or the Receiver depending on the usage.
▪ For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled)
when doing the initialization.
▪ Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing
transmissions during the period the registers are changed.
▪ The TXC Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used
to check that there are no unread data in the receive buffer.
▪ Note that the TXC Flag must be cleared before each transmission (before UDR is written) if it is used for this
purpose.
▪ The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality.
▪ The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The
baud rate is given as a function parameter. 9

▪ • For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers.
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USART Initialization

▪ For the assembly code, the baud rate parameter is assumed to be stored in the R17:R16 registers.
▪ When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O
location by UBRRH and UCSRC.
▪ More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so
on.
▪ However, many applications use a fixed setting of the Baud and Control Registers, and for these types of
applications the initialization code can be placed directly in the main routine, or be combined with initialization code
for other I/O modules.

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USART Data Transmission

▪ The USART Transmitter

▪ The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register.
▪ When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the
function as the transmitter’s serial output.
▪ The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
▪ If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock.

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USART - Transmitter Flags and Interrupts

▪ The USART transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit
Complete (TXC). Both flags can be used for generating interrupts.
▪ The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new data.
▪ This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that
has not yet been moved into the Shift Register.
▪ For compatibility with future devices, always write this bit to zero when writing the UCSRA Register.
▪ When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data
Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled).
▪ UDRE is cleared by writing UDR.
▪ When interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new
data to UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new interrupt will
occur once the interrupt routine terminates.

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USART - Transmitter Flags and Interrupts

▪ The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been
shifted out and there are no new data currently present in the transmit buffer.
▪ The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location.
▪ The TXC Flag is useful in half-duplex communication interfaces (like the RS485 standard), where a transmitting
application must enter receive mode and free the communication bus immediately after completing the
transmission.
▪ When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit Complete
Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are enabled).
▪ When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC Flag,
this is done automatically when the interrupt is executed.

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USART - Data Reception – The USART Receiver

▪ The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one.
▪ When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the
function as the receiver’s serial input.
▪ The baud rate, mode of operation and frame format must be set up once before any serial reception can be done.
▪ If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.

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USART - Receive Compete Flag and Interrupt

▪ The USART Receiver has one flag that indicates the receiver state.
▪ The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer.
▪ This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not
contain any unread data).
▪ If the receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become
zero.
▪ When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt
will be executed if the RXC Flag is set (provided that global interrupts are enabled).
▪ When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR to
clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
▪

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USART Register Description

▪ USART I/O Data Register (UDR)

▪ The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O
address referred to as USART Data Register or UDR.
▪ The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location.
▪ Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB).
▪ The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set.
▪ Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter.
▪ When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into
the transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the
TxD pin.

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USART Register Description

▪ USART Control and Status Register A (UCSRA) – It is used for control and status flags
▪ Bit 7 - USART Receive Complete (RXC)
▪ This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread
data).
▪ If the receiver is disabled, the receive buffer will be flushed and consequently the RXC bit will become zero.
▪ The RXC Flag can be used to generate a Receive Complete interrupt
▪ Bit 6 – USART Transmit Complete (TXC)
▪ This flag bit is set when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit
buffer (UDR).
▪ The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
▪ The TXC Flag can generate a Transmit Complete interrupt
▪ Bit 5 – USART Data Register Empty (UDRE)
▪ The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be
written.
▪ The UDRE Flag can generate a Data Register empty Interrupt
▪ UDRE is set after a reset to indicate that the transmitter is ready.
▪ Bit 4 – Frame Error (FE)
▪ This bit is set if the next character in the receive buffer had a Frame Error when received.
▪ that is, when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR) is read.
▪ The FE bit is zero when the stop bit of received data is one.
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▪ Always set this bit to zero when writing to UCSRA.
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USART Register Description

▪ USART Control and Status Register A (UCSRA) – It is used for control and status flags
▪ Bit 3 – Data Over Run (DOR)
▪ This bit is set if a Data OverRun condition is detected.
▪ A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive Shift Register, and a new start bit
is detected.
▪ This bit is valid until the receive buffer (UDR) is read.
▪ Always set this bit to zero when writing to UCSRA.
▪ Bit 2 – Parity Error (PE)
▪ This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 =
1).
▪ This bit is valid until the receive buffer (UDR) is read.
▪ Always set this bit to zero when writing to UCSRA.
▪ Bit 1 – Double the USART Transmission Speed (U2X)
▪ This bit only has effect for the asynchronous operation.
▪ Write this bit to zero when using synchronous operation.
▪ Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous
communication.
▪ Bit 0 – Multi-processor Communication Mode (MPCM)
▪ This bit enables the Multi-processor Communication mode.
▪ When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be
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USART Register Description

▪ USART Control and Status Register B (UCSRB)

▪ Bit 7 – RX Complete Interrupt Enable (RXCIE)
▪ Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete Interrupt will be
generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and
the RXC bit in UCSRA is set.
▪ Bit 6 – TX Complete Interrupt Enable (TXCIE)
▪ Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete Interrupt will be
generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and
the TXC bit in UCSRA is set.
▪ Bit 5 – USART Data Register Empty Interrupt Enable (UDRIE)
▪ Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty Interrupt will be
generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and
the UDRE bit in UCSRA is set.
▪ Bit 4 – Receiver Enable (RXEN)
▪ Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for
the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE, DOR,
and PE Flags. 19

▪ • Bit 3 – Transmitter Enable (TXEN)

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USART Register Description

▪ USART Control and Status Register B (UCSRB)

▪ Bit 3 – Transmitter Enable (TXEN)
▪ Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not
become effective until ongoing and pending transmissions are completed, that is, when the transmit Shift
Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter
will no longer override the TxD port.
▪ Bit 2 – Character Size (UCSZ2)
▪ The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character Size)
in a frame the receiver and transmitter use.
▪ Bit 1 – Receive Data Bit 8 (RXB8)
▪ RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits.
Must be read before reading the low bits from UDR.
▪ Bit 0 – Transmit Data Bit 8 (TXB8)
▪ TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine
data bits. Must be written before writing the low bits to UDR.
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USART Register Description

▪ USART Control and Status Register C (UCSRC)

▪ Bit 7 – Register Select (URSEL)
▪ This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC.
▪ The URSEL must be one when writing the UCSRC.
▪ Bit 6 – USART Mode Select (UMSEL)
▪ This bit selects between Asynchronous and Synchronous mode of operation.
▪ Bit 5:4 – Parity Mode (UPM1:0)
▪ These bits enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and
send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming
data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set.
▪ Bit 3 – Stop Bit Select (USBS)
▪ This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores this setting.
▪ Bit 2:1 –Character Size (UCSZ1)
▪ The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the
Receiver and Transmitter use.
▪ Bit 0 – Clock Polarity (UCPOL)
▪ This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets
the relationship between data output change and data input sample, and the synchronous clock (XCK). 21
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USART Register Description

▪ USART Baud Rate Registers – UBRRL and UBRRH

▪ Bit 15 – Register Select (URSEL)
▪ This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when reading UBRRH.
▪ The URSEL must be zero when writing the UBRRH.
▪ Bit 14:12 – Reserved Bits
▪ These bits are reserved for future use.
▪ For compatibility with future devices, these bits must be written to zero when UBRRH is written.
▪ Bit 11:0 – USART Baud Rate Register (UBRR11:0)
▪ This is a 12-bit register which contains the USART baud rate.
▪ The UBRRH contains the four most significant bits, and the UBRRL contains the 8 least significant bits of the USART
baud rate.
▪ Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed.
▪ Writing UBRRL will trigger an immediate update of the baud rate prescaler.

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Two-wire Serial Interface

▪ The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications.
▪ The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-
directional bus lines, one for clock (SCL) and one for data (SDA).
▪ The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
▪ All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are
inherent in the TWI protocol.
▪ The Main features of TWI as:
▪ Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed
▪ Both Master and Slave Operation Supported
▪ Device Can Operate as Transmitter or Receiver
▪ 7-bit Address Space allows up to 128 Different Slave Addresses
▪ Multi-master Arbitration Support
▪ Up to 400kHz Data Transfer Speed
▪ Slew-rate Limited Output Drivers
▪ Noise Suppression Circuitry Rejects Spikes on Bus Lines
▪ Fully Programmable Slave Address with General Call Support
▪ Address Recognition causes Wake-up when AVR is in Sleep Mode 23
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Two-wire Serial Interface

TWI Terminology

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Two-wire Serial Interface

▪ SCL and SDA Pins

▪ These pins interface the AVR TWI with the rest of the MCU system.
▪ The output drivers contain a slew-rate limiter in order to conform to the TWI specification.
▪ The input stages contain a spike suppression unit removing spikes shorter than 50 ns.
▪ Note that the internal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and
SDA pins, as explained in the I/O Port section.
▪ The internal pull-ups can in some systems eliminate the need for external ones
▪ Bit Rate Generator Unit
▪ This unit controls the period of SCL when operating in a Master mode.
▪ The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR).
▪ Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the slave must be at
least 16 times higher than the SCL frequency.
▪ Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
▪
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TWI Register Description

▪ TWI Bit Rate Register – TWBR

▪ Bits [7:0] – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator.
▪ The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
▪ TWI Control Register – TWCR
▪ The TWCR is used to control the operation of the TWI.
▪ It is used to
▪ enable the TWI,
▪ to initiate a master access by applying a START condition to the bus,
▪ to generate a receiver acknowledge,
▪ to generate a stop condition, and
▪ to control halting of the bus while the data to be written to the bus are written to the TWDR.
▪ It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.

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TWI Register Description

▪ TWI Control Register – TWCR

▪ Bit 7 – TWI Interrupt Flag (TWINT)
▪ This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in
SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL
low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not
automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation
of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register
(TWDR) must be complete before clearing this flag.
▪ Bit 6 – TWI Enable Acknowledge Bit (TWEA)
▪ The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is
generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A
general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver
or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire Serial
Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
▪ Bit 5 – TWI START Condition Bit (TWSTA)
▪ The application writes the TWSTA bit to one when it desires to become a master on the Two wire Serial Bus. The TWI
hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not
free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master
status. TWSTA must be cleared by software when the START condition has been transmitted.
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TWI Register Description

▪ TWI Control Register – TWCR

▪ Bit 4 – TWI STOP Condition Bit (TWSTO)
▪ Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP
condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used
to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined
unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.
▪ Bit 3 – TWI Write Collision Flag (TWWC)
▪ The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared
by writing the TWDR Register when TWINT is high.
▪ Bit 2 – TWI Enable Bit (TWEN)
▪ The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control
over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to
zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
▪ Bit 1 – Reserved Bit
▪ This bit is a reserved bit and will always read as zero.
▪ Bit 0 – TWI Interrupt Enable (TWIE)
▪ When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the
TWINT Flag is high.
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TWI Register Description

▪ TWI Status Register – TWSR

▪ Bits [7:3] –: TWI Status (TWS)
▪ These five bits reflect the status of the TWI logic and the Two-wire Serial Bus.
▪ The different status codes are described later in this section.
▪ The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking
independent of prescaler setting.
▪ Bit 2 – Reserved Bit
▪ This bit is reserved and will always read as zero.
▪ Bits [1:0] – TWI Prescaler Bits (TWPS)
▪ These bits can be read and written, and control the bit rate prescaler.

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TWI Register Description

▪ TWI Data Register – TWDR

▪ In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received.
▪ It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by
hardware.
▪ Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable if
TWINT is set.
▪ While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus,
except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a
lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the
TWI logic, the CPU cannot access the ACK bit directly.
▪ Bits 7:0 – TWI Data Register (TWD)
▪ These eight bits contain the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus

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TWI Register Description

▪ TWI (Slave) Address Register – TWAR

▪ The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will
respond when programmed as a slave transmitter or receiver.
▪ In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters.
▪ The LSB of TWAR is used to enable recognition of the general call address ($00).
▪ There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial
address.
▪ If a match is found, an interrupt request is generated.
▪ Bits 7:1 – TWI (Slave) Address Register (TWA)
▪ These seven bits constitute the slave address of the TWI unit.
▪ Bit 0 – TWI General Call Recognition Enable Bit (TWGCE)
▪ If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus

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Transmission Modes

▪ Master Transmitter Mode

▪ In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver. In order to enter a Master mode, a START
condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode
is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned
in this section assume that the prescaler bits are zero or are masked to zero.
▪ Master Receiver Mode
▪ In the Master Receiver mode, a number of data bytes are received from a slave transmitter. In order to enter a Master mode, a START
condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode
is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned
in this section assume that the prescaler bits are zero or are masked to zero.
▪ Slave Receiver Mode
▪ In the Slave Receiver mode, a number of data bytes are received from a master transmitter. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
▪ Slave Transmitter Mode
▪ In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver
▪ All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.

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Serial Peripheral Interface – SPI

▪ The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32 and peripheral devices or
between several AVR devices. The
▪ The SPI peripheral logic of the AVR supports all four standard SPI modes of operation.
▪ I/O pins on the AVR device may be configured to act as the MOSI, MISO, and SCK1 signals used by SPI.
▪ These pins are different from the RxD and TxD (receive data and transmit data) pins used by the USART.
▪ ATmega32 SPI includes the following features:
▪ Full-duplex, Three-wire Synchronous Data Transfer
▪ Master or Slave Operation
▪ LSB First or MSB First Data Transfer
▪ Seven Programmable Bit Rates
▪ End of Transmission Interrupt Flag
▪ Write Collision Flag Protection
▪ Wake-up from Idle Mode
▪ Double Speed (CK/2) Master SPI Mode

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SPI - Select Slave (SS) Pin Functionality

▪ Slave Mode
▪ When the SPI is configured as a Slave, the Slave Select (SS) pin is always input.
▪ When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs.
▪ When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which
means that it will not receive incoming data.
▪ Note that the SPI logic will be reset once the SS pin is driven high.
▪ The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator.
▪ When the SS pin is driven high, the SPI Slave will immediately reset the send and receive logic, and drop any partially received data
in the Shift Register

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SPI - Select Slave (SS) Pin Functionality

▪ Master Mode
▪ When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
▪ If SS is configured as an output, the pin is a general output pin which does not affect the SPI system.
▪ Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master
SPI operation.
▪ If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the
SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it.
▪ To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system
becomes a slave.
▪ As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs. 2. The SPIF Flag in SPSR is set, and if the SPI
interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed.
▪ Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possibility that SS is driven low, the
interrupt should always check that the MSTR bit is still set.
▪ If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master mode.

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SPI Registers Descriptions

▪ SPI Control Register – SPCR

▪ Bit 7 – SPI Interrupt Enable(SPIE)
▪ This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set.
▪ Bit 6 – SPI Enable (SPE)
▪ When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
▪ Bit 5 – Data Order (DORD)
▪ When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is
transmitted first.
▪ Bit 4 – Master/Slave Select (MSTR)
▪ This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low
while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode.
▪ Bit 3 – Clock Polarity (CPOL)
▪ When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
▪ Bit 2 – Clock Phase (CPHA)
▪ The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK.

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SPI Registers Descriptions

▪ SPI Status Register – SPSR

▪ Bit 7 – SPI Interrupt Flag (SPIF)
▪ When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled.
▪ If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
▪ SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
▪ Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
▪ Bit 6 – Write Collision Flag (WCOL)
▪ The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
▪ The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
▪ Bit 5:1 – Reserved Bits
▪ These bits are reserved bits in the ATmega32 and will always read as zero.
▪ Bit 0 – Double SPI Speed Bit (SPI2X)
▪ When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode
▪ This means that the minimum SCK period will be two CPU clock periods.
▪ When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower.
▪ The SPI interface on the ATmega32 is also used for program memory and EEPROM downloading or uploading.

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SPI Registers Descriptions

▪ SPI Data Register – SPDR

▪ The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register.
▪ Writing to the register initiates data transmission.
▪ Reading the register causes the Shift Register Receive buffer to be read.

2nd Monday 3-4 Test 2

1st Opp Test 3 Thursday
2nd Opp Monday
Optional Thursday

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 THANK YOU

Andries Po tgieter Blvd. Vanderbij lpark, 1900, So uth Africa | T 098 008 8900 | E [email protected]. za www.vut.ac.za
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