Journal of Circuits, Systems, and Computers

by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

Vol. 29, No. 7 (2020) 2050109 (10 pages)

.c World Scienti¯c Publishing Company
#
DOI: 10.1142/S0218126620501091

A New Capacitance Multiplier Structure with High

Multiplication Factor for Ultra-Low-Frequency
Filter in Biomedical Applications¤

Yan Li†
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

School of Applied Science, Beijing Information

Science and Technology University,
No. 12 Xiaoying East Road, Qinghe, Haidian District,
Beijing 100192, P. R. China
ly [email protected]

Yong Liang Li
Integrated Circuit Advanced Process Center,
Institute of Microelectronics, Chinese Academy of Sciences,
3 Beitucheng West Road, Chaoyang District,
Beijing 100029, P. R. China
[email protected]

Received 10 May 2019

Accepted 5 August 2019
Published 11 September 2019

A novel capacitance multiplier is proposed to implement an ultra-low-frequency ¯lter for

physiological signal processing in biomedical applications. With the proposed multiplier, a
simple ¯rst-order low-pass ¯lter achieves a
3-dB frequency of 33.4
Hz with a 1-pF capacitance
and a 20 k
resistance. This corresponds to a multiplication factor of as large as 2:4  10 11 . By
changing the controlling terminal, the
3-dB frequency can be tuned in a wide range of
33.4
Hz–6.3 kHz.

Keywords: Capacitance multiplier; ultra-low frequency; biomedical applications.

1. Introduction
Integrated circuits are more and more widely used in biomedical ¯elds to process
physiological signals of ultra-low frequency.1,2 Many groups have started to do re-
search in this domain. Ferri and co-workers proposed a low-power low-frequency
analog front-end used in portable apparatus.3,4 Zhang and co-workers did a lot of
work in designing low-frequency physiological signal, such as photoplethysmographic
*This paper was recommended by Regional Editor Piero Malcovati.
† Corresponding author.

2050109-1
 Y. Li & Y. L. Li
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

signal and ECG signal, processing circuit in wearable devices.5–7 Galup-Montoro and
co-workers made great e®ort in implantable application.8,9 In these biomedical
applications, low-frequency ¯lters are needed, which are characterized with large
capacitance and resistance.10 These large passive components will occupy large chip
area that should be avoided in integrated circuits design. In previous works, various
techniques had been proposed to implement large capacitances for low-frequency
operation. The impedance scaler proposed by Silva-Martinez has been adopted in
many designs.11–13 However, the multiplication factor of the structure is proportional
to the ratio of a current mirror, which will result in large current and power con-
sumptions when a large multiplication factor is needed. In addition, a tunable
multiplication factor is often required to get controllable equivalent capacitance and
cuto® frequency. But the multiplication factor in this structure is ¯xed. Brînzoi et al.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

proposed an unbalanced structure with a tunable multiplication factor.14 However,

the tunable range is small. Bonteanu improved the structure. By using a 10-pF
capacitance and a 20-k
resistance, a 3–345-kHz cuto® frequency is achieved. The
tunable range is improved, but the multiplication factor is still not high enough.15
Germanovix et al. got a 0.3-Hz cuto® frequency by using a 7-pF capacitance. The
multiplication factor is increased under low power consumption, but the tunable
range still needs to be further improved.16 Some other researchers also did useful
works.17–19 However, a more e®ective method of getting a high multiplication factor
and a wide tunable range under low power consumption is yet to be obtained.
In this paper, a new capacitance multiplier is proposed. A high multiplication
factor is achieved by using the ratio of two resistances, which are implemented by
MOSFETs. Furthermore, a tunable multiplication factor is obtained by changing the
gate voltage of the MOSFETs. An ultra-wide tunable range can be achieved by
setting the circuit in di®erent working modes.

2. Circuit Description
The schematic of the proposed capacitance multiplier is shown in Fig. 1. A1 and A2
are the ampli¯ers with high gain, having the schematic shown in Fig. 2, IN1–IN4 are
inverters and VC11 , VC12 , VC20A , VC20B , VC20C , VC20D , VC21 and VC22 are the controlling
terminals. The equivalent capacitance seen from node X can be expressed as
Rtu1 Rtu2
Ceq ¼ C; ð1Þ
R1 R2
where C is the original capacitance which will be multiplied, Rtu1 is the equivalent
resistance of the dot-dashed line part and Rtu2 is the equivalent resistance of the
dashed line part. By keeping R1 and R2 small as well as setting Rtu1 and Rtu2 much
larger than R1 and R2 , a large multiplication factor can be achieved. M1 –M8 are MOS
bipolar pseudo-resistors,20 which can provide large equivalent resistance. In this way, a
large Rtu2 will be achieved, which will result in a high multiplication factor.

2050109-2
 A New Capacitance Multiplier Structure with High Multiplication Factor
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Fig. 1. The proposed capacitance multiplier.

Fig. 2. The schematic of the ampli¯er in the proposed capacitance multiplier.

The multiplier will work in two modes, i.e., ultra-high multiplication mode and
normal multiplication mode. In the ultra-high multiplication mode, the controlling
terminals VC11 and VC20A /VC20B /VC20C /VC20D will work. Speci¯cally, in the Rtu2 part,
one of the four channels of A–D will be enabled by setting only one of the controlling
terminals VC20A , VC20B , VC20C and VC20D to be at a high level. The other channels of
A–D, VC21 and VC22 will be disabled by connecting them to low level. And these four
pairs of MOSFETs have di®erent dimensions to get di®erent equivalent resistances,
which will result in di®erent ranges of multiplication factor. The four pairs of MOS
bipolar pseudo-resistors are connected in series instead of parallel. Because when
they are connected in parallel, the equivalent resistances of disabled pairs and en-
abled pairs are almost in the same magnitude for the high resistance of MOS bipolar
pseudo-resistors. As a result, the tuning structure will not take e®ect. At the same

2050109-3
 Y. Li & Y. L. Li
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

time, in the Rtu1 part, VC11 will be tuned to set a tunable multiplication factor and
VC12 is connected to be at a low level to be disabled. For the normal multiplication
mode, VC22 or VC21 will be enabled, VC20A , VC20B , VC20C and VC20D are disabled and
VC12 will be used to tune the multiplication factor. In this mode, VC20A , VC20B , VC20C
and VC20D are connected to be at high level instead of low level, because the high
resistance will not in°uence the lower resistance of VC21 or VC22 when they are in
parallel together. However, if VC20A , VC20B , VC20C and VC20D are connected to be at
low level, M20a , M20b , M20c and M20d will be enabled, this low-resistance channel will
in°uence the function of VC21 or VC22 or even disable them. The MOSFETs M11 , M12 ,
M21 and M22 can be set in subthreshold region or linear region to get di®erent levels
of multiplication factor.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

3. Simulation Results
The circuit was implemented in SMIC 0.18-
m CMOS process with a supply voltage
of 1.8 V. The dimensions of the components in the circuits in Figs. 1 and 2 are shown
in Table 1.
The proposed circuit is connected with a resistor of 20 k
to get a ¯rst-order low-
pass ¯lter to test the multiplication factor.
In the ultra-high multiplication mode, A-channel works with the conditions
of VC12 ¼ GND, VC21 ¼ VC22 ¼ GND, VC20A ¼ 1:8 V and VC20B ¼ VC20C ¼ VC20D ¼
GND. The cuto® frequency will be tunable by changing VC11 . The frequency response
curves of the ¯lter under di®erent VC11 are shown in Fig. 3. We can see that when
VC11 is tuned in the range of 1.3–1.8 V, the cuto® frequency of the ¯lter changes from
33.4 uHz to 0.4 Hz. M11 works in subthreshold region when VC11 is in the range of 1.3–
1.5 V and works in linear region when VC11 is in the range of 1.6–1.8 V. As we know, a

Table 1. The dimensions of the components in the proposed capacitance

multiplier.

Component Dimension/Value Component Dimension/Value

M1 /M2 /M20A /M20a 0.23
m/9.9
m M11 2
m/2
m
M3 /M4 /M20B /M20b 5
m/0.3
m M12 20
m/1
m
M5 /M6 /M20C /M20c 20
m/0.3
m M21 1
m/8
m
M7 /M8 /M20D /M20d 80
m/0.3
m M22 14
m/5
m
R1 8.6 k
C 1 pF
R2 2.5 k
MR 0.89
m/0.3
m
Ma 0.23
m/9.9
m MA1 /MA2 25
m/1
m
Mb 0.23
m/9.9
m MA3 /MA4 0.46
m/9.9
m
MI0 0.23
m/9.9
m MA5 1.2
m/1.2
m
MI1 0.23
m/9.9
m MA6 1.87
m/1
m
MI2 0.23
m/9.9
m MA7 0.35
m/3
m
MI3 0.23
m/9.9
m MA8 0.23
m/9.9
m
MI4 0.23
m/9.9
m MA9 0.23
m/9.9
m
MI5 0.23
m/9.9
m MA10 /MA11 0.25
m/9.9
m
MI6 3
m/0.3
m CC 0.25 pF

2050109-4
 A New Capacitance Multiplier Structure with High Multiplication Factor
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Fig. 3. The simulated frequency response curves of the ¯lter under di®erent VC11 (A-channel).

20-k
resistance and a 1-pF capacitance will result in a cuto® frequency of 8.0 MHz.
So, the corresponding multiplication factor of this mode is 2:4  10 11 –2  10 7 .
In the ultra-high multiplication mode, by enabling di®erent high-resistance
channels, the cuto® frequency ranges can be chosen. By tuning VC11 , the speci¯c
cuto® frequency can be controllable. The curves of simulated cuto® frequency of the
¯lter versus VC11 when di®erent channels are working are shown in Fig. 4. When M3
and M4 work, i.e., B-channel is enabled, the resulted cuto® frequency is 4.9 mHz–
10.6 Hz. When M5 and M6 work, i.e., C-channel is enabled, the resulted cuto® fre-
quency is 17.3 mHz–44.9 Hz. When M7 and M8 work, i.e., D-channel is enabled, the
resulted cuto® frequency is 69.1 mHz–192.1 Hz.
In the normal multiplication mode, M12 and M21 work with the conditions of
VC11 ¼ GND, VC22 ¼ GND, VC20A ¼ VC20B ¼ VC20C ¼ VC20D ¼ 1:8 V and VC21 ¼
1:3 V. The cuto® frequency will be tunable by changing VC12 . As shown in Fig. 5,

Fig. 4. The simulated cuto® frequency of the ¯lter versus VC11 when di®erent high-resistance channels are
enabled.

2050109-5
 Y. Li & Y. L. Li
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

Fig. 5. The simulated frequency response curves of the ¯lter under di®erent VC12 in the normal multi-
plication mode (M21 works).
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Fig. 6. The simulated cuto® frequency of the ¯lter versus VC12 when M21 or M22 is enabled.

when VC12 is tuned in the range of 1.3–1.6 V, the cuto® frequency of the ¯lter changes
from 0.7 Hz to 827.1 Hz.
In the normal multiplication mode, M12 and M22 work with the conditions of
VC11 ¼ GND, VC21 ¼ GND, VC20A ¼ VC20B ¼ VC20C ¼ VC20D ¼ 1:8 V and VC22 ¼
1:3 V. The cuto® frequency will be tunable by changing VC12 . When VC12 is tuned in
the range of 1.3–1.6 V, the cuto® frequency of the ¯lter changes from 10.4 Hz to
6.3 k Hz. The simulated cuto® frequency of the ¯lter versus VC12 when M21 or M22 is
working is shown in Fig. 6.
As a result, by working in di®erent modes and changing the controlling terminal,
the
3-dB frequency can be tuned in a large range of 33.4
Hz–6.3 k Hz as shown in
Table 2.
For the above simulations, the temperature is set as 27  C. To see the temperature
performance of the circuit, AC analysis under di®erent temperatures in the ultra-
high working mode with A-channel working is done. As shown in Fig. 7, the cuto®
frequency of the ¯lter varies with the temperature and just changes much when the
temperature is as high as 80  C. However, the proposed circuit will be used in normal
temperature in daily life. The cuto® frequency changes slightly in this range. So, we

2050109-6
 A New Capacitance Multiplier Structure with High Multiplication Factor
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

Table 2. Working modes and their cuto® frequency range.

Working mode Controlling terminals Frequency range

Ultra-high multiplication mode VC11 , VC20A 33.4
Hz–0.4 Hz
VC11 , VC20B 4.9 mHz–10.6 Hz
VC11 , VC20C 17.3 mHz–44.9 Hz
VC11 , VC20D 69.1 mHz–192.1 Hz
Normal multiplication mode VC12 , VC21 0.7 Hz–827.1 Hz
VC12 , VC22 10.4 Hz–6.3 kHz
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Fig. 7. The simulated cuto® frequencies of the ¯lter under di®erent temperatures.

can see that the temperature performance of the circuit is able to meet the
requirements.
In the ultra-high working mode with A-channel working, AC analysis with corner
conditions has also been done as shown in Fig. 8. The TT simulation result is also
shown in the diagram to do the comparison. The cuto® frequency varies under

Fig. 8. The simulated cuto® frequencies of the ¯lter with di®erent corner conditions.

2050109-7
 Y. Li & Y. L. Li
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

Table 3. Summary of performance comparison.

Max
Power Supply Basic multiplication
consumption Frequency range voltage Process capacitance Factor Source
— 3–345 kHz 1.8-V 0.18-
m CMOS 10 pF 265 Ref. 15
175 nW 0.3–7.5 Hz 1.2-V 65-
m CMOS 7 pF — Ref. 16
12.38
W 35 Hz/150 Hz/ 1.8-V 0.18-
m CMOS 21.36 pF/ — Ref. 17
250 Hz 5.405 pF/3.5 pF
— 180
Hz–241 mHz 1.2-V 0.35-
m CMOS 200 pF — Ref. 18
1.32 mW 131 Hz 1.3-V 0.5-
m CMOS 25 pF 28 Ref. 19
1.38
W 33.4
Hz–6.3 kHz 1.8-V 0.18-
m CMOS 1 pF 2.4  10 11 This work

di®erent corners. The simulated cuto® frequencies are 12.2, 32.9, 227.1, 756.1
Hz
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

and 18.1 mHz with the conditions of SNFP, TT, FNSP, SS and FF.
Summary of performance comparison with the other similar works is shown in
Table 3. The mutiplier proposed in this paper is excellent in terms of the mutipli-
cation factor and tunable range. The power consumption can be improved in the
future work. In this circuit, the two ampli¯ers consume most of the power. In the
next step, ultra-low-power ampli¯er can be designed and used in this architecture to
decrease the power consumption.

4. Conclusion
A new capacitance multiplier is proposed. With the proposed multiplier, a simple
low-pass ¯lter achieves a
3-dB frequency of 33.4
Hz with a 1-pF capacitance and a
20-k
resistance. This corresponds to a multiplication factor of as large as 2:4  10 11 .
By changing the controlling terminal, the
3-dB frequency can be tuned widely from
33.4
Hz to 6.3 kHz.

Acknowledgments
The authors are grateful to the reviewers for their constructive comments and
valuable inputs, which were useful in improving the quality of this paper. This work
was supported by the National Natural Science Foundation of China (Grant No.
61604014) and Scienti¯c Research Projects of Beijing Municipal Education Com-
mission (Grant No. 71E1810981).

References
1. X. F. Teng, Y. T. Zhang, C. C. Y. Poon and P. Bonato, Wearable medical systems for
p-health, IEEE Rev. Biomed. Eng. 1 (2008) 62–74, doi: 10.1109/RBME.2008.2008248.
2. C. C. Y. Poon and Y. T. Zhang, Perspectives on high technologies for low-cost healthcare,
IEEE Eng. Med. Biol. 27 (2008) 42–47, doi: 10.1109/MEMB.2008.923955.

2050109-8
 A New Capacitance Multiplier Structure with High Multiplication Factor
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

3. V. Stornelli and G. Ferri, A single current conveyor-based low voltage low power boot-
strap circuit for ElectroCardioGraphy and ElectroEncephaloGraphy acquisition systems,
Analog Integr. Circuits Signal Process. 79 (2014) 171–175, doi: 10.1007/s10470-013-
0252-2.
4. V. Stornelli, L. Pantoli, G. Leuzzi and G. Ferri, Fully di®erential DDA-based ¯fth and
seventh order Bessel low pass ¯lters and bu®ers for DCR radio systems, Analog Integr.
Circuits Signal Process. 75 (2013) 305–310, doi: 10.1007/s10470-013-0051-9.
5. Y. Li, A. K. Y. Wong and Y. T. Zhang, Fully-integrated transimpedance ampli¯er for
photoplethysmographic signal processing with two-stage Miller capacitance multiplier,
Electron. Lett. 46 (2010) 745–746, doi: 10.1049/el.2010.0868.
6. A. K. Y. Wong, K. N. Leung, K. P. Pun and Y. T. Zhang, A 0.5Hz highpass cuto® dual-
loop transimpedance ampli¯er for wearable NIR sensing device, IEEE Trans. Circuits
Syst. II 57 (2010) 531–535, doi: 10.1109/tcsii.2010.2048401.
7. A. K. Y. Wong, K. P. Pun, Y. T. Zhang and K. Hung, A near-infrared heart rate
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

measurement IC with very low cuto® frequency using current steering technique, IEEE
Trans. Circuits Syst. I 52 (2005) 2642–2647, doi: 10.1109/tcsii.2010.2048401.
8. A. Arnaud, R. Fiorell and C. Galup-Montoro, Nanowatt, sub-ns OTAS, with sub-10-mv
input o®set, using series-parallel current mirrors, IEEE J. Solid-State Circuits 41 (2006)
2009–2018, doi: 10.1109/JSSC.2006.880606.
9. A. Arnaud and C. Galup-Montoro, Pico-A/V range CMOS transconductors using series-
parallel current division, Electron. Lett. 39 (2003) 1295–1296, doi: 10.1049/el:20030840.
10. Y. Li, C. C. Y. Poon and Y. T. Zhang, Analog integrated circuits design for processing
physiological signals, IEEE Rev. Biomed. Eng. 3 (2010) 93–105, doi: 10.1109/
RBME.2010.2082521.
11. J. Silva-Martinez and A. Vazquez-Gonzalez, Impedance scalers for IC active ¯lters,
Proc. Int. Sym. IEEE Circuits and Systems (IEEE, Monterey, CA, 1998), pp. 151–154.
12. S. Solis-Bustos, J. Silva-Martínez, F. Maloberti and E. S anchez-Sinencio, A 60-dB
dynamic-range CMOS sixth-order 2.4-Hz low-pass ¯lter for medical applications, IEEE
Trans. Circuits Syst. II 47 (2000) 1391–1398, doi: 10.1109/82.899631.
13. C. L. Hsu, M. H. Ho, Y. K. Wu and T. H. Chen, Design of low-frequency low-pass ¯lters
for biomedical applications, Proc. IEEE Asia Paci¯c Conf. Circuits and Systems (IEEE,
Singapore, 2006), pp. 690–695.
14. P. Brînzoi, A. Cracan and N. Cojan, A new approach in designing electrically controlled
capacitance multipliers, Proc. Int. Symp. Signals, Circuits and Systems (IEEE, Iaşi,
2011), pp. 1–4.
15. G. Bonteanu, A wide range ¯ne tuning capacitance multiplier, Proc. IEEE 23rd Int.
Symp. Design and Technology in Electronic Packaging (SIITME) (IEEE, Constanţa,
Romania, 2017), pp. 122–125.
16. W. Germanovix, B. Edoardo and M. Franco, Capacitance super multiplier for sub-
hertz low-pass integrated ¯lters, IEEE Trans. Circuits Syst. II, Express Briefs 65 (2017)
301–305, doi: 10.1109/TCSII.2017.2691010.
17. T. Zhao, X. Liu, G. H. Zhang and Y. L. Su, Design of a programmable and low-frequency
¯lter for biomedical signal sensing applications, Proc. 9th Int. Congr. Image and Signal
Processing, BioMedical Engineering and Informatics (IEEE, Datong, China, 2016),
pp. 1746–1750.
18. M. R. Dar, N. A. Kant, F. A. Khanday and C. Psychalinos, Fractional-order ¯lter design
for ultra-low frequency applications, Proc. IEEE Int. Conf. Recent Trends in Electronics
Information Communication Technology (IEEE, India, 2016), pp. 1727–1730.

2050109-9
 Y. Li & Y. L. Li
by BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY on 11/01/19. Re-use and distribution is strictly not permitted, except for Open Access articles.

19. P.-C. Ivan and P. M. Furth, Enhanced grounded capacitor multiplier and its °oating
implementation for analog ¯lters, IEEE Trans. Circuits Syst. II, Express Briefs 62 (2015)
962–966, doi: 10.1109/TCSII.2015.2435751.
20. R. R. Harrison and C. Charles, A low-power, low-noise CMOS ampli¯er for neural
recording applications, IEEE J. Solid-State Circuits 38 (2003) 958–965, doi: 10.1109/
ISCAS.2002.1010674.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

2050109-10