Arithmetic and Logic

Chapter 5

The AVR microcontroller

and embedded
systems
using assembly and c

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 Topics
• Arithmetic instructions
• Logic and compare instructions
• Rotate and shift instructions and data serialization
• BCD and ASCII conversion

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 Arithmetic instructions – summary
• Addition:
– ADD, ADC, ADIW
• Subtraction:
– SUB, SBC, SBCI, SBIW
• Increment/Decrement: INC, DEC
• Multiplication:
– MUL, MULS, MULSU, FMUL, FMULS, FMULSU

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 Data Processing: Arithmetic-ADD
• Add without carry: ADD Rd, Rr
Rd ← Rd + Rr where 0 ≤ d ≤ 31 , 0 ≤ r ≤31
• Adds two registers without the C flag and places the result
in the destination register Rd.
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example :
ADD R1, R2 ;ADD R2 to R1 (r1  r1+r2)
ADD R28,R28 ;ADD R28 to itself (R28  R28 + R28)

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 Data Processing: Arithmetic-ADD
Show the status of the C, H and Z flags after the addition
of 0x38 and 0x2F in the following instructions:

LDI R16, 0x38

LDI R17, 0x2F
ADD R16, R17
Solution:
$38 0011 1000
+ $2F 0010 1111 R16 = 0x67
R16 $67 0110 0111

C = 0 because there is no carry beyond the bit7

H = 1 because there is a carry from the bit 3 to bit 4
Z = 0 because the R16 (the result) has a value other than
0 after the addition.
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 Data Processing: Arithmetic-ADD
Show the status of the C, H and Z flags after the addition of
0x9C and 0x64 in the following instructions:

LDI R20, 0x9C

LDI R21, 0x64
ADD R20, R21 ;add R21 to R20

Solution:
$9C 1001 1100
+ $64 0110 0100 R20 = 0x00
R20 $100 0000 0000

C = 1 because there is a carry beyond the bit7

H = 1 because there is a carry from the bit 3 to bit 4
Z = 1 because the R20 (the result) has a value of 0 after
the addition.
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 ADD - Example

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 ADD - Example

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 Data Processing: Arithmetic-ADC
• Add with carry: ADC Rd, Rr
Rd ← Rd + Rr +C where 0 ≤ d ≤ 31 , 0 ≤ r ≤31
• Adds two registers and the contents of the C flag
and places the result in the destination register Rd
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example : (Add R1:R0 to R3:R2)
ADD R2, R0 ;Add low byte
ADC R3, R1 ;Add with carry high byte

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 Data Processing: Arithmetic-ADC

Example 5-3: Write a program to add two 16-bit

numbers. The numbers are $3CE7 and $3B8D.
Assume that R1 = $8D, R2 = $3B, R3 = $E7, and R4
= $3C. Place sum in R3 and R4; R3 should have the
lower byte

Solution:

ADD R3, R1
ADC R4, R2

Notice: Use
AVR Microcontroller ADD
and Embedded forAssembly
System Using lower and C byte and ADC for the higher byte
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 Data Processing: Arithmetic-ADIW
• Add immediate to word: ADIW Rd+1:Rd, K
Rd+1:Rd ← Rd+1:Rd + K where d  {24,26,28,30}, 0 ≤ K ≤ 63
• Adds an immediate value (0-63) to a register pair and places
the result in the register pair.
• This instruction operates on the upper four register pairs, and is
well suited for operations on the pointer registers.
• Flags affected : S, V, N, Z, C
• CPU Cycle : 2
Example :
ADIW R25:R24, 1 ;Add 1 to R25:R24
ADIW ZH:ZL, 63 ;Add 63 to the Z-pointer (R31:R30)

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 Data Processing: Arithmetic-ADIW

LDI ZL, 13 • 26 is added to ZL

• If the result is > 255 the carry bit is
LDI ZH, 53 set, and ZH incremented by 1
ADIW ZH:ZL, 26 • If ZH is > 255, the carry bit in the
SREG is set
Solution
• ZL = 13 = 0b 0000 1101
• ZH = 53 = 0b 0011 0101
After adding 26 = 0b 0001 1010
• ZL = 13 + 26 = 39 = 0b 0010 0111 is < 255, the carry
bit will not set
• ZH = 53 = 0b 0011 0101 unchanged and the carry bit
in SREG is not set
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 Data Processing: Arithmetic-SUB

• Subtract without carry: SUB Rd, Rr

Rd ← Rd – Rr where 0 ≤ d ≤ 31 , 0 ≤ r ≤31
• Subtracts two registers and places the
result in the destination register Rd
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example :
SUB R13, R12 ;Subtract r12 from r13

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 Subtraction using addition with 2’s complement

AVR uses adder circuitry to perform the subtraction command.

Assuming that the AVR is executing a simple subtract instruction
and that C = 0 prior to the execution of the instruction, one can
summarize the steps of the hardware of the CPU in executing the
SUB instruction for unsigned numbers as follows:

1.Take the 2's complement of the subtrahend (right-hand operand).

2. Add it to the minuend (left-hand operand).
3. Invert the carry.

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 Data Processing: Arithmetic-SUB

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 Data Processing: Arithmetic-SUBI
• Subtract Immediate: SUBI Rd, K
Rd ← Rd – K where 16 ≤ d ≤ 31 , 0 ≤ K ≤ 255
• Subtract a register and a constant and places
the result in the destination register Rd.
• This instruction works on register R16 to R31
and is very well suited for operations on the X,
Y and Z pointers.
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example :
SUBI R17, $11 ;Subtract $11 from R17
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 SUBI - Example

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 Data Processing: Arithmetic-SBC
• Subtract with carry: SBC Rd, Rr
Rd ← Rd – Rr – C where 0 ≤ d ≤ 31 , 0 ≤ r ≤31
• Subtracts two registers and subtracts with the
C flag and places the result in the destination
register Rd.
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1

Example : (Subtract r1:r0 from r3:r2)

SUB R2, R0 ;Subtract low byte
SBC R3, R1 ;Subtract with carry high byte
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 Data Processing: Arithmetic-SBC

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 Data Processing: Arithmetic-SBCI
• Subtract immediate with carry: SBCI Rd, K
Rd ← Rd – K – C where 16 ≤ d ≤ 31 , 0 ≤ K ≤ 255
• Subtracts a constant from a register and subtracts
with the C flag and places the result in the
destination register Rd.
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example : Subtract $4F23 from r17:r16
SUBI R16, $23 ;Subtract low byte
SBCI R17, $4F ;Subtract with carry high byte

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 Data Processing: Arithmetic-SBIW
• Subtract immediate from word: SBIW Rd+1:Rd, K
Rd+1:Rd ← Rd+1:Rd – K where d  {24,26,28,30}, 0 ≤ K ≤ 63
• Subtracts an immediate value (0-63) from a register pair and
places the result in the register pair.
• This instruction operates on the upper four register pairs, and is
well suited for operations on the pointer registers.
• Flags affected : S, V, N, Z, C
• CPU Cycle : 2
Example :
SBIW R25:R24, 1 ;Subtract 1 from r25:r24
SBIW YH:YL, 63 ;Subtract 63 from the Y-pointer

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 SBIW - Example

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 Data Processing: Arithmetic-INC
• Increment: INC Rd
Rd ← Rd + 1 where 0 ≤ d ≤ 31
• Adds one to the contents of register Rd and places the result
in the destination register Rd.
• The C flag in SREG is not affected by the operation, thus
allowing the INC instruction to be used on a loop counter in
multiple-precision computations.
• Flags affected : S, V, N, Z
• CPU Cycle : 1
Example :
LDI R22, $19 ; move $19 to R22 (R22=$19)
INC R22 ; increment R22 (R22=$1A)

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 Data Processing: Arithmetic-DEC
• Decrement: DEC Rd
Rd ← Rd – 1 where 0 ≤ d ≤ 31
• Subtracts one from the contents of register Rd and places
the result in the destination register Rd.
• The C flag in SREG is not affected by the operation, thus
allowing the DEC instruction to be used on a loop counter in
multiple-precision computations.
• Flags affected : S, V, N, Z
• CPU Cycle : 1
Example :
LDI R22, $19 ; move $19 to R22 (R22=$19)
DEC R22 ; decrement R22 (R22=$18)

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 Data Processing: Arithmetic-DEC
Show the status of the Z flag during the execution of the following
program:
LDI R20, 4 ;R20 = 4
DEC R20 ;R20 = R20 -1
DEC R20 ;R20 = R20 -1
DEC R20 ;R20 = R20 -1
DEC R20 ;R20 = R20 -1
Solution:
The Z flag is one when the result is zero. Otherwise, it is cleared (zero).
Thus: After Value of R20 The Z flag
LDI R20, 4 4 0
DEC R20 3 0
DEC R20 2 0
DEC R20 1 0
DEC R20 0 1
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 Data Processing: Arithmetic-MUL
• Multiply unsigned: MUL Rd, Rr
R1:R0 ← Rd x Rr (unsigned ← unsigned x unsigned) where 0 ≤ d ≤ 31 , 0 ≤ r ≤ 31
• This instruction performs 8bit x 8 bit → 16bit unsigned multiplication.
• The multiplicand Rd and the multiplier Rr are two registers containing
unsigned numbers.
• The 16 bit unsigned product is placed in R1(high byte) and R0(low byte).
• Flags affected : Z, C
• CPU Cycle : 2
Example :
MUL R5, R4 ;Multiply unsigned R5 and R4
MOV R5, R1
MOV R4, R0 ;Copy result back in R5:R4

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 Data Processing: Arithmetic-MULS
• Multiply signed: MULS Rd, Rr
R1:R0 ← Rd x Rr (signed ← signed x signed) where 16 ≤ d, r ≤ 31
• This instruction performs 8bit x 8 bit → 16bit signed multiplication.
• The multiplicand Rd and the multiplier Rr are two registers
containing signed numbers.
• The 16 bit signed product is placed in R1(high byte) and R0(low
byte).
• Flags affected : Z, C
• CPU Cycle : 2
Example :
MULS R5, R4 ;Multiply signed R5 and R4
MOVW R5:r4, R1:R0 ;Copy result back in R5:R4

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 Data Processing: Arithmetic-MULSU
• Multiply signed with unsigned: MULSU Rd, Rr
R1:R0 ← Rd x Rr (signed ← signed x unsigned) where 16 ≤ d, r ≤ 31
• This instruction performs 8bit x 8 bit → 16bit signed multiplication
of a signed and an unsigned number.
• The multiplicand Rd and the multiplier Rr are two registers.
• The multiplicand Rd is a signed number and the multiplier Rr is
unsigned.
• The 16 bit signed product is placed in R1(high byte) and R0(low
byte).
• Flags affected : Z, C
• CPU Cycle : 2
Example :
MULSU R5, R4 ;Multiply signed R5 and unsigned R4
MOVW R5:R4, R1:R0 ;Copy result back in R5:R4
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Data Processing: Arithmetic-Division

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 An application for division
• Sometimes a sensor is connected to an ADC (analog-to-
digital converter) and the ADC represents some quantity such
as temperature or pressure. The 8-bit ADC provides data in
hex in the range of 00-FFH. This hex data must be converted
to decimal. We do that by dividing it by 10 repeatedly, saving
the remainders, as shown in Examples 5-8 and 5-9.
• Example 5-8
Assume that the data memory location 0x315 has value FD
(hex). Write a program to convert it to decimal. Save the
digits in locations 0x322, 0x323, and 0x324, where the least-
significant digit is in location 0x322.

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 Example 5-8 (1/2)

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 Example 5-8 (2/2)

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 Example 5-9

Analyze the program in Example 5-8 for a numerator of 253.

Solution:
To convert a binary (hex) value to decimal, we divide it by 10
repeatedly until the quotient is less than 10. After each division
the remainder is saved. In the case of an 8-bit binary, such as
FDH, we have 253 decimal, as shown below.
Quotient Remainder
253/10 25 3 (low digit)
25/10 2 5 (middle digit)
2 (high digit)
Therefore, we have FDH = 253.

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 Data Processing: Arithmetic-FMUL
• Fractional Multiply Unsigned : FMUL Rd, Rr
R1:R0 ← Rd x Rr ; unsigned(1.15) ← unsigned (1.7) x unsigned (1.7)
where 16 ≤ d,r ≤ 23
• This instruction performs 8bit x 8 bit → 16bit unsigned multiplication.
• The multiplicand Rd and the multiplier Rr are two registers containing
unsigned numbers.
• The 16 bit unsigned product is placed in R1(high byte) and R0(low byte).
• Flags affected : Z, C
• CPU Cycle : 2
Example :
MUL R5, R4 ;Multiply unsigned R5 and R4
MOV R5, R1
MOV R4, R0 ;Copy result back in R5:R4

Let (N.Q) denote a fractional number with N binary digits left of the radix point, and
Q binary digits right of the radix point.
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 FMULS & FMULSU

• FMULS Rd,Rr where 16  d, r  23

R1:R0  Rd x Rr
signed (1.15)  signed (1.7) x signed (1.7)

• FMULSU Rd,Rr where 16  d, r  23

R1:R0  Rd x Rr
signed (1.15)  signed (1.7) x unsigned (1.7)

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 Affected flags with addition/subtraction

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 V flag with signed numbers

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 V Flag - Example

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What is the difference between the N and S flags?
• As we mentioned before, in signed numbers the N flag represents
the D7 bit of the result. If the result is positive, the N flag is zero, and
if the result is negative, the N flag is one, which is why it is called the
Negative flag.

• In operations on signed numbers, overflow is possible. Overflow

corrupts the result and negates the sign bit. So if you ADD two
positive numbers, in case of overflow, the N flag would be 1 showing
that the result is negative!

• The S flag helps you to know the sign of the real result. It checks
the V flag in addition to the D7 bit. If V = 0, it shows that overflow has
not occurred and the S flag will be the same as D7 to show the sign
of the result. If V = 1, it shows that overflow has occurred and the S
flag will be opposite to the D7 to show the sign of the real (not the
corrupted) result. See Example 5-17.
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 S and N flags - example

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 Topics
• Arithmetic instructions
• Logic and compare instructions
• Rotate and shift instructions and data serialization
• BCD and ASCII conversion

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Data Processing: Logic Instructions
• Logic instructions include:
– AND - Bit-wise AND
– OR - Bit-wise OR
– EOR - Bit-wise Exclusive OR
– COM - 1’s Complement of bits of destination
– NEG - 2’s Complement of bits of destination
– CLR – Clear a register
– SER – Set a register
– SBR – Set bit(s) in a register
– CBR – Clear bit(s) in a register
– TST – Test for Zero or Minus
A B A AND B A OR B A EOR B NOT A NOT B
0 0 0 0 0 1 1
0 1 0 1 1 1 0
1 0 0 1 1 0 1
1 1 1 1 0 0 0
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 Data Processing: Logic-AND
• Logical AND: AND Rd, Rr
Rd ← Rd & Rr where 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
• Performs the logical AND between the contents of the
register Rd and register Rr and places the result in the
destination register Rd.
• Flags affected : S, V ← 0, N, Z
• CPU Cycle : 1
Example :
AND R2, R3 ;Bitwise AND R2 and R3, result in R2
LDI R16, 1 ;Set bitmask 0000 0001 in R16
AND R2, R16 ;Isolate bit0 in R2

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 Data Processing: Logic-ANDI
• Logical AND with immediate: ANDI Rd, K
Rd ← Rd & K where 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
• Performs the logical AND between the contents of
the register Rd and a constant and places the result
in the destination register Rd.
• Flags affected : S, V ← 0, N, Z
• CPU Cycle : 1
Example :
ANDI R17, $0F ;Clear upper nibble of R17
ANDI R18, $10 ;Isolate bit4 in R18

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 ANDI - Example

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 Data Processing: Logic-OR
• Logical OR: OR Rd, Rr
Rd ← Rd | Rr where 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
• Performs the logical OR between the contents
of the register Rd and register Rr and places
the result in the destination register Rd.
• Flags affected : S, V ← 0, N, Z
• CPU Cycle : 1
Example :
LDI R16, $0F ;Load R16 with $0F
OR R2, R16 ;Set lower nibble of R2
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 Data Processing: Logic-ORI
• Logical OR with immediate: ORI Rd, K
Rd ← Rd | K where 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
• Performs the logical OR between the contents
of the register Rd and a constant and places
the result in the destination register Rd.
• Flags affected : S, V ← 0, N, Z
• CPU Cycle : 1
Example :
ORI R16, $F0 ;Set high nibble of r16
ORI R17, 1 ;Set bit0 of r17
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 Data Processing: Logic-EOR
• Logical Exclusive OR: EOR Rd, Rr
Rd ← Rd ^ Rr where 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
• Performs the logical Exclusive OR between the
contents of the register Rd and register Rr and
places the result in the destination register Rd.
• Flags affected : S, V, Z ← 0, N, Z
• CPU Cycle : 1
Example :
EOR R4, R4 ;Clear R4
EOR R0, R22 ;Bitwise XOR between R0 and R22

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 EOR - example

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 EOR - example

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 EOR - example

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 Data Processing: Logic- COM
• One’s complement: COM Rd
Rd ← $FF – Rd where 0 ≤ d ≤ 31
• Performs a One’s Complement of register Rd.
• Flags affected : S, V, Z ← 0, C ← 1, N, Z
• CPU Cycle : 1
Example :
com R4 ; Take one’s complement of R4
breq zero ; Branch if zero
...
zero: nop ; Branch destination (do nothing)
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 Data Processing: Logic- NEG
• Two’s complement: NEG Rd
Rd ← $00 – Rd where 0 ≤ d ≤ 31
• Replaces the contents of register Rd with its two’s
complement;
• Flags affected : S, V, Z, C ,H, N, Z
• CPU Cycle : 1
Example :
sub R11,R0 ; Subtract R0 from R11
brpl positive; Branch if result positive
neg R11 ; Take two’s complement of R11
positive: nop ; Branch destination (do nothing)

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 Data Processing: Logic- CLR
• Clear register: CLR Rd
Rd ← Rd  Rd where 0 ≤ d ≤ 31
• Clears a register. This instruction performs an Exclusive OR
between a register and itself. This will clear all bits in the Register
• Flags affected : S  0, V  0 , N  0, Z  1
• CPU Cycle : 1
Example :
clr R18 ; clear R18
loop: inc R18 ; increase R18
...
cpi R18,$50 ; Compare R18 to $50
brne loop
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 Data Processing: Logic- SER
• Set register: SER Rd
Rd ← $FF where 16 ≤ d ≤ 31
• Loads $FF directly to register Rd.
• Flags: unaffected
• CPU Cycle : 1
Example :
clr R16 ; Clear R16
ser R17 ; Set R17
out $18,R16 ; Write zeros to Port B
nop ; Delay (do nothing)
out $18,R17; Write ones to Port B
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 Data Processing: Bit Manipulation - SBR
• Set bits in register
– Rd ← Rd | K
• SBR Rd, K
– 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
• Set specified bits in register Rd.
• Performs the logical ORI between the contents of
register Rd and a content mask K and places the
result in the destination register Rd.
• Flags affected : S, V ← 0, N, Z
• CPU Cycle : 1
Example :
SBR R16, 3 ;Set bits 0 and 1 in r16
SBR R17, $F0 ;Set 4 MSB in r17
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Data Processing: Bit Manipulation - CBR
• Clear bits in register
– Rd ← Rd & ($FF – K)
• CBR Rd, K
– 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
• Clears the specified bits in register Rd.
• Performs the logical AND between the contents of
the register Rd and the complement of the constant
mask K.
• Flags affected : S, V ← 0, N, Z
• CPU Cycle : 1
Example :
CBR R16, $F0 ;Clear upper nibble of r16
CBR R17, 1 ;Clear bit0 in r18
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 Data Processing: Bit Manipulation - TST
• Test for Zero or Minus
– Rd ← Rd & Rd
• TST Rd
– 0 ≤ d ≤ 31
• Tests if a register is zero or negative.
• Performs a logical AND between a register and itself.
• The register will remain unchanged.
• Flags affected : S, V ← 1, N, Z
• CPU Cycle : 1
Example :
TST R0 ;Test r0
BREQ zero ;Branch if r0=0
…..
zero: TST R1 ;Test r1
BRPL Positive
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 Data Processing: SWAP
• Swap nibbles
– Rd(7:4) ← Rd(3:0) , Rd(3:0) ← Rd(7:4)
• SWAP Rd
– 0 ≤ d ≤ 31
• Swaps high and low nibbles in a register
• Flags affected : None
• CPU Cycle : 1
Example :
LDI R16, $04 ;Load R16 with $04
SWAP R16 ;Swap high and low nibble of R16 (R16=$40)

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 Data Processing: NOP
• No operation
• NOP
• This instruction perform a single-cycle No
Operation.
• Used to implement delay for timing purpose.
• Flags affected : None
• CPU Cycle : 1
Example :
CLR R16 ;Clear r16
SER R17 ;Set r17
OUT $18, R16 ;Write zero to Port B
NOP ;Wait (do nothing)
OUT $18, R17 ;Write ones to Port B
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 Compare instructions: CP

• Syntax: CP Rd, Rr
• Operands: Rd  {r0, r1, …, r31}
• Operation: Rd – Rr (Rd is not changed)
• Flags affected: H, S, V, N, Z, C
• Words: 1
• Cycles: 1
• Example:
cp r4, r5 ; Compare r4 with r5
brne noteq ; Branch if r4 ≠ r5
...
noteq: nop ; Branch destination (do nothing

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Compare instructions: CPC (Compare with Carry)

• Syntax: CPC Rd, Rr

• Operands: Rd  {r0, r1, …, r31}
• Operation: Rd – Rr – C (Rd is not changed)
• Flags affected: H, S, V, N, Z, C
• Words: 1
• Cycles: 1
• Example:
; Compare r3:r2 with r1:r0
cp r2,r0 ; Compare low byte
cpc r3,r1 ; Compare high byte
brne noteq ; Branch if not equal
...
noteq: nop ; Branch destination (do nothing
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 Compare instructions: CPI (Compare with Immediate)

• Syntax: CPI Rd, K

• Operands: 16 ≤ d ≤ 31, 0≤ K ≤ 255
• Operation: Rd – K (Rd is not changed)
• Flags affected: H, S, V, N, Z, C
• Words: 1
• Cycles: 1
• Example:
cpi r19,3 ; Compare r19 with 3
brne error ; Branch if r19<>3
...
error: nop ; Branch destination (do nothing)

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 CPSE – Compare Skip if Equal
Description:
This instruction performs a compare between two registers Rd
and Rr, and skips the next instruction if Rd = Rr.
Operation:
If Rd = Rr then PC ← PC + 2 (or 3) else PC ← PC + 1
Syntax:
CPSE Rd,Rr ;where 0 ≤ d ≤ 31, 0 ≤ r ≤ 31

Example:
inc r4 ; Increment r4
cpse r4,r0 ; Compare r4 to r0
neg r4 ; Only executed if r4<>r0
nop ; Continue (do nothing)

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 Conditional branch instructions
• As we studied in Chapter 3, conditional branches alter the flow of control
if a condition is true.
• In the AVR there are at least two conditional jumps for each flag of the
status register. Here we will describe eight of the most important
conditional jumps. Others are similar but of different flags.
• Table 5-2 shows the conditional branch instructions that we will describe
in this section.
AVR Conditional branch instructions

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 BRNE - Example

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 BRLO - Example

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 Ex 5-26 (1/2)

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 Ex 5-26 (2/2)

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 BRVC - Example

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 Topics
• Arithmetic instructions
• Logic and compare instructions
• Rotate and shift instructions and data serialization
• BCD and ASCII conversion

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Data Processing: Shift & Rotate Instructions

• LSL – Logical Shift Left

• LSR – Logical Shift Right

• ASR – Arithmetic Shift Right

• ROL – Rotate Left Through Carry

• ROR – Rotate Right Through Carry

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 Data Processing: Shift & Rotate - LSL
• Logical shift left
– Rd ← Rd << 1
• LSL Rd
– 0 ≤ d ≤ 31
• Shifts all bits in Rd one place to the left.
• Bit0 is cleared and Bit7 is loaded into the C flag of the SREG (Status
Register)
• This operation effectively multiplies signed and unsigned values by
two.
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example :
LDI R0, $04 ;Load R0 with $04
LSL R0 ;Multiply R0 by 2 (R0=$08)

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 Data Processing: Shift & Rotate - LSR
• Logical shift right
– Rd ← Rd >> 1
• LSR Rd
– 0 ≤ d ≤ 31
• Shifts all bits in Rd one place to the right.
• Bit7 is cleared and Bit0 is loaded into the C flag of the SREG
(Status Register)
• This operation effectively divides an unsigned value by two.
• The C flag can be used to round the result.
• Flags affected : S, V, N ← 0, Z, C
• CPU Cycle : 1
Example :
LDI R0, $04 ;Load R0 with $04
LSR R0 ;Divide R0 by 2 (R0=$02)

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 Data Processing: Shift & Rotate - ASR
• Arithmetic shift right
– Rd ← Rd >>> 1
• ASR Rd
– 0 ≤ d ≤ 31
• Shifts all bits in Rd one place to the right.
• MSB is duplicated back into MSB and Bit0 is loaded into the C flag
of the SREG.
• This operation effectively divides an signed value by two without
changing its sign.
• The C flag can be used to round the result.
• Flags affected : S, V, N, Z, C
• CPU Cycle : 1

ASR R0

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 Data Processing: Shift & Rotate - ROL
• Rotate left through carry
• ROL Rd
– 0 ≤ d ≤ 31
• Shifts all bits in Rd one place to the left.
• The C flag is shifted into bit0 of Rd.
• Bit7 is shifted into the C flag.
• This operation combined with LSL effectively multiplies multi-byte
signed and unsigned value by two.
• Flags affected : H, S, V, N, Z, C
• CPU Cycle : 1
Example :
LSL R18 ;Multiply R19:R18 by two
ROL R19 ;R19:R18 is a signed or unsigned word

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 Data Processing: Shift & Rotate - ROL

Example

SEC ;make C = 1 (carry is 0)

LDI R20,0x15 ;R20 = 0001 0101
ROL R20 ;R20 = 0010 1011 C = 0
ROL R20 ;R20 = 0101 0110 C = 0
ROL R20 ;R20 = 1010 1100 C = 0
ROL R20 ;R20 = 0101 1000 C = 1

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 Data Processing: Shift & Rotate - ROR
• Rotate right through carry
• ROR Rd
– 0 ≤ d ≤ 31
• Shifts all bits in Rd one place to the right.
• The C flag is shifted into bit7 of Rd.
• Bit0 is shifted into the C flag. This operation combined with ASR effectively
divides multi-byte signed values by two.
• Combined with LSR, it effectively divides multi-byte unsigned values by two.
• The carry flag can be used to round the result.
• Flags affected : S, V, N, Z, C
• CPU Cycle : 1
Example :
LSR R19 ;Divide R19:R18 by two
ROR R18 ;R19:R18 is an unsigned two-byte integer
ASR R17 ;Divide R17;R16 by two
ROR R16 ;R17:R16 is a signed two-byte integer

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 Serializing Data
• Serializing data is a way of sending a byte of data
one bit at a time through a single pin of
microcontroller
• There are two ways to transfer a byte of data serially
– Using one serial port. In using the serial port, programmers
have very limited control over the sequence of data transfer
– The second method of data transfer is to transfer one bit at
a time and control the sequence of data and space
between them in many new generation of devices such as
LCD, ADC, ROM and the serial versions are becoming
popular because they take less space on a printed circuit
board

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 Sending data serially under program control
• Write a program to transfer the value 41H serially one bit at a
time via pin PB1. Put one high at the start and end of the data ,
send LSB first
SBI DDRB, 1 JMP NEXT
LDI R20, 0x41 ONE: SBI PORTB, 1
CLC NEXT:
LDI R16, 8 DEC R16
SBI PORTB, 1 BRNE AGAIN
AGAIN: SBI PORTB, 1
ROR R20
BRCS ONE HERE: JMP HERE
CBI PORTB, 1

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 Bring Data Serially

CBI DDRC, 1
• Write a program to bring a LDI R16, 8
byte of data serially through LDI R20, 0
pin PC7 and save it in R20 AGAIN:
register. The byte comes in SBIC PINC, 7
LSB first SEC
SBIS PINC, 7
CLC
ROR R20
DEC R16
BRNE AGAIN

HERE: JMP HERE

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 Data Processing: SREG- BSET
• Bit set in SREG
– SREG(s) ← 1
• BSET s
–0≤s≤7
• Sets a single flag or bit in SREG (Status
Register)
• Flags affected : Any of the flags
• CPU Cycle : 1
Example :
BSET 6 ;Set T flag
BSET 7 ;Enable interrupt
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 Data Processing: SREG- BCLR

• Bit clear in SREG

– SREG(s) ← 0
• BCLR s
–0≤s≤7
• Clears a single flag or bit in SREG (Status
Register)
• Flags affected : Any of the flags
• CPU Cycle : 1
Example :
BCLR 0 ;Clear carry flag
BCLR 7 ;Disable interrupts
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 Data Processing: SREG- BST

• Bit store from register to T flag in SREG

– T ← Rd(b)
• BST Rd, b
– 0 ≤ d ≤ 31, 0 ≤ b ≤ 7
• Stores bit b from Rd to the T flag in SREG
(Status Register)
• Flags affected : T
• CPU Cycle : 1
Example : ;Copy bit
BST R1, 2 ;Store bit 2 of R1 in T flag
BLD R0, 4 ;Load T into bit4 of R0
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 Data Processing: SREG- BLD
• Bit load from T flag in SREG to a bit in
register
– Rd(b) ← T
• BLD Rd, b
– 0 ≤ d ≤ 31, 0 ≤ b ≤ 7
• Stores bit b from Rd to the T flag in SREG
(Status Register)
• Flags affected : None
• CPU Cycle : 1
Example :
BST R1, 2 ;Store bit 2 of R1 in T flag
BLD R0, 4 ;Load T into bit4 of R0
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 Data Processing: SREG- SEC

• Set carry flag SEt a flag: SE<flag>

CLear a flag: CL<flag>
–C←1 where <flag> = I, T, H, S, V, N, Z, C
• SEC
• Sets the Carry flag (C) in SREG (Status
Register)
• Flags affected : C
• CPU Cycle : 1
Example :
SEC ;Set Carry flag
ADC R0, R1 ;R0=R0+R1+1
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 Data Processing: SREG- CLC

• Clear carry flag

–C←0
• CLC
• Clears the Carry flag (C) in SREG (Status
Register)
• Flags affected : C
• CPU Cycle : 1
Example :
ADD R0, R0 ;Add R0 to itself
ADC R0, R1 ;Clear Carry flag
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 Data Processing: SREG- SEN
• Set negative flag
–N←1
• SEN
• Sets the Negative flag (N) in SREG (Status
Register)
• Flags affected : N
• CPU Cycle : 1
Example :
ADD R2, R19 ;Add R19 to R2
SEN ;Set Negative flag
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 Data Processing: SREG- CLN
• Clear negative flag
–N←0
• CLN
• Clears the Negative flag (N) in SREG
(Status Register)
• Flags affected : N
• CPU Cycle : 1
Example :
ADD R2, R3 ;Add R3 to R2
CLN ;Clear Negative flag
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 Data Processing: SREG- SEZ
• Set zero flag
–Z←1
• SEZ
• Sets the Zero flag (Z) in SREG (Status
Register)
• Flags affected : Z
• CPU Cycle : 1
Example :
SEZ ;Set Zero flag
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 Data Processing: SREG- CLZ

• Clear zero flag

–Z←0
• CLZ
• Clears the Zero flag (Z) in SREG (Status
Register)
• Flags affected : Z
• CPU Cycle : 1
Example :
CLZ ;Clear zero flag

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 Data Processing: SREG- SEI
• Set global interrupt flag
– I←1
• SEI
• Sets the Global Interrupt flag (I) in SREG (Status
Register)
• The instruction following SEI will be executed
before any pending interrupt.
• Flags affected : I
• CPU Cycle : 1
Example :
SEI ;Set global interrupt flag
SEC ;Set Carry Flag
;Carry flag will set before any pending interrupt
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 Data Processing: SREG- CLI
• Clear global interrupt flag
– I←0
• CLI
• Clears the global interrupt flag (I) in SREG (Status
Register)
• The interrupt will be immediately disable.
• No interrupt will be executed after the CLI instruction,
even if it occur simultaneously with the CLI instruction.
• Flags affected : I
• CPU Cycle : 1
Example :
CLI ; disable interrupts during timed sequence
SBI EECR, EEMWE ; Start EEPROM write
SBI EECR, EEWE ;
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 Topics
• Arithmetic instructions
• Logic and compare instructions
• Rotate and shift instructions and data serialization
• BCD and ASCII conversion

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BCD, Packed BCD and ASCII conversion.
•ASCII
•BCD Codes

BCD Codes
Packed BCD

BCD1 BCD0

ASCII and BCD Codes for Digits 0–9

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 Packed BCD to ASCII conversion
To convert packed BCD to ASCII:
• you must first convert it to unpacked BCD.
• Then the unpacked BCD is tagged with 011 0000
(30H).

Packed BCD = 1001 0010

Un packed BCD = 0000 1001 , 0000 0010

ACSII = 0011 1001 , 0011 0010

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 ASCII to Packed BCD conversion

To convert ASCII to packed BCD, you first convert it to

unpacked BCD (to get rid of the 3), and then combine it to
make packed BCD. For example, for 4 and 7 the keyboard
gives 34H and 37H, respectively. The goal is to produce
47H or “01000111 ", which is packed BCD.

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 ASCII to packed BCD - Example

LDI R21,'4‘ ;load character 4 to R21

LDI R22,'7‘ ; load character 7 to R22
ANDI R21,0x0F ;mask upper nibble of R21
SWAP R21 ;swap nibbles of R21
;to make upper nibble of packed BCD
ANDI R22,0x0F ;mask upper nibble of R22
OR R22,R21 ; join R22 and R21 to make packed BCD
MOV R20,R22 ;move the result to R20

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