Tessent® TestKompress®

Lab 2.1
Tessent TestKompress Integration Flows
Post-Synthesis External Logic Flow

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Tessent TestKompress 2
 Table of Contents
Before you Begin ...............................................................................................................................4

Lab 2.1 Tessent TestKompress Integration Flows – Post-Synthesis External Flow .................................6
Exercise 1: Post Synthesis External Logic Creation .................................................................................. 8

Appendix: Answers to Questions ...................................................................................................... 30

Lab 2.1 .................................................................................................................................................... 30

Tessent TestKompress 3
 Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must download and extract
the lab data as described in the "Obtaining Lab Data section below.

Caution
Whenever you are using the VM for lab exercises and are finished with your session, please use the
"Disconnect" feature of the Desktop Viewer before the VM times out to preserve the data from one
session to the next. Failure to do so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you to follow the download
and extract process. This allows you to "refresh" the lab data so you can go through the labs again
with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables
already setup.

Obtaining Lab Data

If the tk_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the tk_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_tk_data_v2019.1_20190826.tgz,

3. In the resultant window, select the Download button, enable the Save File button, then select the
OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_tk_data_v2019.1_20190826.tgz .

4. In a terminal window, extract the files from the compressed tar file using the command:

tar xzvf ./tessent_tk_data_2019.1. v2019.1_20190826.tgz

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 You should now have a directory named tk_data in your $HOME directory. That directory contains all
the files you need to perform the exercises, in this learning path.

You are now ready to proceed with lab exercises.

Tessent TestKompress 5
 Lab 2.1
Tessent TestKompress Integration
Flows – Post-Synthesis External Flow

This lab introduces the TestKompress external post-synthesis logic creation flow.

In this lab, you start with a gate-level, non-scan netlist, insert scan chains using Tessent Scan, create
Tessent TestKompress (EDT) IP, and then generate and verify test patterns for both compression and
(optional) bypass modes.

Notice that this exercise has its own subdirectory and common directories are used for netlists,
generated files, and transcripts.

Introduction

TestKompress Logic Generation Flows

In this lab, you step through the external post-synthesis flow using pre-defined scripts. During EDT IP
creation, a dofile containing scan chain, EDT setup and test procedure files are automatically generated
Tessent Shell checks out a Tessent TestKompress license for pattern generation in the same manner as
Tessent® FastScan™. The flow for creating compressed pattern uses the same commands as the
uncompressed pattern flow.

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Design
In this lab, you use a Verilog gate level netlist for the Microchip PIC 16CCC5X micro controller. You go
through the design flow from scan insertion to simulation of compressed (EDT) test patterns.

Compression Results
Compression is described in using two terms The compression ratio is equal to
<number of external scan channels> : <number of internal scan chains> . The data compression is
calculated using the results of report_scan_volume for non-compressed patterns, and dividing that by
the results of report_scan_volume for the compressed pattern set. The design used for this lab is very
small; therefore, the compression will be relatively small.

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Exercise 1: Post Synthesis External Logic Creation

This exercise demonstrates the default gate-level flow where the EDT logic is placed external to the
core. This flow generates a top-level wrapper (a new level of hierarchy) to integrate the Tessent
TestKompress logic with the core design.

Post Synthesis External Logic Creation

Step 1: Insert Scan

While any scan insertion tool can be used to insert the scan chains, for this exercise, you use Tessent
Scan. The maximum number of channels (ATE Connections to the chip) is dependent on the ATE that will

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be performing the testing. However, the designers choose the number of scan chains. Therefore, scan
insertion is considered to be part of the compressed pattern flow. The following limitations exist for the
generation of scan chains:

 Both prefixed and bussed scan input and output pins can be used. For bussed pins, the buses
must be ordered either ascending or descending (not randomly ordered.)

 Scan chains must have dedicated input/output pins. This is the default operation for the
insert_test_logic command in Tessent Scan.
Scan chain outputs cannot be shared with functional output pins for Tessent TestKompress. By default,
Tessent Scan creates new input and output pins for scan chains. During scan insertion, you will define
the number of scan chains to be created. During EDT IP generation, you will specify the number of scan
channels.

Instructions
Review the Tessent Scan dofile, and then run it on the gate-level netlist and insert 5 scan chains.

1. Go to the 1_insert_scan directory for lab 2.1 and study the files used for this exercise.

$ cd $TK_TRAINING/Lab2.1/Exercise1/1_insert_scan
$ ls -al

2. Review the dofile for Tessent Scan shown in Figure 2.1-2. You will use this dofile to insert the scan
chains. Make sure you understand all the settings in this dofile.

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Figure 2.1-2.

3. Review the invocation script used to invoke Tessent Scan shown in Figure 2.1-3. Notice how the
files are organized for this lab.

Figure 2.1-3. insert_scan Invocation Script

tessent -shell -dofile scan.do -log ../logfiles/scan.log

-replace

4. Issue the following command at the shell command line prompt to invoke Tessent Scan, run the
pre-generated dofile, and insert scan chains.

$ ./insert_scan

5. Examine the logfile and verify the netlist, dofile, and test procedure files were written.

6. Expand the terminal window and answer the following questions:

What does this command do?

set_scan_insertion_options -port_index_start_value 1 -si_port_format
edt_si%d -so_port_format edt_so%d
___________________________________________________________

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How many memory elements were there? ____________

How many were identified as scannable? ____________

How many reported chains were there? (report_scan_chains command)

______________________

What is the length of the longest chain? _________________________

How many new pins were inserted? (report_test_logic command)

______________________

Where are they located?___________________________________

What are the pins used for? __________________________________

Step 2: Create Tessent TestKompress (EDT) Logic

In this step, you invoke Tessent Shell and use Tessent testKompress to create compression logic, and
obtain initial coverage and compression estimates.

The logic created in this step includes the decompressor, compactor, bypass logic, and a top-level
wrapper. The wrapper adds one level of hierarchy to the design. The new top-level includes
instantiations of the EDT IP and the original design. To create the EDT IP in this flow, the scan inserted
core netlist is used. If this is the chip top-level, the EDT IP mist be created before I/O pads are added to
the design.

set_edt_options command is used to configure the EDT logic. The write_edt_files

command is used to write out EDT files.

The set_edt_options command, which configures the EDT circuitry, has several options. For this
basic run, the only option used is -Channels 1, which specifies one scan channel. The following
defaults are used for the rest of the other options:

 Add lockup cells in the EDT logic

 There are no pre-defined pipeline stages in the compactor
 Add EDT bypass logic

The EDT IP is generated using the write_edt_files command, eleven files are generated (see list
below). The files contain the EDT IP described in Verilog or VHDL RTL, as well as a connectivity and a
black box representation of the core, dofiles, and test procedures file that will be used later in the flow.
The tool also generates the ICL and PDL files even if you did not specify the –ijtag option. The TCD file
that contains the description of the generated EDT IP is also generated.

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 EDT logic RTL (*_edt.v)

 Design Compiler (DC) synthesis script (*_dc_script.scr)
 Test procedure file (*_edt.testproc)
 Dofile (*_edt.dofile)
 Bypass dofile (*_bypass.dofile)
 Bypass test procedure file (*_bypass.testproc)
 A core top file (*_edt_top.v)
 A core blackbox file (*_core_blackbox.v)
 ICL file (*_edt.icl)
 PDL file (*_edt.pdl)
 TCD file (*_piccpu_edt.tcd)

At this point in the flow, you can choose to get an estimate of test coverage and data volume for this
given configuration. This can be repeated with different configurations to experiment with coverage and
data volume. For situations where you may want to investigate the effects of changing the number of
chains and channels, compression analyzer can be utilized. We will discuss compression analyzer in
detail in another chapter.

Instructions
Invoke Tessent Shell on the scan-inserted netlist (5 scan chains), set the context to dft -edt and
create EDT IP with one scan channel.

1. Go to the 2_edt_ip directory:

$ cd $TK_TRAINING/Lab2.1/Exercise1/2_edt_ip

2. First, review the dofile edt_ip_creation.do. Just like in the previous step, where you inserted scan,
the dofile contains all information needed to set up scan channels and parameters for EDT IP,
generate EDT IP, and create preliminary patterns.

All Tessent DFT tools are command-driven. You enter commands one of two ways: at the tool’s
command prompt, or in a script called a dofile. Dofiles can have extensions such as .do, .tcl, or
.dofile. Once you are familiar with Tessent Shell and Tessent TestKompress (EDT) commands,
you can place the commands you normally use in a dofile to automate the process and save
time.

In this first exercise, you use dofiles to complete the basic external logic location flow.

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Entering tessent –manual at the UNIX shell prompt displays the

documentation for Mentor Graphics DFT tools. You can look up tool and
Note relevant shell commands in the Tessent Shell Reference Manual.

Figure 2.1-4. edt_ip_creation.do Dofile

When Tessent Shell is invoked it is in setup mode (as indicated by the SETUP prompt if you are entering
commands interactively). The first command that is entered, either via dofile, or interactively is to set
the context. Until you set the context, you can not do anything, including reading in design files and
libraries. Since the commands you use in this exercise are in the dofile, you do not see the various
system modes and prompts; nevertheless the tool goes through the various system modes to create the
EDT hardware.

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To insert EDT IP, the context is set to dft -edt. The dft mode tells the tool going to be “designing”
something, in this case, the EDT hardware. (You may have noticed in the first step, the context was dft
-scan. This indicated you were designing scan chains,)
Once the context is set you read in the design using read_verilog command and ATPG cell library
files using the read_cell_library command.

The next command that is used is set_current_design. This command elaborates the design. If
no module is specifically designated, the tool determines the top-level module in the design. If more
than one top-level is found, the tool presents a list to you and you must choose a top-level by reissuing
the command along with the name of the top-level module. All subsequent commands are applied to
the “current_design” whether it was determined or specified until the current design is specified by
another set_current_design.

Notice that this dofile invokes another dofile, atpg.dofile. This file was generated in the previous step,
when you inserted scan and generated ATPG setup files.

Once the atpg.dofile file is invoked, the command tessent_scan_setup is used to execute the
Tcl procedures from the dofile.

The dofile continues by setting up the EDT logic with one scan channel. Take a look at the different
options for the set_edt_options command in the Tessent Shell Reference Manual,

The command and argument set_edt_options -channels 1 configures the EDT logic with
one channel. EDT Options are set before running DRCs and entering the ANALYSIS mode.

Next command is report_edt_pins. Look up this command and report what it does:
____________________________________________________________

Next, check_design_rules runs DRC, and if there are no errors you leave SETUP mode. When
creating EDT IP, the tool uses the same DRC rules as other Mentor Graphics DFT tools in addition to the
EDT-specific K rules or F rules.

The two commands report_edt_configurations and report_edt_lockup_cells

are next in the script; you will examine what they report after you run the script. These two commands
are optional but are useful when examining results.

The next command creates the EDT logic based on your specifications:

write_edt_files ../results/created -verilog -replace

The tool does not automatically overwrite files of the same name so you must use the -replace
argument or you will get an error if the files exists. Designate what type of output file you want; in this
case, you save the file in Verilog format as designated by the -Verilog switch.

As stated previously, you do not need to create patterns but may choose to do so in order to get an
estimate of coverage. The dofile does this with the create_patterns command.

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After the tool has created patterns, the report_scan_volume command is executed, which
reports the volume of scan data used in the pattern set. If you do not understand any of the commands,
look them up in the Tessent Shell Reference Manual or ask your instructor.

3. Invoke Tessent TestKompress using Tessent Shell on gate_scan_5.v:

$ tessent -shell -dofile edt_ip_creation.do \

-log ../logfiles/edt_ip_creation.log -replace

When commands include a “\” this is an indication that the

command did not fit on a single line in the documentation.
Note
Issue this command on one line.
4. Watch the terminal as the dofile is running. The commands executed in Tessent Shell are echoed
to the terminal. You could scroll up and down to view results, but it is much easier to look at the
log file. The design for this lab is small so it is easy to view results in the terminal, but your design
likely will be too big to view everything in the terminal. This is why the log file is so useful.
Remember you instructed Tessent Shell to create a log file when you invoked the tool. It is in the
logfiles directory. Open the log file, edt_ip_creation.log, and answer the following questions.

a. Open a new terminal window and change to

$TK_TRAINING/Lab2.1/Exercise1/logfiles directory.
b. Using a text editor of your choice, open the log file edt_ip_creation.log

What are the names of the pins the report_edt_pins command reported?
______________________ ,______________________, ______________________,
_____________________, ______________________

Figure 2.1-5 shows the DRC messages reported.

Figure 2.1-5. Tessent TestKompress DRC Messaging

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The DRC reports a K13 violation. What is a K13 violation? (The answer can be found in the Tessent
Shell Reference Manual in the chapter called “Design Rule Checking”.
___________________________________________________________
___________________________________________________________

How many pins are added to the top-level wrapper? _________________

Since the core level scan chain pins will not be connected to the top-level wrapper, scan input pins
are set to __________ and scan output pins are __________. This is done so that the patterns that
are generated in this step, and the reported coverage does not give credit for fault sites that can
only be controlled or observed by the scan chain input and output pins. (These pins will not be
available in the pattern generation phase since they are connected directly to the EDT logic.)

5. When DRC has finished running, configuration details of the EDT logic are reported by the
report_edt_configurations command. This command lists EDT configurations,
including the number of channels and chains, pin names, size of the decompressor, and so on.

How many external scan channels are there? _____________________

How many internal scan chains are there? _______________________

What is the size of the decompressor? __________________________

What is the compression per patterns? __________________________

6. The command report_edt_lockup_cells reports on and examines EDT lockup cells:

Where are the lockup cells located? ___________________________

How many chains have lockup cells? __________________________

7. Review the files created as part of the generation of the EDT logic. By changing to the ../results
directory.

$ cd ../results

Mentor Graphics recommends that you create a separate directory in

which to keep the result of EDT file creation, pattern creation, dofiles and
Note test procedure files.
The following command created the EDT-specific files with the filename prefix “created_”:

write_edt_files ../results/created -verilog -replace

The following files were written:

o created_edt.v — Tessent TestKompress circuitry (Verilog RTL)

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o created_edt_top.v — Top level wrapper (instantiates core and Tessent TestKompress

logic)

o created_core_blackbox.v — Blackbox description of the core (used for synthesis)

o created_dc_script.scr — Design Compiler synthesis script

o created_edt.dofile — Dofile for Tessent TestKompress (test pattern generation)

o created_edt.testproc — Procedure file (test pattern generation)

o created_bypass.dofile — Dofile for bypass mode

o created_bypass.testproc — Procedure file for bypass mode

o created_edt.icl — EDT logic ICL

o created_edt.pdl — EDT logic PDL

o created_piccpu_edt.tcd — The design TCD file

Figure 2.1-6 illustrates the contents of the new top-level netlist created_edt_top.v. This netlist
contains the design module, and edt_top that includes the original core and the EDT logic.

Figure 2.1-6. Top-Level Netlist created_edt_top.v

8. The script also generated test patterns for assessing coverage.

During EDT IP creation, you can generate test patterns to assess the coverage. The patterns that
will be used for manufacturing test and pattern verification are generated after the EDT IP is

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synthesized. For pattern generation, the script uses the same commands
(create_patterns)that is used for Tessent FastScan.

create_patterns
report_scan_volume
9. The script ends by exiting Tessent TestKompress.

exit -f

Step 3: Synthesize EDT Logic and I/O Pads

In the previous step, you created an RTL for the Tessent TestKompress IP. Before synthesis takes place,
I/O pads and boundary scan can be inserted, although neither pads nor JTAG are added for this exercise.
For this step, the synthesized design and the netlist is provided for you.

If you are adding I/O pads, they should be synthesized together with the Tessent TestKompress logic
before the final test patterns are generated. The design used in this exercise, however, does not have
I/O pads.

For this design, the synthesized RAM model is not available. Therefore, the design is synthesized without
the RAM. For ATPG and Tessent TestKompress, the ATPG model is used. For Verilog simulation, you will
use the RTL model of the RAM.

Instructions
This step discusses the generation of the synthesized netlist:

created_edt_top_gate.v
1. Although you do not synthesize the design in this step, you should understand what files are used
in synthesis and how they interact.

Go to the results directory for this lab:

$ cd $TK_TRAINING/Lab2.1/Exercise1/results
2. Examine the synthesis script created_dc_script.scr generated by Tessent TestKompress. Verify that
the synthesized created_edt_top_gate.v netlist is copied into the ../design directory.

You use this netlist in Step 4

Step 4: Tessent TestKompress ATPG in Compression Mode

In this step you generate test patterns for the design. During EDT IP generation, Tessent TestKompress
was invoked on the core level scan inserted netlist of the design. To generate test patterns, Tessent
TestKompress will use the synthesized top-level of the design that can include pads, boundary scan, and
the Tessent TestKompress IP.

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For the pattern generation, the EDT IP will be configured via information stored in the EDT created
dofile. This configuration information should never be edited.

Figure 2.1-7. Dofile ../results/created_edt.dofile

Compared to when you generated test patterns using Tessent FastScan, there are certain differences in
tool setup. For the pattern generation, you operate the existing Tessent TestKompress circuitry. This is
done by exercising two control signals, edt_clock and edt_update.

Prior to each scan load, the Tessent TestKompress circuitry will be reset. This is done by pulsing the
edt_clock while edt_update is high. During shifting, edt_clock should be pulsed together with the scan
clock. In Figure 2.1-8. Control Signals for Test Pattern GenerationFigure 2.1-8, both scan_enable and
edt_update are shown as 0 during the capture cycle. These two signals can have any value during the
capture cycle; they do not have to be constrained. edt_clock, on the other hand, needs to be 0 during
the capture cycle. The operation of these signals is described in the test procedure load_unload / shift
procedures.

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Figure 2.1-8. Control Signals for Test Pattern Generation

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Figure 2.1-9. Procedure File ../results/created_edt.testproc

The following differences can be found in the test procedure files and dofiles that were created by
Tessent Scan and Tessent TestKompress

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The test procedure file:

 Defines that edt_update is active in the load_unload procedure and edt_clock is pulsed in the
load_unload and shift procedures.

 The load_unload procedure is set up to initialize the EDT circuitry and apply shift a number of
times corresponding to the longest scan chain + initialization cycles. The number of
initialization cycles is reported by the report_edt_configurations command.

 The shift procedure is updated to include pulsing the edt_clock signal and deactivate the
edt_update signal.
The dofiles

 The edt_clock signal needs to be defined as a clock and constrained to the off-state (0). The
constraint is necessary in order to avoid the pulsing of this signal during the capture cycle.

 The chains are now connected to the internal nodes of the design and not primary inputs and
outputs. Therefore a different scan chain definition than what was used during the logic
creation phase is implemented. The -internal option with the add_scan_chains
command defines the scan chains as internal chains (as opposed to chains connected to PIs
and POs).
After test patterns are created, you will validate both parallel and serial patterns in a Verilog simulator.

Instructions
In this step, you will use Tessent TestKompress on the synthesized top-level netlist and use the dofile
that was automatically generated during logic creation to set up the circuitry, then generate and save
test patterns.

1. Review the ../results/created_edt.dofile generated by Tessent TestKompress in Step 2 and answer

the following questions:

Why are scan chains defined as internal?

_______________________________________________________

Why is the EDT clock constrained to 0?

_______________________________________________________

Why is it important not to modify the EDT settings?

_____________________________________________________

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2. Examine the ../results/created_edt.testproc generated by Tessent TestKompress in Step 2 and

answer the following questions:

During the load_unload procedure, why is edt_bypass forced to 0?

_____________________________________________________________

What value is edt_update forced to? Why? ___________________________

_____________________________________________________________

What happens when edt_clock pulses during load_unload? ______________

_____________________________________________________________

3. Change directories to the 4_edt_pattern directory for this exercise:

$ cd $TK_TRAINING/Lab2.1/Exercise1/4_edt_pattern
4. Enter the following command to invoke Tessent Shell:
$ tessent -shell -log ../logfiles/edt_pattern_gen.log \
-replace
5. Set the context to create scan patterns, read in the Verilog netlist and the cell library files, and set
the current design to the default.

SETUP> set_context patterns -scan

SETUP> read_verilog ../design/created_edt_top_gate.v
SETUP> read_cell_library ../../../libs/tessent/adk.tcelllib
SETUP> set_current_design
6. Set up Tessent TestKompress before starting the pattern generation test process by invoking the
dofile written by Tessent TestKompress during logic creation:

SETUP> dofile ../results/created_edt.dofile

7. Disable the EDT finder:

SETUP> set_edt_finder off

8. Enter ANALYSIS mode to run DRC and report EDT configurations:

SETUP> check_design_rules
ANALYSIS> report_edt_configurations
Verify that no DRC violations occur. Pay special attention to the Tessent TestKompress DRC
checks. Once you enter ANALYSIS mode, report the EDT configuration as well.

9. Generate test patterns:

ANALYSIS> create_patterns
ANALYSIS> report_scan_volume

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Verify that high test coverage is achieved. The command report_scan_volume provides
reference numbers when analyzing the achieved compression.

What is the total test data volume? ____________

10. Save test patterns for simulation. Write the flat model for use in debugging simulation
mismatches and for use with Tessent Diagnosis. Save all patterns in parallel format and Sample
two patterns of each pattern type for serial simulation.

ANALYSIS> write_patterns ../results/patterns_edt.ascii \

-replace
ANALYSIS> write_flat_model ../results/pat_edt_flat.flt \
-replace
ANALYSIS> write_patterns ../results/patterns_edt_p.v \
-verilog -parallel -param tk.param -replace
ANALYSIS> set_pattern_filtering –sample_per_type 2
ANALYSIS> write_patterns ../results/patterns_edt_s.v \
-verilog -serial -param tk.param -replace
11. Exit Tessent TestKompress:

ANALYSIS> exit

Step 5: Run Tessent TestKompress ATPG in Bypass Mode

(Optional)
Figure 2.1-10. EDT Bypass Circuit

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 Tessent TestKompress Integration Flows
Post Synthesis External Logic Creation

This is an optional step for the generic Tessent TestKompress flow. However, by default bypass mode is
included in the Tessent TestKompress circuitry to allow access to the scan chains if there are
manufacturing defects associated with the EDT IP. When bypass mode is implemented, patterns that
exercise this mode should be generated and verified. You also can use bypass mode patterns for the
following:

 As a reference point for calculation of Tessent FastScan/Tessent TestKompress compression.

 As additional hints for debugging: Patterns can be generated and simulated to verify that non-
Tessent TestKompress patterns simulate without problems.
This run is like any Tessent FastScan run and does not have any special settings. However, to be able to
compare simulation mismatches etc., all settings (pattern types, constraints, etc.) should be identical to
those used when generating compressed patterns. Tessent TestKompress automatically generates a test
procedure file and dofile to set up the Tessent TestKompress circuitry for this step.

Instructions
Invoke Tessent Shell on the synthesized top-level netlist and use the dofile generated during logic
creation to set up the circuitry for bypass, then generate and save bypass test patterns.

Tessent Shell will process the dofile and understand that these patterns
will be generated in bypass mode, not EDT.
Note

1. Go to the 5_bypass_pattern directory.

$ cd $TK_TRAINING/Lab2.1/Exercise1/5_bypass_pattern
2. Examine the bypass dofile and test procedure files generated during Tessent TestKompress logic
generation. These files are in the Exercise1/results directory.

Notice the difference and similarities to the files generated for Tessent TestKompress pattern
generation.

$ cat ../results/created_bypass.dofile
$ cat ../results/created_edt.dofile
$ cat ../results/created_bypass.testproc
$ cat ../results/created_edt.testproc

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 Tessent TestKompress Integration Flows
Post Synthesis External Logic Creation

Figure 2.1-11. ../results/created_bypass.dofile

Figure 2.1-12. ../results/created_bypass.testproc

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 Tessent TestKompress Integration Flows
Post Synthesis External Logic Creation

3. Issue the following command to invoke Tessent TestKompress:

$ tessent -shell -log \

../logfiles/bypass_pattern_gen.log -replace
4. Set the context to scan patterns, read in the Verilog netlist, read in the cell library files, and set the
current design to the default.
SETUP> set_context patterns -scan
SETUP> read_verilog ../design/created_edt_top_gate.v
SETUP> read_cell_library ../../../libs/tessent/adk.tcelllib
SETUP> set_current_design

5. Define the scan chain and read the test procedure file and define clocks. Remember, in bypass
mode, the EDT IP will not be involved in pattern generation.

SETUP> dofile ../results/created_bypass.dofile

6. Run DRC and verify that no DRC errors occur.
SETUP> check_design_rules
7. Generate test patterns (ATPG).

Use the exact same pattern generation sequence as you did for Tessent TestKompress to create
basic patterns with dynamic compression. For comparison purposes, add faults only on the core
of the design and disregard the EDT circuitry:

ANALYSIS> create_patterns
ANALYSIS> report_scan_volume

The command report_scan_volume provides reference numbers when analyzing the

compression.

What is the total test data volume? ____________

8. Save test patterns.

Save the test patterns in different formats so you can simulate all of them. Save all patterns in
parallel format and a few in serial format. For the serial patterns, use only a few patterns.
Rather than selecting the first few patterns, have Tessent TestKompress sample two patterns of
each pattern type in the pattern set.

ANALYSIS> write_patterns \
../results/patterns_bypass.ascii -replace
ANALYSIS> write_flat_model \
../results/patterns_bypass_flatmodel.flt -
replace

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 Tessent TestKompress Integration Flows
Post Synthesis External Logic Creation

ANALYSIS> write_patterns \
../results/patterns_bypass_p.v -verilog \
-parallel –param tk.param -replace
ANALYSIS> set_pattern_filtering –sample_per_type 2
ANALYSIS> write_patterns \
../results/patterns_bypass_s.v –verilog \
-serial -param tk.param -replace

9. Exit Tessent TestKompress:

ANALYSIS> exit

Step 6: Simulate Test Patterns

To verify that the test patterns, the EDT IP, and the bypass circuitry operate correctly, test patterns
should be simulated with full timing. For this example, all patterns are simulated in parallel along with a
sample of the pattern set in serial. Only the serial Tessent TestKompress patterns exercise the EDT
circuitry and scan chain shifting. Also, notice that a Tessent TestKompress chain and logic integrity test is
included in the pattern set to verify correct operation and high-test coverage of the Tessent
TestKompress circuitry itself.

Instructions
You use the ModelSim simulator, but any other Verilog simulator can be used. The test benches
generated by Tessent TestKompress are tool independent.

1. Prepare for simulation.

Go to the directory 6_pattern_sim and study the files in this directory. The directory contains
scripts for pattern simulation.
$ cd $TK_TRAINING/Lab2.1/Exercise1/6_pattern_sim
2. Examine the invocation script and use it to compile the four test benches and the Verilog netlist
and library:

$ ./run_vlog_all
3. Simulate the test patterns.

After the test benches, the netlist, and the library are compiled, the patterns can be simulated
using the invocation script for vsim. Notice that four different logfiles are saved, so that you can
verify later that no mismatches occurred in any of the test benches.

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 Tessent TestKompress Integration Flows
Post Synthesis External Logic Creation

Figure 2.1-13. ModelSim Invocation Script (run_vsim_all)

vsim -novopt piccpu_edt_top_patterns_edt_p_v_ctl -do “run -all” -c -l ../results/sim_edt_p.log
vsim -novopt piccpu_edt_top_patterns_edt_s_v_ctl -do “run -all” -c -l ../results/sim_edt_s.log
vsim -novopt piccpu_edt_top_patterns_bypass_p_v_ctl -do “run -all” -c -l ../results/sim_edt_p.log
vsim -novopt piccpu_edt_top_patterns_bypass_s_v_ctl -do “run -all” -c -l ../results/sim_edt_s.log

Notice that the simulator is invoked from the generated directory. The -c switch instructs the
simulator to run in non-GUI mode.

4. Execute the invocation script and verify that no simulation mismatches were reported:

$ ./run_vsim_all

There should be no simulation mismatches returned.

Congratulations! You have successfully finished your first Tessent TestKompress integration
flow.

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Tessent TestKompress – Lab Answers

Appendix: Answers to Questions

Lab 2.1

Exercise 1: Post-Synthesis External Logic Creation

Step 1: Insert Scan

Step 6

Q. What does this command do?

set_scan_insertion_options -port_index_start_value 1 -
si_port_format edt_si%d -so_port_format edt_so%d?

It specifies the high-level options for the scan insertion process.

Using the following options:

-port_index_start_value 1

-si_port_format edt_si%d

-so_port_format edt_so%d

The index placeholder "%d" gets substituted by the chain index, so the port names
created will be edt_si1, edt_si2, etc.

Q. How many memory elements were there?

134

Q. How many were identified as scannable?

127

Q. How many reported chains were there? (report_scan_chains command)

Q. What is the length of the longest chain?

26

Q. How many new pins were inserted (report_test_logic command)?

11

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Tessent TestKompress – Lab Answers

Q. Where are they located?

Primary input and output ports

Q. What are the pins used for?

Scan enable, and scan chain inputs and outputs

Step 2: Create Tessent TestKompress (EDT) Logic

Q. Next command is report_edt_pins. Look up this command and report what it
does?

It displays the names of all EDT channel and control pins and whether the pin signals are
inverted between the chip input pin and the EDT logic.

Step 2

Q. What are the names of the pins the report_edt_pins command reported?

edt_clock, edt_update, edt_bypass, edt_channels_in1, edt_channels_out1

Q. What is a K13 violation?

This rule check reports all pins that will be added to the EDT top-level wrapper in
order to implement the EDT hardware

Q. How many pins are added to the top-level wrapper?

Q. Since the core level scan chain pins will not be connected to the top-level wrapper, scan
input pins are set to ……. and scan output pins are …….

TIE-X , masked

Step 3

Q. How many external scan channels are there?

Q. How many internal scan chains are there?

Q. What is the size of the decompressor?

10

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Tessent TestKompress – Lab Answers

Q. What is the compression per patterns?

3.02x ( ATPG bypass = 1 x 127, EDT = 1 x 42 )

Step 4

Q. Where are the lockup cells located?

DECOMPRESSOR & COMPACTOR

Q. How many chains have lockup cells?

5 (chain 1 – chain 5)

Step 4: Tessent TestKompress ATPG in Compression Mode

Step 1

Q. Why are scan chains defined as internal?

The chains are connected to the internal nodes of the design and not primary inputs
and outputs. The -internal option with the add_scan_chains command
defines the scan chains as internal chains (as opposed to chains connected to PIs and
POs).

Q. Why is the EDT clock constrained to 0?

This constraint is needed in order to avoid the pulsing of this clock during the capture
procedure.

Q. Why is it important not to modify the EDT settings?

Modifying the EDT settings may lead to DRC violations and invalid patterns as there is
inconsistency between the EDT settings and EDT logic.

Step 2

Q. During the load_unload procedure, why is edt_bypass forced to 0?

This will disable bypass mode and create patterns with the compression logic.

Q. What value is edt_update forced to? Why?

1, this initiates the resetting of the decompressor logic.

Q. What happens when edt_clock pulses during load_unload?

The flipflops in the decompressor get reset.

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Tessent TestKompress – Lab Answers

Step 9

Q. What is the total test data volume?

Input volume = 12012

Output volume = 11802

Step 5: Run Tessent TestKompress ATPG in Bypass Mode

(Optional)
Step 7

Q. What is the total test data volume?

Input volume = 30226

Output volume = 29718

Tessent TestKompress 33