ES 333

MICROPROCESSORS AND EMBEDDED

Ahaan Giriya - 21110015

CODE (for INR, DCR):

MVI B, 80H
INR B

MVI C, 91H
DCR C

HLT

REGISTERS

A/PSW 0x96

BC 0x8190

DE 0x0000

HL 0x0000

SP 0xFFFF

PC 0x0807

FLAGS
 Z 0

S 1

P 1

C 0

AC 1

CODE (for INX, DCX):

LXI H, 1010H
INX H

LXI B, 1051H
DCX B

HLT

REGISTERS

A/PSW 0x0002

BC 0x1050

DE 0x0000
 HL 0x1011

SP 0xFFFF

PC 0x0809

FLAGS

Z 0

S 0

P 0

C 0

AC 0

Q1 b)

Accumulator || Directly || Load:

CODE:

LXI H, 1000H
MVI M, 32H

LDA 1000H

HLT
REGISTERS

A/PSW 0x3202

BC 0x0000

DE 0x0000

HL 0x1000

SP 0xFFFF

PC 0x0809

FLAGS

Z 0

S 0

P 0

C 0

AC 0

Accumulator || Directly || Store:

CODE:
 MVI A, 45H
STA 1000H
HLT

REGISTERS

A/PSW 0x4502

BC 0x0000

DE 0x0000

HL 0x0000

SP 0xFFFF

PC 0x0806

FLAGS

Z 0

S 0

P 0

C 0
 AC 0

Accumulator || Indirectly || Load:

CODE:

MVI H, 20H
MVI L, 50H

MVI M, 43H

MOV A,M

HLT

REGISTERS

A/PSW 0x4302

BC 0x0000

DE 0x0000

HL 0x2050

SP 0xFFFF

PC 0x0808

FLAGS
 Z 0

S 0

P 0

C 0

AC 0

Accumulator || Indirectly || Store:

CODE:

MVI H, 20H
MVI L, 60H

MVI A, 13H

MOV M,A

HLT

REGISTERS

A/PSW 0x1302

BC 0x0000

DE 0x0000
 HL 0x2060

SP 0xFFFF

PC 0x0808

FLAGS

Z 0

S 0

P 0

C 0

AC 0

HL || Directly || Load:

CODE:

MVI A, 40H
STA 1050H

MVI A, 72H
STA 1051H

LHLD 1050H

HLT
REGISTERS

A/PSW 0x7202

BC 0x0000

DE 0x0000

HL 0x7240

SP 0xFFFF

PC 0x080E

FLAGS

Z 0

S 0

P 0

C 0

AC 0
 HL || Directly || Store:

CODE:

MVI H, 56H
MVI L, 78H

SHLD 1091H

HLT

REGISTERS

A/PSW 0x0002

BC 0x0000

DE 0x0000

HL 0x5678

SP 0xFFFF

PC 0x0808

FLAGS

Z 0
 S 0

P 0

C 0

AC 0

Q1c)

The three types of branching instructions are:

(a) Unconditional Jump (JMP)

CODE:

MVI A, 02H
JMP TARGET

ADD A ; not executed because of JMP

TARGET: MOV B, A

HLT

Registers

A/PSW 0x0202

BC 0x0200
 DE 0x0000

HL 0x0000

SP 0xFFFF

PC 0x0808

Flags

Z 0

S 0

P 0

C 0

AC 0

(b) Conditional Jump (JC, JNC, JZ, JNZ, JPE, JPO, JM, JP)

Example of JNZ (jump if no zero)-

CODE:

SUB A
MVI B, 01H
MVI C, 05H ; counter
 LOOP:ADD B
DCR C
JNZ LOOP

HLT

Registers

A/PSW 0x0556

BC 0x0100

DE 0x0000

HL 0x0000

SP 0xFFFF

PC 0x080B

Flags

Z 1

S 0

P 1

C 0
 AC 1

Q1 d) Push and Pop

CODE:

LXI B, AB45H
PUSH B
POP D
MOV H,D
MOV L,E
HLT

REGISTERS

A/PSW 0x0002

BC 0xAB45

DE 0xAB45

HL 0xAB45

SP 0xFFFF

PC 0x0808

FLAGS
Z 0

S 0

P 0

C 0

AC 0

Q2)

CODE:

SUB A

MVI H, 20H
MVI L, 00H
MVI M, 03H

MVI H, 20H
MVI L, 01H
MVI M, 08H

LXI H, 2000H
MOV B, M

INX H
MOV C, M

LOOP: ADD B
DCR C
JNZ LOOP
 INX H
MOV M, A

HLT

REGISTERS

A/PSW 0x1856

BC 0x0300

DE 0x0000

HL 0x2002

SP 0xFFFF

PC 0x081B

FLAGS

Z 1

S 0

P 1

C 0
 AC 1

Note: 1 represents flag is set and 0 represents flag is reset

Q3)

CODE:

MVI A, 02H
STA 0040H

MVI A, 01H
STA 0041H

MVI A, 01H
STA 0042H

MVI A, 01H
STA 0043H

MVI A, 00H
STA 0044H

MVI A, 00H
STA 0045H

MVI A, 04H
STA 0046H

MVI A, 09H
STA 0047H

LXI H, 0040H
SUB A
MOV A, M

MVI C, 07H

LOOP:INX H
 ADD M
DCR C
JNZ LOOP

ADI 08H
STA 0A90H
HLT

REGISTERS

A/PSW 0x1A12

BC 0x0000

DE 0x0000

HL 0x0047

SP 0xFFFF

PC 0x083B

FLAGS

Z 0

S 0

P 0
C 0

AC 1

Q4)

CODE:
LXI B, 153AH
PUSH B
POP D
SUB A
ADD D
ADD E
STA 2000H
HLT

REGISTERS:

A/PSW 0x4F12

BC 0x153A

DE 0x153A

HL 0x0000

SP 0xFFFF

PC 0x080C
FLAGS:

Z 0

S 0

P 0

C 0

AC 1

Q5)

CODE:

LXI H,2400H
MVI M,97H
INX H
MVI M,1AH
INX H
MVI M,61H
INX H
MVI M,43H
INX H
MVI M,2DH

MVI C, 05H
DCR C
REPEAT: MOV D, C
LXI H, 2400H
LOOP: MOV A, M
 INX H
CMP M
JC SKIP
MOV B, M
MOV M, A
DCX H
MOV M, B
INX H
SKIP: DCR D
JNZ LOOP
DCR C
JNZ REPEAT
HLT

REGISTERS

A/PSW 0x1A57

BC 0x2D00

DE 0x0000

HL 0x2401

SP 0xFFFF

PC 0x082C

FLAGS

Z 1
S 0

P 1

C 1

AC 1