Technical University of Mombasa

TEE 4451: MICROCONTROLLER SYSTEMS AND APPLICATIONS

Lecturer: Francisco Omutsani

Email: [email protected]

LECTURE SESSIONS
Session FIVE: PIC Microcontrollers Interrupts and EEPROM Data Memory
5.1 Session Objectives
By the end of this session, you should be able to:
 The PIC interrupts sources.
 The interrupt logic circuit.
 The interrupt controls register INTCON.
 Context Saving During Interrupts
 EEPROM registers
 EEPROM Data Read & Write Operation
5.2 The PIC interrupts sources
The PIC16F84A has 4 sources of interrupt:
• External interrupt RB0/INT pin
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• Data EEPROM write complete interrupt
5.2.1 INT INTERRUPT
It is an edge triggered interrupt that is externally applied on RB0/INT pin

TUM is ISO 9001:2015 Certified Omutsani Francisco

1
The appropriate edge is reflected in the OPTION register for example on rising INTEDG bit
(OPTION_REG<6>) is set, or falling if INTEDG bit is clear.
The INT interrupt can wake the processor from SLEEP only if the INTE bit was set prior to going
into SLEEP.
The status of the GIE bit decides whether the processor branches to the interrupt vector following
wake-up.
Note: When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This
interrupt can be disabled by clearing control bit INTE (INTCON<4>).
5.2.2 TMR0 INTERRUPT
It occurs as a result of an overflow (FFh to 00h) in TMR0 will set flag bit T0IF (INTCON<2>). The
interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>)
5.2.3 PORTB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled
/disabled by setting/clearing enable bit RBIE (INTCON<3>)
5.2.4 DATA EEPROM INTERRUPT
At the completion of a data EEPROM write cycle, flag bit EEIF (EECON1<4>) will be set. The
interrupt can be enabled /disabled by setting/clearing enable bit EEIE (INTCON<6>)
5.3 INTERRUPT LOGIC

5.4 INTCON Register

The INTCON register is a readable and writable register that contains the various enable bits for
all interrupt sources.

TUM is ISO 9001:2015 Certified Omutsani Francisco

2
 Bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
Bit 6 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE Write Complete interrupts
0 = Disables the EE Write Complete interrupt
Bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
Bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
Bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
Bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
Bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
Bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
5.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save
key register values during an interrupt (e.g., W register and STATUS register). This is
implemented in software.

TUM is ISO 9001:2015 Certified Omutsani Francisco

3
The code in Example 5.5-1 stores and restores the STATUS and W register’s values. The user
defined registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W
and STATUS registers values.
EXAMPLE 5.5-1: SAVING STATUS AND W REGISTERS IN RAM
PUSH MOVWF W_TEMP ; Copy W to TEMP register,
SWAPF STATUS, W ; Swap status to be saved into W
MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
ISR : :
: ; Interrupt Service Routine
: ; should configure Bank as required
: ;
POP SWAPF STATUS_TEMP,W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF STATUS ; Move W into STATUS register
; (sets bank to original state)
SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in ;
; W_TEMP
SWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into
; W
NB: Example 6-1 does the following:
a) Stores the W register.
b) Stores the STATUS register in STATUS_TEMP.
c) Executes the Interrupt Service Routine code.
d) Restores the STATUS (and bank select bit) register.
e) Restores the W register.
5.6 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range).
This memory is not directly mapped in the register file space. Instead it is indirectly addressed
through the Special Function Registers.
The EEPROM is non-volatile and is particularly useful for holding data variables that can be
changed but are likely to be needed for the medium to long term.
 Examples include TV tuner settings, phone numbers stored in a cell phone or calibration
settings on a measuring instrument.

TUM is ISO 9001:2015 Certified Omutsani Francisco

4
The EEPROM data memory allows bytes read and write. A byte write automatically erases the
location and writes the new data (erase before write).
The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an
on-chip timer. The write time will vary with voltage and temperature as well as from chip to chip.
Please refer to AC specifications for exact limits.
When the device is code protected, the device programmer can no longer access this memory.
There are four SFRs used to read and write this memory. These registers are:
• EECON1
• EECON2
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write,
EEADR holds the address of the EEPROM location being accessed.
PIC16F84A devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh.
Reading from EEPROM is a simple process but writing to it is not. Since writing in EEPROM
takes significant time in electronic terms (i.e. milliseconds) care must be taken to avoid accidental
writes.
 A set of controls is therefore required to start the process and (for write) to detect when
it is ended. These controls are found in the bits of the EECON1 register;
5.6.1 The EECON1 Special Function register (address 88H)

TUM is ISO 9001:2015 Certified Omutsani Francisco

5
5.6.2 DATA EEPROM WRITE
To write to an EEPROM location, the required data and address must be placed in EEDATA and
EEADR respectively. The write process is enabled by the WREN (Write Enable) bit being set high,
followed by the bytes 55H followed by AAH being sent to the EECON2 register.
EXAMPLE 1: DATA EEPROM WRITE
BSF STATUS, RP0; Bank 1
BCF INTCON, GIE; Disable INTs
BSF EECON1, WREN; Enable Write
MOVLW 55h;
MOVWF EECON2; Write 55h
Required Sequence

MOVLW AAh;
MOVWF EECON2; Write AAh
BSF EECON1, WR; Set WR bit
; begin write
BSF INTCON, GIE; Enable INTs
The built-in requirement for these codes helps to ensure that accidental writes do not take place,
for example on power-up or -down.
The WR bit is then set high and writing actually commences. The write completion is signaled by
the setting of bit EEIF in EECON1.
 The write will not initiate if the above sequence is not exactly followed (write 55h to
EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend
that interrupts be disabled during this code segment.

TUM is ISO 9001:2015 Certified Omutsani Francisco

6
  Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism
prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e.,
lost programs). The user should keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared by hardware
 After a write sequence has been initiated, clearing the WREN bit will not affect this write
cycle. The WR bit will be inhibited from being set unless the WREN bit is set.
 At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write
Complete
 Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF
must be cleared by software.
5.6.3 DATA EEPROM READ
To read an EEPROM location, the required address must be placed in EEADR and the RD bit set
in EECON1. The data in that memory location is then copied to the EEDATA register and can be
read immediately.

EXAMPLE 2: DATA EEPROM READ

BCF STATUS, RP0; Bank 0
MOVLW CONFIG_ADDR;
MOVWF EEADR; Address to read
BSF STATUS, RP0; Bank 1
BSF EECON1, RD; EE Read
BCF STATUS, RP0; Bank 0
MOVF EEDATA, W; W = EEDATA
5.7 Student Activity
i. Explain the source of interrupt in PIC Microcontroller
ii. With aid of a interrupt logic circuit and Interrupt control register explain the significance of
each interrupt source
iii. Describe the significance of EEEPROM Special Function register,
5.8 Further Readings/References
Textbooks for the course
i. Raja, K. (2009). Microcontrollers: Architecture, Programming, Interfacing and System Design.
Prentice Hall, Upper Saddle River,NJ,USA
ii. John, S. (2006). Inside the Machine: An Illustrated Introduction to Microprocessor and Computer
Architecture, No Starch Pr,London.
iii. Kip, R. I. (2006). Assembly Language for Intel Based Computers, Prentice Hall, Upper Saddle
River,New Jersey,USA .
iv. Kleitz, W. (2002). Digital and Microprocessor Fundamentals, Theory and Applications, Prentice
Hall, Upper Saddle River,NJ,USA

TUM is ISO 9001:2015 Certified Omutsani Francisco

7