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Lecture 04

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34 views23 pages

Lecture 04

Uploaded by

Kashmala Alam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COMPILER CONSTRUCTION

Instructor:
Mr. Sheraz Babar

1
Lecture 04

2
Syntax Tree goal

x+2-y expr

expr op term

expr op term – <id,y>

term + <number, 2>


<id,x> 3
Abstract Syntax Trees
 The parse tree contains a lot
of unneeded information.
 Compilers often use an
abstract syntax tree (AST).

4
Abstract Syntax Trees
–

+ <id,y>
<id,x> <number,2>

 This is much more concise

5
Abstract Syntax Trees
–

+ <id,y>
<id,x> <number,2>

 AST summarizes grammatical


structure without the details of
derivation
6
Abstract Syntax Trees
–

+ <id,y>
<id,x> <number,2>

 ASTs are one kind of


intermediate representation
(IR)
7
The Back End

IR Instruction IR Register IR Instruction machine


selection allocation scheduling code

errors

8
The Back End
 Translate IR into target
machine code.
 Choose machine (assembly)
instructions to implement each
IR operation

9
The Back End
 Ensure conformance with
system interfaces
 Decide which values to keep
in registers

10
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Selection:
 Produce fast, compact code.
11
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Selection:
 Take advantage of target
features such as addressing
modes.
12
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Selection:
 Usually viewed as a pattern
matching problem – dynamic
programming.
13
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Selection:
 Spurred by PDP-11 to VAX-11
- CISC.
14
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Selection:
 RISC architecture simplified
this problem.
15
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Register Allocation:
 Have each value in a register
when it is used.
16
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Register Allocation:
 Manage a limited set of
resources – register file.
17
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Register Allocation:
 Can change instruction choices
and insert LOADs and STOREs.
18
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Register Allocation:
 Optimal register allocation is
NP-Complete.
19
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Scheduling:
 Avoid hardware stalls and
interlocks.
20
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Scheduling:
 Use all functional units
productively.
21
The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors

Instruction Scheduling:
 Optimal scheduling is
NP-Complete in nearly all cases.
22
The End

23

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