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    Ddco Simp 2024

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    Praneeth

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    Ddco Simp 2024

    Uploaded by

    Praneeth
    45 views3 pages

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    ddco simp 2024 (1) (1)

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    45 views3 pages

    Ddco Simp 2024

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    Praneeth

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    of 3

    DDCO SIMP Questions -21SCHEME

    BY TIE REVIEW TEAM

    Module 2 -Study any 7 Questions

    1. Design a combinational circuit to convert BCD to Excess-3 or can ask any design. 2.
    Design 4-bit parallel adder/ subtractor circuit.

    3. Explain carry look ahead adder circuit with block diagram


    Or
    3b.What is a binary subtractor, explain

    4. Explain half adder/subtractor and design full adder using 2 half adders.
    Or
    Explain the full adder with the help of TT and Logic diagram

    5. What is a decoder? Construct a two four line decoder


    with enable input along with TT and Explain
    6. Define Multiplexer? Explain 8:1 mux with the help of Logic diagram and logic expression, Also
    implement function F (A, B, C, D) = ϵm (1,2,5,6,9,12) using 8:1 Mux
    7. Design 32:1 MUX using 8:1 MUX and 4:1 MUX with the help of logic expn
    8. Explain the operation of JK, SR T and D flip flop and Positive edge triggered D Flip flop with
    Characteristic table and truth table.
    9.Explain the working of SR Latch using NOR gates, show how SR Latch can be used for switch
    debouncing
    10. Write the verilog HDL code for (i)Two to one line MUX (ii)Two to four line decoder (iii)Full adder
    using half adder module

    Module 3 -Study any 7 Questions

    1. With a neat diagram explain the basic operational concepts of computer , explain the registers
    of processor and explain the sequence of steps
    2. Analyze Big-Endian and little-Endian methods of byte addressing with example.
    3. WAP to evaluate Y= A*B+C*D or A+B*C+D is executed using one address, two address and
    three address and zero address instruction
    4. Define instruction sequencing and branching. Explain conditional flags and the concept of
    branching with an example program
    5. What is performance measurement? Explain the overall SPEC rating.
    6. Explain processor clock, clock rate, basic performance equation and performance
    measurement
    7. Explain all the addressing modes with examples

    8. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the
    effective- address of the memory operand in each of the following instructions?
    (a) Load 20(R1), R5 (b) Move #3000, R5 (c) Store R5,30(R1, R2) (d) Add -(R2), R5 (e) Subtract
    (R1)+, R5

    9. Consider the following possibilities for saving the return address of a subroutine: (a) In the
    processor register. (b) In a memory-location associated with the call, so that a different location is
    used when the subroutine is called from different places (c) On a stack. Which of these possibilities
    supports subroutine nesting and which supports subroutine recursion(that is, a subroutine that calls
    itself)?
    Module 4 -Study any 7 Questions

    1. How the input and output are performed by the processor? Write a program that reads the line
    or characters and displays it.
    2. Differentiate memory mapped I/O and I/O mapped I/O
    3. With neat sketches explain various methods for handling multiple interrupts raised by multiple
    devices. (or explain how I/O devices are organized in priority structure)
    4. Define Interrupt and interrupt hardware. how enabling and disabling of interrupts are
    performed.
    5. Define exceptions, describe different kinds of exceptions.
    6. Explain operation of DMA controller with neat block diagram.
    7. Define DMA bus arbitration. Explain centralized and distributed bus arbitration.
    8. Draw a neat diagram of memory hierarchy in a computer system. Discuss the variation of size,
    speed and cost per bit in the hierarchy.
    9. What is cache memory? Explain different mapping functions with diagrams.

    Module 5 -Study any 7 Questions

    1. Write and explain the control sequence for execution of the instruction ADD (R3), R1 on a single
    bus processor.
    Or
    Write and explain the control sequence for execution of an unconditional branch instruction

    2. Explain the 3-bus organization of a data path with a neat diagram.


    3. With a neat diagram explaining single bus processor data path wrt organization of
    computer and fundamental concepts.
    4. Write and explain the control sequence for execution of an unconditional branch
    instruction.
    5. Write a note on register transfer and ALU operation.
    6. Briefly explain fetching a word from memory and storing a word in memory.
    7. Explain in detail (i) Hazards and its types with examples (ii) pipeline performance (iii)role of
    cache in pipelining (iv)process of fetching a word from memory with diagram
    8. What is a stall or bubble in the pipeline? Explain in detail with example.

    Module 1 -Study any 7 Questions

    1. Simplify the following Boolean expressions, using four-variable K- maps and design using
    Nand and Nor gates.

    F (A, B, C, D) =AD' + B'C'D + BCD' + BC'D


    F(A, B, C, D) = πM(1, 2, 3, 7, 13, 15)
    F (w, x, y, z) = ϵm (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)

    2. Implement the following Boolean expressions, using Nand and Nor gates. F (x, y, z)
    = ∑ (0, 6,8,13,14) + d (1, 3, 10)
    3. Design the multiple-level NOR and NAND circuit for the following expression: F=CD (B
    + C) A + (BC' + DE')
    4. Demonstrate the validity of the following identities by means of truth tables: i. DeMorgan’s
    theorem for three variables: (x + y + z)' = x'y'z' and (xyz)' = x' + y' + z'
    ii. The distributive law: x (y + z) = xy + xz
    5. Design AND, OR, Xor and Invert using NAND and NOR gates
    6. Implement the following Boolean function F, using the two-level forms of logic (a)
    NAND-AND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR
    F (A, B, C, D) = ϵm (0, 4, 8, 9, 10, 11, 12, 14)
    7. Draw the logic diagram of the digital circuit specified by the following Verilog
    description:
    module Circuit_A (A, B, C, D, F);
    input A, B, C, D;
    output F;
    wire w, x, y, z, a, d;
    or (x, B, C, d);
    and (y, a, C);
    and (w, z, B);
    and (z, y, A);
    or (F, x, w);
    not (a, A);
    not (d, D);
    endmodule
    8. Explain Nand gate, Nor gate and Xor gate with truth table and timing diagram for three input
    variables a, b and c respectively.

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