CPEN 211: Computer Systems I

Slide Set 4:
Combinational Logic Building Blocks (1)

Instructor: Tor Aamodt

[Image: Roman Geometric Mosaic. There are some hardware combinational logic designs we use repeatedly, not unlike patterns found in art and nature
Slide Set #4
Source Wikipedia, By Mbellaccini - Own work, CC BY-SA 4.0, https://commons.wikimedia.org/w/index.php?curid=38150120] 1
 Learning Objectives
After this slide set you should be able to:
• Explain what a one-hot code is
• Explain the operation of the following
combinational building blocks and use them in
your own hardware designs :
– Decoder (binary to one-hot)
– Encoder (one-hot to binary)
– Multiplexer (select one of N)

Slide Set #4 2
Combinational Building Blocks
There are some combinational circuits that appear
very frequently. Makes sense to design these
“once” and then reuse them.

Learning these is also a great way to practice

translating from a logic diagram to Verilog and vis
versa.

Slide Set #4 3
Text: Dally §8
[image source: https://www.partsnotincluded.com/researching-time-circuit-led-displays/]

Slide Set #4 4
Example: Seven-Segment Decoder

0000 (“0”)
? 0111111
0001 (“1”) 0000110
0010 (“2”) 1011011
… …

Slide Set #4 5
 One-hot representation
• Represent a set of N elements with N bits
• Exactly one bit is set to 1 (all other bits are 0)
• Example – encode numbers 0-7:

Binary One-hot
000 00000001
001 00000010
010 00000100
… …
110 01000000
111 10000000

Slide Set #4 6
Text: Dally §8.2
• Suppose we are given a number in binary and
want to build a circuit that converts this to the
corresponding one-hot code.
• How might you design such a circuit?
• Write out the truth table then, for each
output bit draw a KMAP.
• However, this is such a common circuit, it has
a name…

Slide Set #4 7
 Decoder
• A decoder converts symbols from one code to another.
• A binary to one-hot decoder converts a symbol from
binary code to a one-hot code.
• Used to construct memory (return to see how later)

Binary input a to one-hot output b

Decoder
b[i] = 1 if a = i
(or b = 1<<a) a b
n m
n
m ≤ 2

Slide Set #4 8
Text: Dally §8.2
 Example of a Decoder
2 4 Decoder
a1 a0 b3 b2 b1 b0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

a1 a0 b0 a1 a0 b1
0 0 1 0 0 0
0 1 0 0 1 1
1 0 0 1 0 0
1 1 0 1 1 0

Slide Set #4 9
Text: Dally §8.2
 Example of a Decoder
2 4 Decoder

a1 a0 b3 b2 b1 b0 1 a[1]
0 0 0 0 0 1 1 a[0]
0 1 0 0 1 0
1 0 0 1 0 0 0
0 1
1 1 1 0 0 0 b[3]
1 1
1
b[2]
0 0
0
b[1] 0
1
0
b[0] 0
0
Slide Set #4 10
Text: Dally §8.2
 3:8 decoder
a(2)
a(1)
a(0)

a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 b(7)
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 ⁞ ⁞ ⁞ ⁞ ⁞ ⁞
0 1 0 0 0 0 0 0 1 0 0 b(2)
0 1 1 0 0 0 0 1 0 0 0
⁞ ⁞ b(1)
1 1 1 1 0 0 0 0 0 0 0
b[0]

Slide Set #4 11
 Encoder
• An encoder is an inverse of a decoder.
• Encoder is a logic module that converts a one-hot input signal to a
binary-encoded output signal.

a3

a2

a1

a0
• Example: a 4 2 encoder.
b1
a3 a2 a1 a0 b1 b0
0 0 0 1 0 0
b0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

b0 = a3 ∨ a1
b1 = a3 ∨ a2

Slide Set #4 12
Text: Dally §8.4
How to choose one of two different
inputs in a digital circuit?

Slide Set #4 13
 Multiplexer
• Often want to select one thing out of many possibilities.
• Example: Pick either A0 or A1 as input to module.
• Solution: Use a combinational logic block with three
inputs select, A0 and A1 where the value of select says
whether the output is equal to A0 or A1.
• So common, this circuit is given a name, “multiplexer” (or
“mux” for short):
A0
0
k b
Mux
A1 1
k
k Operation: If select is
zero then b = A0
select otherwise b = A1
01
Slide Set #4 14
Text: Dally §8.3
 Multiplexer Select Encoding

A0
k b
Mux
A1 k
k
select
• What is best encoding for “select”?
• Two common encodings:
Binary: select=0 means b=A0,
select=1 means b=A1
One hot: select=01 means b=A0
select=10 means b=A1
Slide Set #4 15
Text: Dally §8.3
Example: k-bit, 4 to 1 multiplexer with
one-hot select

If select = 0001, then b = a0

If select = 0010, then b = a1
If select = 0100, then b = a2
If select = 1000, then b = a3
Slide Set #4 16
 Multiplexer
• Multiplexer:
– n k-bit inputs
– n-bit one-hot select signal s
– Multiplexers are commonly used as data selectors

Selects one of n k-bit inputs

s must be one-hot
b=a[i] if s [i] = 1

Slide Set #4 17
Text: Dally §8.3
 Multiplexer (n=2,k=1)
s1 s0 A0 A1 b
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
A0
k1 0
0 1 1 1 1 b
Mux
1 0 0 0 0 A1 1
k1
1 0 0 1 1 k1
1 0 1 0 0 select
1 0 1 1 1

Question: How to build this

circuit out of gates?
Slide Set #4 18
Let’s design this multiplexer… s1 s0 A0 A1 b
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Slide Set #4 19
Multiplexer Implementation
k=1, n=4

1 0
0
1 0
0
1
1
1 1
0
0 0

Slide Set #4 20
Text: Dally §8.3
1-bit, 2-input One-Hot Select Mux
Symbol: Implementation with
AND and OR gates:
a0
Mux b a0
a1
s[0]
b
a1
s s[1]
2

Slide Set #4 21
2-bit, 3-input Mux
a0[0]
a0[1]

a1[0]
b[0]
a1[1]

a2[0]
a2[1]
a0
2
a1 b
Mux
2 2
a2 b[1]
2

s s[0]
3 s[1]
s[2]

Slide Set #4 22
 k-bit Binary-Select Multiplexer
Start with one hot select mux:

Selects one of n k-bit inputs

s must be one-hot
b=a[i] if s [i] = 1

Slide Set #4 23
Text: Dally §8.3
 1-bit, 4-input: Binary-Select Multiplexer

Add decoder: sb(1)

a0 sb(0)
k b
Mux
an-1 k
k

a3
Decoder

sb s
a b
m n
a2
b

k=1, m=2, n=4 a1

a[1]
a[0]

a0

3-input AND gates result from combining

b[3]

b[2]

b[1] two 2-input AND gates: one from decoder

Slide Set #4 24
b[0]
and one from one-hot select Mux. Text: Dally §8.3
 Recall: Tri-state inverter
e

a x

e=0, a=1

p-type
e a x
e=1 p-type
a=1 x=? 0 0 Z
e=0 0 1 Z
n-type
1 0 1
n-type 1 1 0

Slide Set #4 25
 Multiplexer Implementation
k=1, n=4

1 0
0
1 0
0
1
1
1 1
0
0 0

Tri-State Buffer
e

a x

Slide Set #4 26
Text: Dally §8.3
 Recall: Shannon Expansion
Can factor any Boolean function of n-inputs:
𝐹𝐹(𝑥𝑥0 , 𝑥𝑥1 , … , 𝑥𝑥𝑛𝑛−1 ) = 𝑥𝑥0 ∧ 𝐹𝐹 0, 𝑥𝑥1 , … , 𝑥𝑥𝑛𝑛−1 ∨ 𝑥𝑥0 ∧ 𝐹𝐹(1, 𝑥𝑥1 , … , 𝑥𝑥𝑛𝑛−1 )

For prime function (F=1 if 𝑥𝑥2 𝑥𝑥1 𝑥𝑥0 is prime or 1):

𝐹𝐹 𝑥𝑥0 , 𝑥𝑥1 , 𝑥𝑥2 = 𝑥𝑥2 ∧ 𝑥𝑥1 ∨ 𝑥𝑥0

E.g., Expand around 𝑥𝑥0

𝐹𝐹 𝑥𝑥0 , 𝑥𝑥1 , 𝑥𝑥2 = 𝑥𝑥0 ∧ 𝑥𝑥2 ∧ 𝑥𝑥1 ∨ 0 ∨ 𝑥𝑥0 ∧ 𝑥𝑥2 ∧ 𝑥𝑥1 ∨ 1
= 𝑥𝑥0 ∧ 𝑥𝑥2 ∧ 𝑥𝑥1 ∨ 𝑥𝑥0 ∧ 1

𝑥𝑥2 ∧ 𝑥𝑥1 0
is prime
1
1
1

𝑥𝑥0
Slide Set #4 27
Next, expand around 𝑥𝑥1 :
𝐹𝐹 𝑥𝑥0 , 𝑥𝑥1 , 𝑥𝑥2 = 𝑥𝑥0 ∧ 𝑥𝑥2 ∧ 𝑥𝑥1 ∨ 𝑥𝑥0 ∧ 1

= 𝑥𝑥1 ∧ 𝑥𝑥0 ∧ 𝑥𝑥2 ∧ 0 ∨ 𝑥𝑥0 ∧ 1 ∨ 𝑥𝑥1 ∧ 𝑥𝑥0 ∧ 𝑥𝑥2 ∧ 1 ∨ 𝑥𝑥0 ∧ 1

= 𝑥𝑥1 ∧ 𝑥𝑥0 ∧ 0 ∨ 𝑥𝑥1 ∧ 𝑥𝑥0 ∧ 1 ∨ 𝑥𝑥1 ∧ 𝑥𝑥0 ∧ 𝑥𝑥2 ∨ 𝑥𝑥1 ∧ 𝑥𝑥0 ∧ 1

0
0
1 1 isprime
x2 2
1 3
2

x1 x0
Slide Set #4 28
 Logic with Muxes
0
1
1 0
0
1
1 1 isprime
Muxb
isprime x2
0 2
1 1 3
0 2
1
3
x1 x0

x2 x1 x0

Slide Set #4 29
Text: Dally §8.3
What’s Inside an FPGA?

Slide Set #4 30
 What’s Inside an FPGA?
Basic Logic Gate: Lookup-Table
3
Inputs Truth table for isprime:

0
1
1
Bit-Stream
Muxb
1
(.sof file)
0
1
0
1

Function of each lookup table can be configured by shifting in bit-stream.

Lookup table is basically a hardware implementation of a “truth table”
storing the output for each different input in one of the rows.
Slide Set #4 31
 FPGA Logic Block:
Lookup Table
3
Inputs

Muxb

Mux selects between output of lookup table, or flip-flop

that connects to output of lookup table. Mux select input
Slide Set #4 32
is programmed by configuration bit-stream as well.
 What’s Inside an FPGA?
• Logic Block
Connection
Block

Switch Block

Routing Track
(Horizontal)

Routing Channel
(Vertical)
{
TILE
Slide Set #4 33
Reconfigurable Logic:

Connect Logic
Blocks using
Fixed Metal
Tracks and
Programmable
Switches

Slide Set #4 34
Memory

Slide Set #4 35
 Memory
• Memory is one of the most important structures inside a
computer (or any digital system)
• Memory is composed of large number of locations that
can be uniquely identified and can store a value
• “8 gigabytes (8GB)” means 8 billion memory locations*,
each containing 1 byte (8-bits) of information.
• Each location is uniquely identified by its “address”
• Total number of locations is called the “address space”
• Number of bits stored in each location is “addressability”
• Let’s look at a special type of memory called read-only
memory (ROM) – values cannot be modified

Slide Set #4 36
* Actually, 8 x 1024 x 1024 x 1024 = 8,589,934,592 locations
 Read-only memory (ROM)

address data
a ROM d
n m

Above ROM contains 2n (read-only) memory

locations each storing m-bits of data

Slide Set #4 37
Text: Dally §8.8
Example Read Only Memory (n=2, m=1)
Switch

Stored Data:
22 x 1-bit words

Simplified view (e.g., omits logic for controlling switches)

This memory stores 22 = 4 “words” where each word is 1-bit
Each address is 2-bits long.
Address space contains 4 locations.
Addressability is 1-bit. Slide Set #4 38
Example: n=2, m=1
“0” on “control input”
means switch “open”
“1” on “control input”
means switch “open”

Slide Set #4 39
Read-only memory (ROM) – internal structure

“Tri-state driver” – acts

Like a switch where input
on side of triangle is
“control input”.

Slide Set #4 40
Text: Dally §8.8
 2-D array implementation

Slide Set #4 41
Text: Dally §8.8
What’s Inside an FPGA? Continued…

FPGA vendors embed fixed blocks to improve speed

and density:
Embedded Memories
(blocks of 2K-18K)

To use these memory blocks we

Need to follow the coding
Style in the Quartus manual

Slide Set #4 42
 What’s Inside an FPGA?

FPGA vendors embed fixed blocks to improve speed

and density:
Embedded Memories
(blocks of 2K-18K)
Multiplier Blocks

Slide Set #4 43
 What’s Inside an FPGA?

FPGA vendors embed fixed blocks to improve speed and

density:

Embedded Memories
(blocks of 2K-18K)
Multiplier Blocks
High-Speed I/Os
Dedicated Clock Circuitry
CPU (eg. ARM Cortex-A9
in Cyclone V on DE1-SoC)

Slide Set #4 44
 Factoring
Many combinational blocks can be built up out
of multiple smaller versions of the same block

Slide Set #4 45
Example: 4-Input Binary Select
Multiplexer

Slide Set #4 46
Text: Dally §8.3
Example: 4-Input Binary Select
Multiplexer

Slide Set #4 47
Text: Dally §8.3
 Designing A Large Encoder – 164
from five 42s
First, encode lower 2 bits.
Next, want to encode upper 2 bits. Can do that with an
encoder where input is one hot vector summarizing which
encoder has a one on input.
0 High bits
a[15:12] 2 Low bits

4:2
0000
15 14 13 12 4 00
0
a[11:8] 2 0 b[3:2]

4:2
0000
4:2
0
11 10 9 8 4 00 1 2 01
One hot 0
input 1
a[7:4] 2
0010
4:2

7654 4 01
0
b[1:0]
4:2

0000 a[3:0]
2 01
3210 4 00 2

Slide Set #4 48
Text: Dally §8.4
 Example: Larger Decoders
• Decoders used for constructing memory are
LARGE (e.g., 6:64, 7:128, etc…)
• Building large decoder using same approach
as for 2:4 and 3:8 is inefficient
• Want to build a large decoder using fewer
transistors

Slide Set #4 49
• Don’t freak out if you don’t understand the
next ~15 slides. You will do fine in this course
even if you don’t get this example.

• It is however a useful and “interesting”

example

Slide Set #4 50
 Reconsider 2:4 Decoder

a[1]
a[0]
yb

Truth Table y1 y0
yb y1 y0 b[3]

0 0 1
b[2]
1 1 0

b[1]
A 1:2 decoder!
b[0]

Slide Set #4 51
Text: Dally §8.2
 Reconsider 2:4 Decoder
• 2:4 decoder can be built
out of two 1:2 decoders xb a[1]
combined using four AND a[0]
gates. yb
• One AND gate for each
output. x1 x0 y1 y0
b[3]
• How to extend to larger
decoders? b[2]
• Hard part: Knowing which
small decoder outputs to b[1]
AND together.
b[0]

Slide Set #4 52
Text: Dally §8.2
 Geometric Interpretation: Big picture
• Divide input bus into N smaller busses such that every
input wire is part of just one of the smaller buses
• Any input bus value has a corresponding set of values
assigned to each of the N smaller busses.
• Let the smaller busses specify positions in an N-
dimensional space. Notice: Each point in this space
corresponds to just one input value.
• Let each decoder output be represented by one of
these positions.
• Use AND gate to verify each of the N smaller busses
has the value that corresponds to this output.
• Simplify AND gate inputs by using one-hot code.
Slide Set #4 53
2:4 Decoder Geometric Interpretation
• (xb,yb) specify coordinate in Euclidean space:

yb

0
0 1
xb
• The 2:4 decoder output that has value of 1
indicates which point (xb,yb) corresponds to.
Slide Set #4 54
Text: Dally §8.2
2:4 Decoder Geometric Interpretation
• (xb,yb) specify coordinate in Euclidean space:

Decoder
1 0
{xb,yb}=002 a b
0
yb 1

0
0 1
xb
• The 2:4 decoder output that has value of 1
indicates which point (xb,yb) corresponds to.
Slide Set #4 55
Text: Dally §8.2
2:4 Decoder Geometric Interpretation
• (xb,yb) specify coordinate in Euclidean space:

Decoder
1 0
{xb,yb}=012 a b
1
yb 0

0
0 1
xb
• The 2:4 decoder output that has value of 1
indicates which point (xb,yb) corresponds to.
Slide Set #4 56
Text: Dally §8.2
2:4 Decoder Geometric Interpretation
• (xb,yb) specify coordinate in Euclidean space:

Decoder
1 1
{xb,yb}=102 a b
0
yb 0

0
0 1
xb
• The 2:4 decoder output that has value of 1
indicates which point (xb,yb) corresponds to.
Slide Set #4 57
Text: Dally §8.2
2:4 Decoder Geometric Interpretation
• (xb,yb) specify coordinate in Euclidean space:

Decoder
1 0
{xb,yb}=112 a b
0
yb 0

0
0 1
xb
• The 2:4 decoder output that has value of 1
indicates which point (xb,yb) corresponds to.
Slide Set #4 58
Text: Dally §8.2
2:4 Decoder Geometric Interpretation
• (x1,x0) is one-hot code indicating x value
• (y1,y0) is one-hot code indicating y value

y1=1

yb
y0=1
x0=1 x1=1
xb

Slide Set #4 59
Text: Dally §8.2
2:4 Decoder Geometric Interpretation
• (x1,x0) is one-hot code indicating x-dimension
• (y1,y0) is one-hot code indicating y-dimension

Decoder
0
{xb,yb}=002 a b
0
yb 1
y0=1
x0=1
xb

• b[0] is 1 when x0 = 1 AND y0 = 1

• Same as “b0 = x0 ⋀ y0”
010 002 Text: Dally §8.2
60
2:4 Decoder Geometric Interpretation
• (x1,x0) is one-hot code indicating x-dimension
• (y1,y0) is one-hot code indicating y-dimension

Decoder
y1=1 0
{xb,yb}=012 a b
1
yb 0

x0=1
xb

• b[1] is 1 when x0 = 1 AND y1 = 1

• Same as “b1 = x0 ⋀ y1;”
110 012 Text: Dally §8.2
61
2:4 Decoder Geometric Interpretation
• (x1,x0) is one-hot code indicating x-dimension
• (y1,y0) is one-hot code indicating y-dimension

Decoder
1
{xb,yb}=102 a b
0
yb 0
y0=1
x1=1
xb

• b[2] is 1 when x1 = 1 AND y0 = 1

• Same as “b2 = x1 ⋀ y0;”
210 102 Text: Dally §8.2
62
2:4 Decoder Geometric Interpretation
• (x1,x0) is one-hot code indicating x-dimension
• (y1,y0) is one-hot code indicating y-dimension

Decoder
y1=1 0
{xb,yb}=112 a b
0
yb 0

x1=1
xb

• b[3] is 1 when x1 = 1 AND y1 = 1

• Same as “b3 = x1 ⋀ y1;”
310 112 Text: Dally §8.2
63
6:64 Decoder Geometric Interpretation
• Build 6  64 decoder from three 2  4 decoders
• Think of each bit of output as one point in a cube
• Each 24 decodes 2 bits of input “a” z
• a[5:4]x[3:0]
• a[3:2]y[3:0] 3
2
• a[1:0]z[3:0] y
1
Example: input a = 011010 0 1 2
3 x
a5 a4 x3 x2 x1 x0 a3 a2 y3 y2 y1 y0 a1 a0 z3 z2 z1 z0
0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0
1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0
1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0
Slide Set #4 64
Text: Dally §8.2
2-Stage decoder

Slide Set #4 65
Text: Dally §8.2
 Advantage Of Dividing Large Decoder

• 6->64 decoder requires:

– 64 6-input AND gates (384 inputs)
• 6->64 decoder using 2->4 decoders requires:
– 12 2-input AND gates (24 inputs)
– 64 3-input AND gates (192 inputs)
• Faster, smaller, lower power

Slide Set #4 66
Text: Dally §8.2
 Summary
• We learned about three combinational logic
building blocks: decoder, encoder, mux
• We saw how to design them using truth tables
and optimize them using Boolean algebra
• Learned how an FPGA works
• Saw how a read-only-memory works.
• Saw how to build larger building blocks out of
smaller building blocks.
Slide Set #4 67