Getting familiar with internal architecture of a basic

computer processor (16-bits).

2
3
- Letters (capital) - numbers
- Start letters
- Examples:
R1
R2
DR

AC(H) AC(L)
4
1. General Purpose: R1, R2, R3

2. Specific Purpose:
- AC (accumulator: data)
- DR (data register: data)
- PC (program counter) points to the address of
the next instruction)

5
 RTL is a symbolic notation that is considered a type
of hardware description language (HDL).
 Easily describes register operations within processor
- register transfer operation
- sequence
- control

6
Basic RTL symbols:
Symbols Description Examples
Capital letters and
Denotes a register MAR, R1, R2
numbers
Subscript Denotes a bit of a register A2, B6, …...
Parentheses () Denotes a part of a register R2(0-7), PC(L)
Arrow ← Denotes transfer of information A←B
Colon : Terminates a control function X T0 :
Comma , Separates two micro-operations D ← C, B ← A
Specify an address for memory
Square brackets [ ] R1 ← M[AR]
transfer
7
Normally, we want the operation to occur under a
predetermined control condition.

Example:

If (K1==1) then ( copy contents of R1 to R2)

K1: R2  R1 //RTL

8
Show the block diagram that implements the
following RTL statements: K1: R2  R1

(a) Block diagram (b) Timing diagram

Transfer from R1 to R2 when K1 =1

9
 K1: R2  R1

Given that R1= 34 h and R2=AB h, what will be the

contents of each register after the execution of the
above RTL statement?

10
Show the block diagram that implements the
following RTL statements: X+Y: R5  R3 + R4

11
Microoperation: an elementary operation
performed on the information stored in one or
more registers within one clock cycle.

12
Can two microoperations be performed at the
same time?? e.g. R1 R2, R1 R4??

13
RTL statements cannot have the same destination.

Example: State whether the following statements are

VALID or INVALID.
a) R1  R2, R3 R1 + R2
b) R1  R1 + 1, R2  R3
c) R1 R2, R1  R3

14
Show the block diagram that implements the
following RTL statements:
X+YZ: R1  R1 + R2, R3  R2

15
Write the RTL statements for the shown block diagram
in fig. 2. Then draw the corresponding logic diagram.

K1 K2 RTL Statement

0 0

0 1

1 0

1 1

Block diagram

16
Write the RTL statements for the shown block
diagram. Then draw the corresponding logic diagram.
Note that the load will
be zero for the first
operation

Block diagram

17
The logic diagram of Example 4
18
Memory Transfer
19
Memory is typically determined using two parameter:
 Number of memory locations >>
 Size of each memory location >>
Address:
0
1
Example: 8x4 2
3
4
5
6
7 20
a) Address bus: ?? bits b) Address bus: ?? bits c) Address bus: ?? bits

K address bits
?? Memory locations
M≤ 2^k

21
Given the following memories, what will be the size of
the data and address buses?

Data Bus Address Bus

a) 32 x 16
b) 1k x 8
c) 4M x 32

22
Assume a CPU has a 24 bit address bus, what is the
largest memory size that this MP can access?

a) 4MB
b) 4GB Draft:
c) 16MB
d) 16GB
e) Not mentioned

23
1. WRITE: store data into the memory
W: M ← DR

2. READ: read data from the memory

R: DR ← M
Notes:
- All memory access operations require specifying the
address to be accessed.
- Memory addresses are typically stored in the address
register (AR) or (MAR).
24
25
 Memory operations (Fig.4.9)

Read
AR
Memory
unit Write

DR

Memory unit that communicates with two external registers

26
Show the block diagram that implements the
following RTL statement: T1: M[AR]  R1

27
Show the block diagram that implements the
following RTL statement: T1: M[AR]  R1

R1 AR

MEMORY

28
Show the block diagram that implements the
following RTL statement: T2: R2  M[AR]

29
Show the block diagram that implements the
following RTL statement: T2: R2  M[AR]

R2 AR

MEMORY

30
R1=1212H R2= 4455H AR=345H
[345H] = 5555H [1212H]=7777H
Show how the memory and registers will change after
the following independent RTL statements:
a) R1  M[AR] >>

b) M[AR]  R2 + 1 >>

31
Common Bus system
32
How many connections are needed to connect
four registers? >>

R3 R0

R2 R1

33
How many connections are needed to connect
four registers? >>

R3 R0

R2 R1

𝑵𝑵(𝑵𝑵 − 𝟏𝟏) 𝟑𝟑
= 𝟒𝟒. = 𝟔𝟔
𝟐𝟐 𝟐𝟐
𝑵𝑵 𝒊𝒊𝒊𝒊 𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏 𝒐𝒐𝒐𝒐 𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓𝒓
34
 Computer processors typically include many registers.

 Direct connection between each register and all others

will result in excessive wiring connections.

 A more efficient scheme is to use a common bus system.

R3 R2 R1 R0

Example: R1  R3
35
 WRTIE TO BUS READ FROM BUS
R1  R3 R1  R3

Choose one of many? Store to specific

 register?

36
 A common bus consists of set of common lines,
one for each bit of a register, though which binary
information is transferred one at a time.
 Control signals determine which register is
selected by the bus during each particular register
transfer. One way of selecting a common bus
system is with multiplexers.

37
 BIT3 BIT2 BIT1 BIT0

D3 C3 B3 A3

D C B A
38
 S3 S2 Register
0 0 A
0 1 B
1 0 C
1 1 D

D C B A

Y3 Y2 Y1 Y0

2X4 DECODER

S3 S2 39
S3 S2 40
 Bus Transfer (Continued)

Register Decoder MUX

Transfer Select Select
Language Lines Lines
Statement S3 S2 S1 S0

R0 ← R3 0 0 1 1

R1 ← R2 0 1 1 0

R3 ← R1 1 1 0 1

R2 ← R0 1 0 0 0

40
For the common bus system in the previous figure,
determine the control signals S0, S1, S2 and S3 that
implement the following RTL statements:
a) A← D
b) B← C
c) D← B
d) C← A

42
 Decoder Select Lines MUX Select Lines
RTL S3 S2 S1 S0
A← D
B← C
D← B
C← A

43
 Decoder Select Lines MUX Select Lines
RTL S3 S2 S1 S0
A← D 0 0 1 1

B← C 0 1 1 0

D← B 1 1 0 1

C← A 1 0 0 0

44
Complete the table to show the select lines required to execute the
following RTL statements:

a) M[A1]  B2
b) B0  M[A3]
c) B1  M[A2]
d) M[A0]  B3

45
Complete the table to show the select lines required to execute the
following RTL statements: Address Registers

a) M[A1]  B2
b) B0  M[A3]
c) B1  M[A2] BUS
d) M[A0]  B3

46
 Memory Control MUX_2 Select MUX_1 Select Decoder Select
RTL Statement Lines Lines Lines Lines
Read Write S5 S4 S3 S2 S1 S0
M[A1] ← B2
B0 ← M[A3]
B1 ← M[A2]
M[A0] ← B3

47
 Memory Control MUX_2 Select MUX_1 Select Decoder Select
RTL Statement Lines Lines Lines Lines
Read Write S5 S4 S3 S2 S1 S0
M[A1] ← B2 0 1 0 1 1 0 - -
B0 ← M[A3] 1 0 1 1 - - 0 0
B1 ← M[A2] 1 0 1 0 - - 0 1
M[A0] ← B3 0 1 0 0 1 1 - -

48
//to bus
 Size of mux=
 #muxes =

//from bus:
 Decoder size =

49
//to bus
 Size of mux=
 #muxes =

//from bus:
 Decoder size =

50
//to bus
 Size of mux= # registers x 1
 #muxes = register size

//from bus
 Decoder size = log2(# registers) x # registers

51
Assume a common bus system has 16 registers, each
of size 8 bits. Find:
- Mux size: 16X1

- Number of muxes: 8

- Decoder size: 4X16

52
Assume a common bus system has 32 registers, each
of size 64 bits. Find:
- Mux size: ..

- Number of muxes: ..

- Decoder size: ..

53
 A bus system can be constructed with three-state
buffer gates instead of multiplexers
 A three-state buffer is a digital circuit that exhibits
three states: logic-0, logic-1, and high-impedance
(Hi-Z)
Control input C

Normal input A Output B

Three-State Buffer

54
 C=1

Buffer
A B A B

C=0

Open Circuit
A B A B

55
 S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state

buffer (replaces MUX0 in the
previous diagram) D0

56
57
1. Arithmetic Operations
a. Add/subtract
b. Increment

2. Logic Operations
a. Simple Logic
b. Shift/Circulate operations

58
59
i. Logical Shift
ii. Circulate
iii. Arithmetic Shift

60
 LEFT

RIGHT

61
LEFT

RIGHT

62
 LEFT

RIGHT

63
64
Assume A= 1101b

- SHL A =
- SHR A =

- CIL A =
- CIR A =

- ASHL A =
- ASHR A =
65
 Logical shifts / Circulate are used for data transfer.
 Arithmetic shifts can rapidly multiply or divide signed numbers
by powers of two.

 The result of a Arithmetic Right Shift operation is a division by

2n , where n is the number of shifted bit positions.

 The result of a Arithmetic left Shift operation is a multiplication

by 2n , where n is the number of shifted bit positions.

66
Example:
 If we have the binary number 01110101 (117 decimal) and we
perform arithmetic right shift by 1 bit we get the binary
number 00111010 (58 decimal). So we have divided the original
number by 2.
 If we have the binary number 1010 (-6 decimal) and we
perform arithmetic right shift by 1 bit we get the binary
number 1101 (-3 decimal). So we have divided the original
negative number by 2.
 Note: The examples above use two’s complement
representation.

67
 EXAMPLES

B= 0010b // 2 decimal
ASHL B =
ASHR B =

C= 1100B //
ASHL C=
ASHR C =

68
ASHL multiplication can result in
a number that is too large to be
properly stored in the designated
register.  overflow

e.g. 4x2 or -8x2 using 4-bit regs.

69
 R1 = 95H, R2 = 89H, R3 = 93H.
Determine the values in each register (hexadecimal) after
executing each of the following microoperations.
a) R1  SHL R1
Draft:
>> R1=
b) R2  R3 AND R2
>> R1=
c) R3  CIR R3
>> R1=
d) R2  R1 XOR R3
>> R1=
70
 MSB LSB
S H3 H2 H1 H0

SHR 0 IR A3 A2 A1

SHL 1 A2 A1 A0 IL

71
 A: A3 A2 A1 A0

?? ?? ?? ?? ?? ?? ?? ??

S
MUX3 MUX2 MUX1 MUX0

H3 H2 H1 H0
72
Arithmetic Microoperation
• The basic arithmetic microoperations as listed in the following Table:
Addition - Subtraction - Increment - Decrement.

Summary of Typical Arithmetic Micro-Operations

R3 ← R1 + R2 Contents of R1 plus R2 transferred to R3

R3 ← R1 - R2 Contents of R1 minus R2 transferred to R3
R2 ← R2’ Complement the contents of R2
R2 ← R2’+ 1 2's complement the contents of R2 (negate)
R3 ← R1 + R2’+ 1 subtraction
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement

• Add Microoperation R3 ← R1 + R2 is done by using Adder

• Subtract Microoperation R3 ← R1 – R2
is done by using the Adder and 2’s complement of R2 as follow
R3 ← R1 + R2’ + 1

74
Arithmetic Microoperation (Continued)
Adder/Subtractor:
• The subtraction of binary numbers can be done most conveniently by
means of 2’s complement as shown in the following Figure by including an
XOR gate with each full Adder
• When Sub/Add = 1 : S = A + B’ + 1 = A – B
Sub/Add = 0 : S=A+B

4-bit Adder-Subtractor unit

75
Arithmetic Microoperation (Continued)
Arithmetic unit
• Consider the circuit shown in Fig.4.12, the output of the binary adder
is calculated as: F = A + B + Cin
• It is possible to generate 8 arithmetic microoperations

S1 S0 Cin Y Output Microoperation

0 0 0 B F=A+B Add
0 0 1 B F=A+B+1 Add with carry
0 1 0 B’ F = A + B’ Subtract with borrow
0 1 1 B’ F = A + B’+ 1 Subtract
1 0 0 0 F=A Transfer A
1 0 1 0 F=A+1 Increment A
1 1 0 1 F=A-1 Decrement A
1 1 1 1 F=A Transfer A

76
Arithmetic Microoperation (Continued)
S1
S0

A0 X0 C0

S1 F0
S0
FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1

S1 F1
FA
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 F2
S0
FA
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3

S1 F3
S0
FA
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1

77
Design the arithmetic circuit that performs the following
operations:

S1 S0 Output Operation
0 0 D=A+B Add
0 1 D=A-B Subtract
1 0 D=A Transfer A
1 1 D=A +1 Increment A

77
Design an ALU circuit to perform the following
operations:
Control Control
Function Operation Function Operation
S2 S1 S0 S2 S1 S0
0 0 0 F = A + B. Addition 1 0 0 F = 𝐴𝐴 ⊕ 𝐵𝐵 XOR
0 0 1 F=A-B Subtraction 1 0 1 F = 𝐴𝐴 + 𝐵𝐵 OR
0 1 0 F=A Transfer 1 1 0 F = 𝐴𝐴̅ Complement
0 1 1 F = A +1 Increment 1 1 1 F= AB AND

78
Design 4-bit ALU that performs the indicated four arithmetic operations
and four logical operations via three control inputs (S2, S1, S0)
according the following table:

A3 A2 A1 A0 B3 B2 B1 B0
S2
S1
Arithmetic and Logical Unit S0
Cout Cin

F4 F3 F2 F1 79
Arithmetic Logic Shift Unit
• The arithmetic, logic and shift circuits introduced in the previous
sections can be combined into one ALU with common selection
variables one stage of this unit.

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A
0 0 0 1 0 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F=A-1 Decrement A
0 0 1 1 1 F=A Transfer A
0 1 0 0 X F=A∧B AND
0 1 0 1 X F=A∨B OR
0 1 1 0 X F=A⊕B XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F
Function Table for Arithmetic Logic Shift Unit

80
Arithmetic Logic (Continue)

S3
S2 Ci
S1
S0

F A
Arithmetic i

Circuit
Select

0 4x1 Fi
C i+1 1 MUX
2
3
F
Logic Li
Bi
Circuit
A
i
shr
A i-1
shl
A

One stage of arithmetic logic shift unit

81
Design of an arithmetic unit

𝐅𝐅 = 𝐀𝐀 + 𝐲𝐲 + 𝐂𝐂𝐂𝐂𝐂𝐂

82
Arithmetic unit (Cont.)

83
Arithmetic unit (Cont.)

84
Arithmetic unit (Cont.)

85
Arithmetic unit (Cont.)

86